Chip and processing method thereof

Abstract

The invention discloses a chip and a processing method thereof, and belongs to the field of chips, and the processing method comprises the steps: providing a first substrate, the first substrate is provided with a first cutting channel region, and a first binding surface is formed on the first surface of the first substrate; cutting in a first cutting channel area on the first surface of the first substrate to form a first channel, wherein the depth of the first channel is smaller than the thickness of the first substrate; a second substrate is provided, the second substrate is provided with a second cutting channel area, and a second binding face is formed on the first surface of the second substrate; the first binding face and the second binding face are bound, and the first cutting channel area and the second cutting channel area are aligned; cutting in a second cutting channel area of the second substrate to form a second channel, wherein the second channel penetrates through the second substrate; a third channel is formed in the first cutting channel area of the first substrate in a cutting mode so that the third channel can be communicated with the first channel, and the width of the first channel is larger than or equal to that of the third channel. The technical effect of improving the cutting quality of the chip is achieved.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a chip and a processing method thereof. Background Art

[0002] Silicon-based OLED (Organic Light-Emitting Diode) has excellent display effects due to its high resolution and high refresh rate, and is widely used in AR (Augmented Reality) and VR (Virtual Reality) devices. The production process of silicon-based OLED includes a cutting process, and the current cutting method will leave some raw materials, affecting the cutting quality, and easily causing yield loss and strength failure in the subsequent module process. Summary of the invention

[0003] The main purpose of the present invention is to provide a chip and a processing method thereof, aiming to solve the technical problem that part of the raw materials remain in the current cutting method, affecting the cutting quality, improving the yield in the subsequent module process, and reducing strength failure.

[0004] To achieve the above object, the present invention provides a chip processing method, comprising:

[0005] Providing a first substrate, wherein the first substrate is provided with a first scribe line area, and a first bonding surface is formed on a first surface of the first substrate;

[0006] Cutting a first trench in the first cutting line region on the first surface of the first substrate, wherein the depth of the first trench is less than the thickness of the first substrate;

[0007] Providing a second substrate, wherein the second substrate is provided with a second cutting line area, and a second bonding surface is formed on a first surface of the second substrate;

[0008] Laminating the first laminating surface of the first substrate with the second laminating surface of the second substrate, wherein the first cutting line area is aligned with the second cutting line area;

[0009] Cutting a second channel in the second cutting line region of the second substrate located on the side surface opposite to the second bonding surface, wherein the second channel penetrates the second substrate;

[0010] A third channel is cut in the first cutting line region of the first substrate on the side surface opposite to the first bonding surface so that the third channel communicates with the first channel, and the width of the first channel is greater than or equal to the width of the third channel.

[0011] In one embodiment, the first substrate is a glass substrate, and the second substrate is a silicon substrate.

[0012] In one embodiment, the depth of the first trench is 20-50 μm.

[0013] In one embodiment, the width of the second channel is equal to the width of the third channel.

[0014] In one embodiment, an alignment accuracy between the first scribe line region and the second scribe line region is less than or equal to 5 μm.

[0015] In one embodiment, the cutting depth of the second trench exceeds the first surface of the second substrate by 10-20 μm.

[0016] In one embodiment, the cutting depth of the third trench exceeds the inner trench surface of the first trench by 10-20 μm.

[0017] In one embodiment, before the step of cutting and forming a first trench in a first cutting line region of the first substrate located on one side of the first bonding surface, the step further includes:

[0018] A positioning mark is processed on one side of the first bonding surface of the first substrate or on the side opposite to the first bonding surface.

[0019] In one embodiment, the shape of the positioning mark includes at least one of a cross, a square and a circle.

[0020] In addition, to achieve the above-mentioned purpose, the present invention also provides a chip, which includes a first substrate and a second substrate, the first surface of the first substrate forms a first bonding surface, the first surface of the second substrate forms a second bonding surface, the first bonding surface and the second bonding surface are bonded to each other, and the first surface of the first substrate has a notch on at least part of its edge.

[0021] The chip processing method disclosed in the present invention comprises the following steps: firstly providing a first substrate, wherein the first substrate is provided with a first cutting path area, and a first bonding surface is formed on the first surface of the first substrate, the first cutting path area is an area reserved for cutting of the first substrate, and the first bonding surface is used for bonding; a first groove is formed by cutting in the first cutting path area of ​​the first surface of the first substrate, the depth of the first groove is less than the thickness of the first substrate, and the first groove cut out before the bonding process does not affect the strength of the first substrate; providing a second substrate, wherein the second substrate is provided with a second cutting path area, and a second bonding surface is formed on the first surface of the second substrate, the second cutting path area is an area reserved for cutting of the second substrate, and the second bonding surface can be used for bonding with the first substrate; bonding the first bonding surface of the first substrate and the second bonding surface of the second substrate, wherein the first cutting path area is aligned with the second cutting path area, and the areas to be cut of the first substrate and the second substrate are aligned through the bonding process, so as to facilitate subsequent cutting to form a chip; A second channel is formed by cutting in the second cutting path area on the side surface opposite to the bonding surface, and the second channel penetrates the second substrate. The penetrated second channel can separate the areas corresponding to each chip in the second substrate. Due to the existence of the first channel, the cutting depth of the second cutting path can be slightly greater than the thickness of the second substrate, which is easier to achieve penetration without having to reserve part of the raw material to avoid damage to the first substrate; a third channel is formed by cutting in the first cutting path area on the side surface opposite to the first bonding surface of the first substrate, so that the first channel and the third channel are connected, and the width of the first channel is greater than or equal to the width of the third channel. The connected first channel and the third channel can separate the areas corresponding to each chip in the first substrate. Due to the existence of the first channel, it is easier to achieve through-cutting of the first substrate by cutting from the side opposite to the first bonding surface to the first bonding surface, and the width of the first channel is greater than or equal to the width of the third channel. After the first substrate is through-cut, the raw material close to the first bonding surface will not protrude to the outside of the chip, thereby avoiding the falling of debris from the protruding part. Therefore, the embodiment of the present invention opens a trench in the first substrate before the bonding process to avoid damage to the substrate material during the slicing process. This can reduce problems such as glass scratches caused by falling substrate material debris during the subsequent module process and improve cutting quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present drawings or related technologies, the drawings required for use in the embodiments or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present drawings. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0023] Figure 1 It is a schematic diagram of the product structure after a chip is cut and processed in the related technology;

[0024] Figure 2 It is a schematic diagram of the structure of another product after chip cutting and processing in the related art;

[0025] Figure 3 A schematic diagram of processing positioning marks in an embodiment of the present invention;

[0026] Figure 4 A top view of the first substrate after the first trench is processed in an embodiment of the present invention;

[0027] Figure 5 The cross-sectional schematic diagram of the embodiment of the present invention after the first channel is processed;

[0028] Figure 6 is a schematic diagram of bonding the first substrate and the second substrate in an embodiment of the present invention;

[0029] Figure 7 The cross-sectional schematic diagram of the embodiment of the present invention after the second channel is processed;

[0030] Figure 8 The cross-sectional schematic diagram of the embodiment of the present invention after the third channel is processed;

[0031] Fig. 9 The figure is a schematic diagram of the structure of a chip according to an embodiment of the present invention.

[0032] Description of reference numerals:

[0033] 100, a first substrate; 110, a first channel; 120, a third channel;

[0034] 200, a second substrate; 210, a second channel;

[0035] 300, OCR glue; 400, filler;

[0036] 500, chip; 501, first substrate; 502, second substrate; 503, notch;

[0037] A1, first surface of the first substrate; A2, side surface opposite to the first bonding surface; A3, first surface of the second substrate; A4, side surface opposite to the second bonding surface;

[0038] P1, first cutting line area; P2, second cutting line area;

[0039] K1, soft knife No. 1; K2, hard knife; K3, soft knife No. 2.

[0040] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0041] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0042] Hereinafter, the embodiments of the chip and the processing method thereof of the present invention are specifically disclosed in detail with appropriate reference to the accompanying drawings. However, there may be cases where unnecessary detailed descriptions are omitted. For example, there may be cases where detailed descriptions of well-known matters and repeated descriptions of actually the same structures are omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate the understanding of those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the present invention and are not intended to limit the subject matter described in the claims.

[0043] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the technical solutions of the present invention are further described below in conjunction with the accompanying drawings and embodiments. However, the present invention is not limited to the embodiments listed, and should also include any other known changes within the scope of the rights claimed by the present invention.

[0044] It should be noted that if there are directional indications (such as up, down, left, right, front, and back) in the embodiments of the present invention, the directional indications are only used to explain the relative positional relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, if there are descriptions of "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features.

[0045] Silicon-based OLED can be composed of a double-layer structure of Wafer (silicon wafer) + Glass. The two-layer structure is made of different materials and requires different cutting methods to complete the cutting process. Different cutting methods will have some residues of Wafer and Glass, affecting the cutting quality, which is easy to cause yield loss and strength failure in subsequent module processes.

[0046] Figure 1 The schematic diagram of the product structure after a chip cutting process in the related technology. Wafer and Glass are first bonded together, and then different cutting methods are used to cut Wafer and Glass into the set shape of the chip. Due to the limitation of the cutting process accuracy, it is impossible to achieve complete through-cutting in the cutting area. Wafer and Glass will retain part of the material on the cross section of the product, forming Figure 1 Product structure shown. Figure 2This is another schematic diagram of the product structure after chip cutting in the related technology. Wafer and Glass are also first bonded, and Glass and Wafer form different structures. After the Glass part is cut with a knife wheel, surface damage and glass fragments fall off, and the Wafer part still has the problem of cross-section material retention. The cutting quality of these two product structures is relatively low.

[0047] Based on this, an embodiment of the present invention provides a chip processing method. In this embodiment, the chip processing method includes:

[0048] Step S10, providing a first substrate 100, wherein the first substrate 100 is provided with a first scribe line area P1, and a first surface A1 of the first substrate is formed with a first bonding surface;

[0049] It can be understood that this embodiment can be applied to micro display chips with a double-layer structure, including silicon-based OLED chips and Micro-LED chips. The first substrate 100 refers to one of the base layers in the double-layer structure of the micro display chip, and the other base layer is the second substrate 200. The first cutting road area P1 refers to the area divided in the first substrate 100 for cutting slices. The first surface A1 of the first substrate refers to a side surface of the first substrate 100 used for the bonding process. Adhesives and other substances are attached to the first surface A1 of the first substrate to form a first bonding surface for bonding. In a feasible embodiment, the first substrate 100 is a glass substrate.

[0050] Step S20, cutting and forming a first trench 110 in a first scribe line region P1 of the first surface A1 of the first substrate, wherein the depth of the first trench 110 is less than the thickness of the first substrate 100;

[0051] The first trench 110 refers to a trench formed by cutting on the first substrate 100 before the bonding process. The depth of the first trench 110 is less than the thickness of the first substrate 100. The depth of the first trench 110 can be selected according to actual conditions without affecting the bonding strength of the first substrate 100. The cutting depth of the first trench 110 can also be selected according to the thickness of the first substrate 100. For example, 20-30% of the thickness of the first substrate 100 is selected as the cutting depth.

[0052] In a feasible implementation, before step S20, the process further includes: processing a positioning mark 120 on the first surface A1 of the first substrate or the side surface A2 opposite to the first bonding surface. The positioning mark 120 can be used for positioning in the bonding or cutting process. It is understandable that the positioning mark 120 can be processed on both surfaces of the first substrate 100. Figure 3 Schematic diagram of processing positioning marks in this embodiment, such as Figure 3As shown, the shape of the positioning mark 120 includes at least one of a cross, a square and a circle. The positioning mark 120 may appear in pairs and be arranged at the edge of the first substrate 100. The size of the positioning mark 120 may be adjusted according to actual conditions. The processing method of the positioning mark 120 may include laser engraving.

[0053] Figure 4 This is a top view of the first substrate 100 after the first trench 110 is processed in this embodiment, as shown in FIG. Figure 4 As shown, the first channels 110 are arranged at a certain interval, and the positions of the first channels 110 can be used as reference positions for slicing in subsequent processes. Figure 5 FIG. 1 is a cross-sectional schematic diagram of the embodiment after the first channel 110 is processed. Figure 5 As shown, the area of ​​the first substrate 100 indicated between two adjacent dotted lines with a smaller spacing is the location of the first scribe line area P1, the area between the first scribe line areas P1 is the location of the chip Chip, and the first channel 110 is located in the center of the first scribe line area P1.

[0054] It is understandable that the cutting process in this embodiment can use a grinding wheel blade as a cutting tool. Different cutting processes have different requirements for the cutting process, and grinding wheel blades of different hardness and size can also be used. In the process of cutting the first groove 110, for the first substrate 100 made of glass material, a soft knife No. 1 K1 can be selected as a cutting tool. The Kerf value of the soft knife No. 1 K1 determines the width of the first groove 110. According to the required groove width, a grinding wheel blade with a suitable Kerf value can be selected as the soft knife No. 1 K1.

[0055] In a feasible embodiment, the depth of the first trench 110 is 20-50 μm, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. It is understandable that the cutter cuts the surface of the first substrate 100, and the amount of feed affects the depth of the formed first trench 100. If the depth of the first trench 110 is too shallow, the amount of feed is difficult to control, and the first substrate 100 is easily damaged during the subsequent through-cutting of the second substrate 200. If the depth of the first trench 110 is too deep, it will affect the bonding strength of the first substrate 100. Controlling the depth of the first trench 110 within a suitable range can ensure the bonding strength of the first substrate 100 and make it easy to control the cutter.

[0056] Step S30, providing a second substrate 200, wherein the second substrate 200 is provided with a second scribe line area P2, and a second bonding surface is formed on the first surface A3 of the second substrate;

[0057] The second cutting line area P2 refers to the area divided in the second substrate 200 for cutting and slicing. The first surface A3 of the second substrate refers to a side surface of the second substrate 200 used for the bonding process. Adhesives and other materials are attached to the first surface A3 of the second substrate to form a second bonding surface for bonding. The first substrate 100 and the second substrate 200 can be made of different materials.

[0058] In a feasible embodiment, the second substrate 200 is a silicon substrate. It is understandable that the glass substrate and the silicon substrate are made of different materials and have different physical properties, and different cutting processes can be used for cutting. The hardness of the silicon substrate is higher than that of the glass substrate, and a tool with higher hardness is required to cut the silicon substrate. The material cost of the silicon substrate is also higher than that of the glass substrate. The first substrate 100 of this embodiment needs to be cut twice, and a mark can also be made on the first substrate 100. The glass substrate is used as the first substrate 100 and the silicon substrate is used as the second substrate 200, which can reduce the difficulty of cutting. This embodiment is described later with the first substrate 100 being a glass substrate and the second substrate 200 being a silicon substrate.

[0059] Step S40, laminating the first laminating surface of the first substrate 100 with the second laminating surface of the second substrate 200, wherein the first scribe line area P1 is aligned with the second scribe line area P2;

[0060] Figure 6 Schematic diagram of the bonding of the first substrate 100 and the second substrate 200, as shown in Figure 6 As shown, the two sides of the second substrate 200 are respectively the first surface A3 of the second substrate and the side surface A4 opposite to the second bonding surface. The first bonding surface of the first substrate and the second bonding surface of the second substrate can be bonded together by OCR (Optical Clear Resin, optically transparent resin) glue 300 to complete the bonding between the first substrate 100 and the second substrate 200. It is understandable that a filler 400 can also be placed between the first substrate 100 and the second substrate 200 to play a buffering role.

[0061] In a feasible embodiment, the alignment accuracy between the first cutting road area P1 and the second cutting road area P2 is less than or equal to 5μm, for example, 5μm, 4μm, 3μm, 2μm, 1μm, etc. It can be understood that the second cutting road area P2 in the second substrate 200 is also a pre-divided area, and has the same width as the first cutting road area P1. The bonding process can use the positions of the first cutting road area P1 and the second cutting road area P2 as references, respectively, with the goal of completely aligning the positions of the two. Alignment accuracy refers to the position deviation between the first cutting road area P1 and the second cutting road area P2. Through process control, the alignment accuracy can be made as high as possible.

[0062] Step S50, cutting and forming a second channel 210 in a second scribe line region P2 of the second substrate 200 located on the side surface A4 opposite to the second bonding surface, wherein the second channel 210 penetrates the second substrate 200;

[0063] Figure 7 FIG. 2 is a cross-sectional diagram of the embodiment after the second channel 210 is processed. Figure 7 As shown, the position of the second cutting road area P2 is aligned with the position of the first cutting road area P1, and the second channel 210 is located in the center of the second cutting road area P2. The hard knife K2 is used to cut through the second substrate 200 to form the second channel 210 that runs through the second substrate 200. It can be understood that the hard knife K2 cuts from the side A4 opposite to the second bonding surface of the second substrate, and the Kerf value of the hard knife K2 is less than or equal to the width of the first channel 110, so that the width of the second channel 210 is less than or equal to the width of the first channel 110, and the effect of complete cutting can be achieved during the cutting process without causing damage to the first substrate 100. For silicon substrates, a hard knife K2 with higher hardness is used for cutting, and the hardness of the hard knife K2 is greater than the hardness of the soft knife No. 1 K1. The penetrating second channel 210 divides the second substrate 200 into multiple areas, and the area containing the complete chip shape can enter the subsequent process to be made into a chip product.

[0064] In a feasible embodiment, the cutting depth of the second channel 210 exceeds the first surface A3 of the second substrate by 10-20 μm, for example, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, etc. It is understandable that the center of the second channel 210 is aligned with the center of the first channel 110, the width of the second channel 210 is less than or equal to the width of the first channel 110, and the cutting depth of the hard knife K2 can exceed the first surface A3 of the second substrate to achieve complete through-cutting. If the excess is too small, the effect of complete through-cutting cannot be achieved, and if the excess is too large, damage to the first substrate 100 may be caused. The value of the excess can be flexibly set according to the depth of the first channel 110.

[0065] In step S60 , a third channel 120 is formed by cutting in the first cutting line region P1 of the first substrate 100 located on the side surface A2 opposite to the first bonding surface, so that the first channel 110 and the third channel 120 are connected, and the width of the first channel 110 is greater than or equal to the width of the third channel 120 .

[0066] Figure 8 FIG. 1 is a cross-sectional schematic diagram of the embodiment after the third channel 120 is processed. Figure 8As shown, after the third channel 120 is cut, the first substrate 100 is completely divided into multiple areas. On the basis that the second substrate 200 on the opposite side has been divided, each independent small area containing a complete chip shape can enter the subsequent process to be processed into a finished chip. The width of the first channel 110 is greater than or equal to the width of the third channel 120, so it can be ensured that the third channel 120 is completely cut. For the first substrate 100 made of glass, a soft knife No. 2 K3 can be used to cut from the center of the first cutting line area P1 to cut out the third channel 120. The hardness value of the soft knife No. 2 K3 can be the same as that of the soft knife No. 1 K1, and the Kerf value of the soft knife No. 2 K3 is less than or equal to the Kerf value of the soft knife No. 1 K1.

[0067] In a feasible embodiment, the cutting depth of the third channel 120 exceeds the inner channel surface of the first channel 110 by 10-20 μm, for example, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, etc. It can be understood that the inner surface of the first channel 110 refers to the surface where the first channel 110 contacts the third channel 120. Due to the existence of the first channel 110 and the formation of the second channel 210, the cutting depth of the soft knife No. 2 K3 can exceed the inner channel surface of the first channel 110 to achieve complete through-cutting. If the excess is too small, the effect of complete through-cutting cannot be achieved, and if the excess is too large, the effect of through-cutting will not be further improved.

[0068] In a feasible implementation, the width of the second channel 210 is equal to the width of the third channel 120. It is understandable that the center positions of the second channel 210 and the third channel 120 are aligned, and setting the width of the second channel 210 equal to the width of the third channel 120 can maintain the uniformity of the chip shape. For the cutting tool, that is, the Kerf value of the hard knife K2 is equal to the Kerf value of the soft knife No. 2 K3. In this way, Figure 8 The product structure shape shown breaks through the limitation of related technologies that cannot achieve through cutting due to process limitations and need to retain part of the raw materials, thereby improving the product yield in the cutting process.

[0069] In this embodiment, a first substrate 100 is first provided, the first substrate 100 is provided with a first cutting line area P1, and a first bonding surface is formed on the first surface A1 of the first substrate, the first cutting line area P1 is an area of ​​the first substrate 100 reserved for cutting, and the first bonding surface is used for bonding; a first channel 110 is cut in the first cutting line area P1 of the first surface A1 of the first substrate to form a first channel 110, the depth of the first channel 110 is less than the thickness of the first substrate 100, and the first channel 110 cut in the first cutting line area P1 before the bonding process is performed will not affect the strength of the first substrate 100; a first substrate 100 is provided. The second substrate 200 is provided with a second cutting road area P2, and the first surface A3 of the second substrate is formed with a second bonding surface, the second cutting road area P2 is an area reserved for cutting of the second substrate 200, and the second bonding surface can be used to bond with the first substrate 100; the first bonding surface of the first substrate 100 and the second bonding surface of the second substrate 200 are bonded, wherein the first cutting road area P1 is aligned with the second cutting road area P2, and the areas to be cut of the first substrate 100 and the second substrate 200 are aligned through a bonding process, so as to facilitate subsequent cutting to form a chip; on the second substrate 200 at the second bonding area The second trench 210 is cut in the second scribe line area P2 on the side surface A4 opposite to the bonding surface, and the second trench 210 penetrates the second substrate 200. The penetrated second trench 210 can separate the areas corresponding to the chips in the second substrate 200. Due to the existence of the first trench 110, the cutting depth of the second scribe line P2 can be slightly greater than the thickness of the second substrate 200, making it easier to penetrate without having to reserve part of the raw material to avoid damage to the first substrate 100. The third trench 120 is cut in the first scribe line area P1 on the side surface A2 opposite to the first bonding surface of the first substrate, so that the first trench 110 can separate the areas corresponding to the chips in the second substrate 200. The first channel 110 and the third channel 120 are connected, the width of the first channel 110 is greater than or equal to the width of the third channel 120, and the connected first channel 110 and the third channel 120 can separate the areas corresponding to each chip in the first substrate 100. Due to the existence of the first channel 110, it is easier to cut the first substrate 100 from the side surface A2 opposite to the first bonding surface to the first bonding surface, and the width of the first channel 110 is greater than or equal to the width of the third channel 120. After the first substrate 100 is cut, the raw material close to the first bonding surface will not protrude to the outside of the chip, thereby avoiding the falling of debris from the protruding part. Therefore, the embodiment of the present invention opens a channel in the first substrate 100 before the chip bonding process to avoid damage to the substrate material during the chip separation process, which can reduce problems such as glass scratches caused by the falling of substrate material debris in the subsequent module process and improve the cutting quality.

[0070] The embodiment of the present invention further provides a chip 500, which is processed by the chip processing method described in the above embodiment, referring to Fig. 9 , Fig. 9 is a schematic diagram of the structure of the chip of this embodiment, as shown in Fig. 9 As shown, the chip 500 includes a first substrate 501 and a second substrate 502. It can be understood that after the slicing process, the first substrate 100 is divided into the first substrates 501 of the individual chips 500, and the second substrate 200 is divided into the second substrates 502 of the individual chips 500. Therefore, the first surface of the first substrate is the first surface A1 of the first substrate, forming a first bonding surface, and the first surface of the second substrate is the first surface A3 of the second substrate, forming a second bonding surface. The first bonding surface and the second bonding surface are bonded to each other, and a notch 503 is provided on at least part of the edge of the first surface A1 of the first substrate. Based on the above embodiment, it can be known that the formation of the notch 503 is due to the fact that the first channel 110 is first cut out on the first surface A1 of the first substrate before the bonding process, combined with Figure 4 It can be seen from the processing scene of the first channel 110 shown that when the chip 500 is located at the edge of the first substrate 100, the notch 503 is opened at a part of the edge of the first surface A1 of the first substrate, and when the chip 500 is located inside the first substrate 100, the notch 503 is opened around the first surface A1 of the first substrate. The chip 500 in this embodiment can be a micro display chip with a double-layer structure, including a silicon-based OLED chip and a Micro-LED chip. The chip 500 in this embodiment adopts a new cutting method, and there is no protruding area in the product structure due to the retention of raw materials. The cutting quality is high, and the damage to the chip during the slicing process is small, which is conducive to improving the product yield.

[0071] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip processing method, characterized in that: include: Providing a first substrate, wherein the first substrate is provided with a first scribe line area, and a first bonding surface is formed on a first surface of the first substrate; Cutting a first trench in the first cutting line region on the first surface of the first substrate, wherein the depth of the first trench is less than the thickness of the first substrate; Providing a second substrate, wherein the second substrate is provided with a second cutting line area, and a second bonding surface is formed on a first surface of the second substrate; Laminating the first laminating surface of the first substrate with the second laminating surface of the second substrate, wherein the first cutting line area is aligned with the second cutting line area; Cutting a second channel in the second cutting line region of the second substrate located on the side surface opposite to the second bonding surface, wherein the second channel penetrates the second substrate; A third channel is cut in the first cutting line region of the first substrate on the side surface opposite to the first bonding surface so that the third channel communicates with the first channel, and the width of the first channel is greater than or equal to the width of the third channel.

2. The chip processing method according to claim 1, characterized in that: The first substrate is a glass substrate, and the second substrate is a silicon substrate.

3. The chip processing method according to claim 2, characterized in that: The first trench has a depth of 20-50 μm.

4. The chip processing method according to claim 3, characterized in that: The width of the second channel is equal to the width of the third channel.

5. The chip processing method according to claim 2, characterized in that: An alignment accuracy between the first scribe line region and the second scribe line region is less than or equal to 5 μm.

6. The chip processing method according to claim 2, characterized in that: The cutting depth of the second trench exceeds the first surface of the second substrate by 10-20 μm.

7. The chip processing method according to claim 2, characterized in that: The cutting depth of the third trench exceeds the inner trench surface of the first trench by 10-20 μm.

8. The chip processing method according to any one of claims 2 to 7, characterized in that: Before the step of cutting and forming a first channel in the first cutting street area on the first surface of the first substrate, the step further includes: Positioning marks are processed on the first surface of the first substrate or the surface opposite to the first bonding surface.

9. The chip processing method according to claim 8, characterized in that: The shape of the positioning mark includes at least one of a cross, a square and a circle.

10. A chip, characterized in that: The chip includes a first substrate and a second substrate, wherein a first surface of the first substrate forms a first bonding surface, and a first surface of the second substrate forms a second bonding surface, the first bonding surface and the second bonding surface are bonded to each other, and a notch is formed on at least part of the edge of the first surface of the first substrate.

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