Thin film transistor and preparation method thereof, and preparation method of display substrate

Abstract

The invention provides a thin film transistor and a preparation method thereof, and a preparation method of a display substrate, and belongs to the technical field of display. The thin film transistor comprises a substrate base plate and an active layer arranged on the substrate base plate, and the active layer comprises a first film layer and a second film layer which are sequentially arranged in a laminated mode in the direction away from the substrate base plate; the material of the active layer is a metal oxide containing an indium element and a gallium element, the content of the indium element in the first film layer is In1, the content of the indium element in the second film layer is In2, and [In1-In2 / max (In1, In2)] is greater than or equal to 0 and less than or equal to 0.5; the first film layer and the second film layer are in an amorphous state, and the mobility of the material of the first film layer is greater than that of the material of the second film layer.

Description

A thin film transistor and its manufacturing method, and a display substrate manufacturing method Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a thin film transistor and a method for preparing the same, and a method for preparing a display substrate. Background Art

[0002] Mobility refers to the speed at which electrons move in semiconductor materials. For semiconductor display devices, mobility represents the display quality and lifespan that can be achieved within the same device size. In existing technologies, the effective mobility of amorphous silicon (a-Si), metal oxides, and low-temperature polysilicon (LTPS) used in the industry is approximately 1 cm / s. 2 / V*s、10cm 2 / V*s and 80cm 2 / V*s. It can be seen that LTPS is far ahead in terms of material capabilities.

[0003] To improve the mobility of metal oxide materials, the industry has developed a variety of new material families. However, this increased mobility also brings with it issues such as high device leakage, high current density, and potential burnout in thin-film transistors (TFTs), for example.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a thin film transistor and a method for preparing the same, and a method for preparing a display substrate.

[0006] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a thin film transistor, comprising a base substrate and an active layer provided on the base substrate, wherein the active layer comprises a first film layer and a second film layer stacked in sequence in a direction away from the base substrate;

[0007] The material of the active layer is a metal oxide containing indium and gallium elements, the indium content in the first film layer is In1, and the indium content in the second film layer is In2, wherein 0≤[|In1-In2| / max(In1, In2)]≤0.5; the first film layer and the second film layer are amorphous, and the mobility of the material of the first film layer is greater than the mobility of the material of the second film layer.

[0008] In some embodiments, a ratio of the thickness of the second film layer to the thickness of the first film layer ranges from 1 to 10.

[0009] In some embodiments, the thin film transistor also includes a gate layer, and a gate insulation layer located between the gate layer and the active layer; the first film layer is closer to the gate layer than the second film layer, and the thickness of the first film layer ranges from 5nm to 25nm, and the thickness of the second film layer ranges from 40nm to 120nm.

[0010] In some embodiments, the thin film transistor also includes a gate layer, and a gate insulation layer located between the gate layer and the active layer; the second film layer is closer to the gate layer than the first film layer, and the thickness of the first film layer ranges from 10nm to 20nm, and the thickness of the second film layer ranges from 10nm to 50nm.

[0011] In some embodiments, the gallium content in the first film layer is Ga1, the gallium content in the second film layer is Ga2, Ga1>Ga2, and 1≤Ga1 / Ga2≤4.

[0012] In some embodiments, the active layer further contains zinc element, the zinc element content in the first film layer is Zn1, and the zinc element content in the second film layer is Zn2, wherein Zn1>Zn2, and 1≤Zn1 / Zn2≤2.

[0013] In some embodiments, the active layer further includes tin element, the tin element content in the first film layer is T1, and the tin element content in the second film layer is T2, wherein T1>T2≥0.

[0014] In some embodiments, the ratio of the indium element to the gallium element in the first film layer is in the range of 2≤In1 / Ga1≤5.

[0015] In some embodiments, the ratio of the indium element to the gallium element in the second film layer is in the range of 0≤In2 / Ga2≤2.

[0016] In some embodiments, the ratio of the zinc element to the gallium element in the first film layer is in the range of 3≤Zn1 / Ga1≤5.

[0017] In some embodiments, the ratio of the zinc element to the gallium element in the second film layer is in the range of 0≤Zn2 / Ga2≤2.

[0018] In some embodiments, the ratio of the indium element to the tin element in the first film layer is in the range of 3≤In1 / T1≤5.

[0019] In some embodiments, the threshold voltage of the thin film transistor is in the range of 1V to 2V.

[0020] In some embodiments, the electron mobility of the thin film transistor is in the range of 17 cm2 / V*s~24cm 2 / V*s.

[0021] In some embodiments, the positive shift of the threshold voltage of the thin film transistor under positive bias temperature stress is less than 3V.

[0022] In some embodiments, the negative shift of the threshold voltage of the thin film transistor under the action of negative bias temperature and light stress is less than 4V.

[0023] In some embodiments, the thin film transistor can withstand a voltage between the source and the drain that is not less than 63V.

[0024] In a second aspect, the present disclosure also provides a method for manufacturing a thin film transistor, comprising:

[0025] providing a substrate;

[0026] An active layer is formed; forming the active layer includes sequentially forming a first film layer and a second film layer stacked in a direction away from the substrate; the material of the active layer is a metal oxide containing indium and gallium elements, the indium content in the first film layer is In1, and the indium content in the second film layer is In2, wherein 0≤[|In1-In2| / max(In1, In2)]≤0.5; the first film layer and the second film layer are amorphous, and the mobility of the material of the first film layer is greater than the mobility of the material of the second film layer.

[0027] In some embodiments, the material of the second film layer is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1.

[0028] In some embodiments, the method for preparing the thin film transistor further includes:

[0029] Before forming the active layer, a gate layer and a gate insulating layer are sequentially formed on the base substrate;

[0030] After the active layer is formed, a source electrode layer and a drain electrode layer are formed, wherein the source electrode layer and the drain electrode layer are electrically connected to the source contact region and the drain contact region of the active layer, respectively.

[0031] In some embodiments, the material of the first film layer is indium gallium zinc tin oxide, and the thickness of the first film layer ranges from 5 nm to 25 nm; the thickness of the second film layer ranges from 40 nm to 120 nm.

[0032] In some embodiments, the method for preparing the thin film transistor further includes:

[0033] Before forming the active layer, a light shielding layer and a buffer layer are sequentially formed on the base substrate;

[0034] After forming the active layer, a gate layer, a gate insulating layer, an interlayer insulating layer, a source layer and a drain layer are formed. The source layer and the drain layer are electrically connected to the source contact region and the drain contact region of the active layer, respectively.

[0035] In some embodiments, the material of the first film layer is indium gallium zinc tin oxide or indium gallium oxide, and the thickness of the first film layer ranges from 10 nm to 20 nm; the thickness of the second film layer ranges from 10 nm to 50 nm.

[0036] In a third aspect, an embodiment of the present disclosure further provides a method for preparing a display substrate, which includes a thin film transistor prepared according to the method for preparing a thin film transistor according to any one of the above embodiments.

[0037] In some embodiments, the method for preparing the display substrate further includes:

[0038] forming a first passivation layer, wherein the first passivation layer is located on a side of the source electrode layer and the drain electrode layer facing away from the substrate;

[0039] forming a planarization layer, wherein the planarization layer is located on a side of the first passivation layer facing away from the substrate;

[0040] forming a first electrode layer, where the first electrode layer is located on a side of the planarization layer facing away from the base substrate, and the material of the first electrode layer is a transparent conductive material;

[0041] forming a second passivation layer, wherein the second passivation layer is located on a side of the first electrode layer facing away from the substrate;

[0042] A second electrode layer is formed, where the second electrode layer is located on a side of the second passivation layer away from the base substrate, and the second electrode layer is connected to the source layer through a via hole penetrating the second passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present disclosure;

[0044] FIG2 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present disclosure;

[0045] 3a to 3j are flow charts of a process for preparing a bottom-gate metal oxide thin film transistor according to an embodiment of the present disclosure;

[0046] FIG4 a is a schematic diagram of a cross-sectional transmission electron bright-field image of a bottom-gate metal oxide thin film transistor according to an embodiment of the present disclosure;

[0047] FIG4 b is a schematic diagram of a scattered electron dark field image of a bottom-gate metal oxide thin film transistor provided by an embodiment of the present disclosure;

[0048] FIG4 c is an energy spectrum diagram of each element in the active layer of the bottom-gate metal oxide thin film transistor provided by an embodiment of the present disclosure;

[0049] FIG5 is a schematic diagram of device performance of a bottom-gate metal oxide thin film transistor provided by an embodiment of the present disclosure;

[0050] FIG6 is a diagram showing a Vds withstand voltage capability test of a bottom-gate metal oxide thin film transistor according to an embodiment of the present disclosure;

[0051] FIG7 is a schematic diagram showing how the device characteristics of a bottom-gate metal oxide thin film transistor according to an embodiment of the present disclosure vary with the thickness of the first film layer;

[0052] FIG8 is a schematic diagram showing how the device characteristics of a bottom-gate metal oxide thin film transistor according to an embodiment of the present disclosure vary with the thickness of the second film layer;

[0053] 9a to 9m are flow charts of a process for preparing a top-gate metal oxide thin film transistor according to an embodiment of the present disclosure.

[0054] The figures are marked as follows: 10, substrate; 20, gate layer; 30, gate insulating layer; 40, active layer; 41, first film layer; 42, second film layer; 51, source layer; 52, drain layer; 61, first passivation layer; 70, planarization layer; 81, first electrode layer; 62, second passivation layer; 82, second electrode layer; 11, light-shielding layer; 12, buffer layer; 90, interlayer insulating layer. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0057] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0058] With the development of science and technology, human society has entered the information age. More and more information is being accessed through screens. The mobile phones, computers, and television screens we use daily are all flat panel displays (FPDs). Currently, FPDs are developing towards higher resolution, thinness, flexibility, and energy efficiency. Thin-film transistors (TFTs), as switching control elements or integrated components in peripheral drive circuits, are core components in display technology. Their electrical performance determines the quality of display devices.

[0059] TFTs are classified as field-effect transistors (FETs). They consist of a gate electrode, a gate insulator, a channel layer, and source and drain electrodes. The material selection and fabrication process for each component are crucial to the overall device performance. Traditional amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used in industrial production due to their light weight and compact size. However, their low carrier mobility prevents them from adapting to the current trend toward higher-definition and larger-screen displays, limiting their application to small displays. Polycrystalline silicon thin-film transistors (LTPS TFTs) offer high carrier mobility, but their high fabrication temperature, complex production process, high production costs, and poor mobility distribution uniformity caused by grain boundaries make LTPS TFTs unsuitable for large-area fabrication. Furthermore, a-Si:H and LTPS TFTs have low optical transmittance in the visible light range and are inflexible, hindering the development of transparent and flexible displays. Oxide thin film transistors (Oxide TFTs) have been widely studied in recent years due to their flexibility, large-area production and simple process. Their carrier mobility has surpassed that of a-Si TFTs.

[0060] The inventors discovered that in existing metal oxide thin film transistors, in order to improve the mobility of metal oxides, different series of materials were developed and the ratio of elements in the metal oxides was adjusted. However, as the mobility of metal oxide materials increased, some problems also emerged.

[0061] For example, the optical band gap of high-mobility materials decreases, meaning electrons in high-mobility materials can absorb some visible light to generate electronic transitions. This manifests itself in premature light-sensitive TFT activation, an increase in new defects under illumination, and severe degradation of negative bias temperature and light stress characteristics, resulting in a significant reduction in service life. Furthermore, high-mobility metal oxide thin-film transistors (TFTs) exhibit rapid electron drift and high current density, leading to rapid localized heat release. This can cause localized high temperatures in TFTs, accelerating characteristic degradation and even leading to burnout.

[0062] It should be noted that metal oxide thin film transistors are sensitive to voltage stress, temperature and light, which will seriously affect their characteristics. Specifically, metal oxide thin film transistors are usually subject to the following two more common stresses: positive bias temperature stress (PBTS) and negative bias temperature illumination stress (NBTIS). Under normal circumstances, the thin film transistor drifts in the positive direction under the action of PBTS and drifts in the negative direction under the action of NBTIS. In this way, when the thin film transistor is under the joint action of PBTS and NBTIS, the threshold voltage Vth of the thin film transistor can be guaranteed in the long-term reliability evaluation, that is, in the long-term use process, after the positive and negative drifts of the threshold voltage are neutralized, the threshold voltage can remain stable, thereby ensuring product quality.

[0063] In view of this, a thin film transistor is provided in an embodiment of the present disclosure. Figure 1 is a structural schematic diagram of a thin film transistor provided in an embodiment of the present disclosure. As shown in Figure 1, the thin film transistor in the embodiment of the present disclosure is a metal oxide thin film transistor, and it has a dual active stacked structure and adopts high-mobility metal oxide material to improve the problems of high leakage and high current density and easy burning of existing high-mobility devices, thereby improving the switching capability of the display backplane and the service life of the product.

[0064] It should be noted that the mobility range of the high mobility metal oxide material mentioned in the embodiments of the present disclosure is not less than 20 cm 2 / V*s.

[0065] On the first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a thin film transistor, as shown in Figure 1, which includes a base substrate 10 and an active layer 40 arranged on the base substrate 10, the active layer 40 includes a first film layer 41 and a second film layer 42 stacked in sequence along a direction away from the base substrate 10; the material of the active layer 40 is a metal oxide containing indium and gallium elements, the indium content in the first film layer 41 is In1, and the indium content in the second film layer 42 is In2, wherein 0≤[|In1-In2| / max(In1, In2)]≤0.5; the first film layer 41 and the second film layer 42 are amorphous, and the mobility of the material of the first film layer 41 is greater than the mobility of the material of the second film layer 42.

[0066] Specifically, in the embodiment of the present disclosure, the material of the first film layer 41 in the active layer 40 is a high-mobility metal oxide. For example, the material of the first film layer 41 includes but is not limited to indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), indium gallium zinc tin oxide (IGZTO), lanthanide-doped metal oxide (Ln-OS), etc. Since the mobility of the material of the first film layer 41 is not less than the mobility of the material of the second film layer 42, and the mobility range of the material of the first film layer 41 is not less than 20 cm 2 / V*s, this setting can prevent the excessive increase of photoinduced defects and improve the problem of high leakage and easy burning of display devices due to high current density.

[0067] It should be noted that the element content in the present disclosure may refer to the mass percentage of the element, or the atomic number percentage, or the proportion of the element in the entire film layer, or the proportion of the element in a specific film layer. The present disclosure does not impose any special restrictions on this.

[0068] It should be noted that |In1-In2| represents the absolute value of the difference in indium content between the first film layer 41 and the second film layer 42, and max(In1, In2) represents the larger of the indium content values ​​of the first film layer 41 and the second film layer 42. When the values ​​of In1 and In2 are equal, the ratio is 0. Generally, the difference between In1 and In2 does not exceed 3. Preferably, 0.05 ≤ [|In1-In2| / max(In1, In2)] ≤ 0.25.

[0069] In some embodiments, the gallium content in the first film layer 41 is Ga1, the gallium content in the second film layer 42 is Ga2, Ga1>Ga2, and 1≤Ga1 / Ga2≤4.

[0070] In some embodiments, the active layer 40 further includes zinc. The zinc content in the first film layer 41 is Zn1, and the zinc content in the second film layer 42 is Zn2. Zn1>Zn2, and 1≤Zn1 / Zn2≤2.

[0071] In some embodiments, the active layer 40 further includes tin element, the tin element content in the first film layer 41 is T1, and the tin element content in the second film layer 42 is T2, wherein T1>T2≥0.

[0072] In some embodiments, the ratio of the indium element to the gallium element in the first film layer 41 is in the range of 2≤In1 / Ga1≤5.

[0073] In some embodiments, the ratio of the indium element to the gallium element in the second film layer 42 is in the range of 0≤In2 / Ga2≤2.

[0074] In some embodiments, the ratio of the zinc element to the gallium element in the first film layer 41 is in the range of 3≤Zn1 / Ga1≤5.

[0075] In some embodiments, the ratio of the zinc element to the gallium element in the second film layer 42 is in the range of 0≤Zn2 / Ga2≤2.

[0076] In some embodiments, the ratio of the indium element to the tin element in the first film layer 41 is in the range of 3≤In1 / T1≤5.

[0077] Hereinafter, a specific description will be given by taking an example where the material of the second film layer 42 is indium gallium zinc oxide and the atomic ratio of the indium gallium zinc oxide is In:Ga:Zn=1:1:1.

[0078] Specifically, in the disclosed embodiment, the material of the first film layer 41 of the thin film transistor is a high-mobility metal oxide, and the material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1. The material used for the second film layer 42 is indium gallium zinc oxide, which mainly utilizes the relatively stable and balanced mobility and resistance of indium gallium zinc oxide. The mobility of indium gallium zinc oxide is about 10cm 2 / V*s, this intermediate mobility level can provide a certain amount of carriers, thereby compensating for the problem of weak device switching capability caused by the first film layer 41 (i.e., the high-mobility layer). At the same time, the intermediate resistance level of InGaZnO can limit the movement of carriers in the high-mobility layer to a certain extent, control the device to a reasonable off-state current level, and prevent the device from overheating and burning due to its own high resistance.

[0079] The thin-film transistors provided in the embodiments of the present disclosure can improve display devices, such as high leakage current, high current density, and easy burnout. Therefore, the thin-film transistors provided in the embodiments of the present disclosure can be applied to medium- and large-sized products, such as televisions (TVs) and desktop TV displays (MNTs), as well as in scenarios with relatively high voltages.

[0080] It should be noted that the material of the second film layer 42 in the disclosed embodiment includes, but is not limited to, indium gallium zinc oxide. In other words, any material with properties very similar to those of indium gallium zinc oxide can also be used to make the second film layer 42. As long as the second film layer 42 can work together with the high-mobility first film layer 41 to improve the high leakage and high current density issues of thin-film transistors, the switching capability of the display backplane and the product's service life can be improved.

[0081] 1 , the thin film transistor further includes a gate layer 20 and a gate insulating layer 30 located between the gate layer 20 and the active layer 40. The gate insulating layer 30 is used to isolate the gate layer 20 from the active layer 40 to prevent short circuits.

[0082] It should be noted that, according to the upper and lower positional relationship between the gate layer 20 and the active layer 40, the structure of the thin film transistor can be simply divided into a bottom gate structure and a top gate structure. The gate of the top gate structure is located at the top of the device, and the gate of the bottom gate structure is located above the substrate. In the process of production, no matter how the new structure is designed, the device is composed of common parts: substrate, gate electrode (i.e., gate layer 20), insulating layer (i.e., gate insulating layer 30), active layer 40, source and drain electrodes, etc. Depending on the relative positions of different components of the device, there can be different device structures. In the embodiment of the present disclosure, the thin film transistor shown in Figure 1 is a bottom gate thin film transistor. Figure 2 is a schematic structural diagram of another thin film transistor provided in the embodiment of the present disclosure, as shown in Figure 2, which is a top gate thin film transistor.

[0083] It should be noted that the active layer 40 of the thin film transistor in the present disclosure is a dual active stacked structure, which can be applied to thin film transistors of different structures. For ease of description and understanding, the embodiments of the present disclosure are mainly described in detail for bottom-gate thin film transistors and top-gate thin film transistors.

[0084] It should be noted that, whether it is a bottom-gate thin film transistor or a top-gate thin film transistor, the ratio of the thickness of the second film layer 42 to the first film layer 41 in the active layer 40 is in the range of 1 to 10. By adjusting the ratio of the thickness of the second film layer 42 to the first film layer 41 in the active layer 40, the thin film transistor provided by the embodiment of the present disclosure can ensure that the first film layer 41 and the second film layer 42 are fully formed while ensuring that the thin film transistor achieves a preset mobility, thereby reducing film defects.

[0085] In some embodiments, as shown in FIG1 , the first film layer 41 is closer to the gate layer 20 than the second film layer 42, meaning that the thin film transistor is a bottom-gate thin film transistor. The first film layer 41 is made of indium gallium zinc tin oxide and has a thickness of 5 nm to 25 nm; the second film layer 42 has a thickness of 40 nm to 120 nm.

[0086] Specifically, in the embodiment of the present disclosure, the material of the first film layer 41 is indium gallium zinc tin oxide, so that the first film layer 41 has a higher mobility. At the same time, the thickness of the first film layer 41 is between 5nm and 25nm to prevent excessive increase of photoinduced defects. The material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1, and the thickness of the second film layer 42 is between 40nm and 120nm. This arrangement utilizes the relatively stable and balanced mobility and resistance of indium gallium zinc oxide. The mobility of indium gallium zinc oxide is about 10cm 2 / V*s. This intermediate mobility level can provide a certain amount of carriers, thereby compensating for the weak switching capability of the device caused by the first film layer 41 (i.e., the high-mobility layer). At the same time, the intermediate resistance level of the indium gallium zinc oxide can both limit the movement of carriers in the high-mobility layer to a certain extent, controlling the device to a reasonable off-state current level, and preventing the device from overheating and burning due to its own high resistance. The thin-film transistor provided by the disclosed embodiments can improve the problems of high leakage and easy burning of display devices due to high current density.

[0087] In some embodiments, as shown in FIG2 , the second film layer 42 is closer to the gate layer 20 than the first film layer 41, meaning that the thin film transistor is a top-gate thin film transistor. The material of the first film layer 41 is indium gallium zinc tin oxide or indium gallium oxide, and the thickness of the first film layer 41 is 10 nm to 20 nm; the thickness of the second film layer 42 is 10 nm to 50 nm.

[0088] Specifically, in the embodiment of the present disclosure, the material of the first film layer 41 is indium gallium zinc tin oxide or indium gallium oxide, so that the first film layer 41 has a higher mobility. At the same time, the thickness of the first film layer 41 is between 10nm and 20nm to prevent excessive increase of photoinduced defects. The material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1, and the thickness of the second film layer 42 is between 10nm and 50nm. This arrangement utilizes the relatively stable and balanced mobility and resistance of indium gallium zinc oxide. The mobility of indium gallium zinc oxide is about 10cm 2 / V*s. This intermediate mobility level can provide a certain amount of carriers, thereby compensating for the weak switching capability of the device caused by the first film layer 41 (i.e., the high-mobility layer). At the same time, the intermediate resistance level of the indium gallium zinc oxide can both limit the movement of carriers in the high-mobility layer to a certain extent, controlling the device to a reasonable off-state current level, and preventing the device from overheating and burning due to its own high resistance. The thin-film transistor provided by the disclosed embodiments can improve the problems of high leakage and easy burning of display devices due to high current density.

[0089] In a second aspect, the embodiments of the present disclosure also provide a method for preparing a thin film transistor.

[0090] Hereinafter, the preparation methods of the bottom-gate metal oxide thin film transistor shown in FIG1 and the top-gate metal oxide thin film transistor shown in FIG2 will be described in detail respectively.

[0091] FIG3a to FIG3j are flow charts of a process for preparing a bottom-gate metal oxide thin film transistor according to an embodiment of the present disclosure. As shown in FIG3a to FIG3j , when preparing the bottom-gate metal oxide thin film transistor shown in FIG1 , the preparation method may include steps S11 to S110, which are specifically as follows:

[0092] S11, providing a base substrate 10.

[0093] Specifically, as shown in FIG3 a , the base substrate 10 includes but is not limited to a glass substrate. In the embodiment of the present disclosure, the base substrate 10 is described as a glass substrate as an example.

[0094] S12 , forming a gate layer 20 .

[0095] Specifically, as shown in FIG3b , the step of forming the gate layer 20 includes forming a gate metal layer on the base substrate 10 and patterning the gate metal layer to form the final gate layer 20. Methods for forming the gate layer 20 include, but are not limited to, magnetron sputtering; patterning methods include, but are not limited to, photolithography and imprinting; and etching and transfer methods include, but are not limited to, wet etching and dry reaction.

[0096] In some embodiments, the gate metal layer can be patterned using a mask-based process. Specifically, for example, a photoresist can be coated on the gate metal layer, and the photoresist can be exposed using a corresponding mask. The mask includes a light-transmitting area and a non-light-transmitting area. During the exposure process, the portion of the photoresist corresponding to the light-transmitting area is completely exposed, and the portion of the photoresist corresponding to the non-light-transmitting area is not exposed. Next, the exposed photoresist is developed to obtain a photoresist pattern. The photoresist pattern includes a retained area corresponding to the light-transmitting area and an area to be removed corresponding to the non-light-transmitting area. Thereafter, the gate metal layer is etched using the photoresist pattern, for example, using a wet etching process to completely etch the area to be removed corresponding to the gate metal layer. Finally, the remaining photoresist is stripped off to form the final gate layer 20.

[0097] Furthermore, in some embodiments, the gate layer 20 may include a buffer layer 12, a main conductive layer, and a top protective layer in a stacked arrangement. Specifically, the buffer layer 12 is located on a side close to the base substrate 10, and the material of the buffer layer 12 includes, but is not limited to, titanium (Ti), molybdenum (Mo) alloys, etc. The material of the main conductive layer includes, but is not limited to, aluminum (Al), copper (Cu), etc. The material of the top protective layer includes, but is not limited to, titanium (Ti), molybdenum (Mo) alloys, etc.

[0098] S13 , forming a gate insulating layer 30 .

[0099] Specifically, as shown in FIG3 c , the step of forming the gate insulating layer 30 includes: forming a first insulating layer on the side of the gate layer 20 away from the substrate 10 , and patterning the first insulating layer to form a final gate insulating layer 30 , wherein the gate insulating layer 30 covers the gate layer 20 .

[0100] In some embodiments, the first insulating layer can be patterned using a mask-based process. Specifically, for example, a photoresist can be coated on the first insulating layer, and the photoresist can be exposed using a corresponding mask. The mask includes a light-transmitting area and a non-light-transmitting area. During the exposure process, the portion of the photoresist corresponding to the light-transmitting area is completely exposed, and the portion of the photoresist corresponding to the non-light-transmitting area is not exposed. Next, the exposed photoresist is developed to obtain a photoresist pattern. The photoresist pattern includes a retained area corresponding to the light-transmitting area and an area to be removed corresponding to the non-light-transmitting area. Thereafter, the first insulating layer is etched using the photoresist pattern, for example, using a dry etching process to completely etch the area to be removed corresponding to the first insulating layer. Finally, the remaining photoresist is stripped off to form the final gate insulating layer 30.

[0101] In some embodiments, the gate insulating layer 30 has a thickness of 300 nm to 500 nm. Preferably, the gate insulating layer 30 may include silicon oxide, and the thickness of the silicon oxide is not less than 100 nm. It should be noted that the material selection and preparation process of the gate insulating layer 30 greatly affect the performance of the thin film transistor. In the embodiments of the present disclosure, the gate insulating layer 30 includes silicon oxide, which can reduce the device threshold voltage.

[0102] S14 , forming an active layer 40 .

[0103] Specifically, the active layer 40 includes a first film layer 41 and a second film layer 42 stacked in a direction away from the base substrate 10. As shown in Figure 3d, the steps of forming the active layer 40 include: forming a first conductive layer and a second conductive layer stacked on the side of the gate insulating layer 30 facing away from the base substrate 10, and patterning the first conductive layer and the second conductive layer to form a first film layer 41 and a second film layer 42. The first film layer 41 and the second film layer 42 form the final active layer 40. The material of the first film layer 41 is a high-mobility metal oxide, and the mobility of the material of the first film layer 41 is not less than the mobility of the material of the second film layer 42.

[0104] It should be noted that the mobility range of the high mobility metal oxide material mentioned in the embodiments of the present disclosure is not less than 20 cm 2 / V*s. The material of the first film layer 41 includes but is not limited to indium gallium oxide (IGO), indium tin zinc oxide (ITZO), indium gallium zinc tin oxide (IGZTO), etc. Since the mobility of the material of the first film layer 41 is not less than the mobility of the material of the second film layer 42, and the mobility range of the material of the first film layer 41 is not less than 20cm 2 / V*s, this setting can prevent the excessive increase of photoinduced defects and improve the problem of high leakage and easy burning of display devices due to high current density.

[0105] In some embodiments, the first conductive layer and the second conductive layer can be patterned using a mask-based process. Specifically, for example, a photoresist can be coated on the side of the first conductive layer and the second conductive layer facing away from the base substrate 10, and the photoresist can be exposed using a corresponding mask. The mask includes a light-transmitting area and a non-light-transmitting area. During the exposure process, the portion of the photoresist corresponding to the light-transmitting area is completely exposed, and the portion of the photoresist corresponding to the non-light-transmitting area is not exposed. Next, the exposed photoresist is developed to obtain a photoresist pattern, which includes a retained area corresponding to the light-transmitting area and an area to be removed corresponding to the non-light-transmitting area. Thereafter, the first conductive layer and the second conductive layer are etched using the photoresist pattern, for example, using a wet etching process to completely etch the area to be removed corresponding to the first conductive layer and the second conductive layer. Finally, the remaining photoresist is stripped off to form the first film layer 41 and the second film layer 42.

[0106] In some embodiments, the step of forming the active layer 40 further includes depositing a channel. A 30 nm thick ITZO layer may be deposited by magnetron sputtering as the channel of the thin film transistor, and then the channel is annealed to obtain the active layer 40 .

[0107] In some embodiments, the material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1. Specifically, in the embodiment of the present disclosure, the material of the first film layer 41 of the thin film transistor is a high-mobility metal oxide, and the material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1. The material used for the second film layer 42 is indium gallium zinc oxide, which mainly utilizes the relatively stable and balanced mobility and resistance of indium gallium zinc oxide. The mobility of indium gallium zinc oxide is about 10cm 2 / V*s. This intermediate mobility level can provide a certain amount of carriers, thereby compensating for the weak switching capability of the device caused by the first film layer 41 (i.e., the high-mobility layer). At the same time, the intermediate resistance level of the indium gallium zinc oxide can both limit the movement of carriers in the high-mobility layer to a certain extent, controlling the device to a reasonable off-state current level, and preventing the device from overheating and burning due to its own high resistance. The thin-film transistor provided by the disclosed embodiments can improve the problems of high leakage and easy burning of display devices due to high current density.

[0108] It should be noted that the material of the second film layer 42 in the disclosed embodiment includes, but is not limited to, indium gallium zinc oxide. In other words, any material with properties very similar to those of indium gallium zinc oxide can also be used to make the second film layer 42. As long as the second film layer 42 can work together with the high-mobility first film layer 41 to improve the high leakage and high current density issues of thin-film transistors, the switching capability of the display backplane and the product's service life can be improved.

[0109] Furthermore, in some embodiments, the material of the first film layer 41 is indium gallium zinc tin oxide, and the thickness of the first film layer 41 is 5nm to 25nm; the thickness of the second film layer 42 is 40nm to 120nm. Specifically, in the embodiment of the present disclosure, the material of the first film layer 41 is indium gallium zinc tin oxide, so that the first film layer 41 has a higher mobility. At the same time, the thickness of the first film layer 41 is between 5nm and 25nm to prevent excessive increase of photoinduced defects. The material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1, and the thickness of the second film layer 42 is between 40nm and 120nm. This arrangement utilizes the relatively stable and balanced mobility and resistance of indium gallium zinc oxide. The mobility of indium gallium zinc oxide is about 10cm 2 / V*s. This intermediate mobility level can provide a certain amount of carriers, thereby compensating for the weak switching capability of the device caused by the first film layer 41 (i.e., the high-mobility layer). At the same time, the intermediate resistance level of the indium gallium zinc oxide can both limit the movement of carriers in the high-mobility layer to a certain extent, controlling the device to a reasonable off-state current level, and preventing the device from overheating and burning due to its own high resistance. The thin-film transistor provided by the disclosed embodiments can improve the problems of high leakage and easy burning of display devices due to high current density.

[0110] S15 , forming a source electrode layer 51 and a drain electrode layer 52 .

[0111] Specifically, as shown in FIG3e , the step of forming the source layer 51 and the drain layer 52 includes depositing the source layer 51 and the drain layer 52 on the side of the active layer 40 facing away from the base substrate 10. The source layer 51 and the drain layer 52 are located on the side of the gate insulating layer 30 facing away from the base substrate 10, and the active layer 40 is located on the side of the gate insulating layer 30 facing away from the base substrate 10, and at least portions of the source layer 51 and the drain layer 52 are connected to the active layer 40, that is, the source layer 51 and the drain layer 52 are electrically connected to the source contact region and the drain contact region of the active layer 40, respectively.

[0112] In some embodiments, during the process of depositing the source layer 51 and the drain layer 52, the source layer 51 and the drain layer 52 need to be patterned. Since the material of the second film layer 42 of the active layer 40 is indium gallium zinc oxide, in order to prevent the indium gallium zinc oxide from being excessively damaged by the etching solution during the patterning process, preferably, a copper Cu stack and a hydrogen peroxide-based etching solution can be used to complete the process.

[0113] S16 , forming a first passivation layer 61 .

[0114] Specifically, as shown in FIG3 f , after the source layer 51 and the drain layer 52 are formed, a first passivation layer 61 is formed on the side of the source layer 51 and the drain layer 52 facing away from the substrate 10. The first passivation layer 61 is located on the side of the source layer 51 and the drain layer 52 facing away from the substrate 10, and the thickness of the first passivation layer 61 is 300 nm to 400 nm.

[0115] The material of the first passivation layer 61 includes silicon oxide. Preferably, the thickness of the silicon oxide is not less than 100 nm.

[0116] S17 , forming a planarization layer 70 .

[0117] Specifically, as shown in FIG. 3 g , after the first passivation layer 61 is formed, a planarization layer 70 is formed on a side of the first passivation layer 61 facing away from the base substrate 10 , so as to make the surface of the thin film transistor planar.

[0118] S18 , forming a first electrode layer 81 .

[0119] Specifically, as shown in FIG3 h , after the planarization layer 70 is formed, a first electrode layer 81 is formed on the side of the planarization layer 70 facing away from the base substrate 10 . The material of the first electrode layer 81 is a transparent conductive material.

[0120] In the embodiment of the present disclosure, the first electrode layer 81 is a common electrode, and the transparent conductive material of the first electrode layer 81 can be indium tin oxide ITO.

[0121] S19 , forming a second passivation layer 62 .

[0122] Specifically, as shown in FIG. 3 i , after the first electrode layer 81 is formed, a second passivation layer 62 is formed on the side of the first electrode layer 81 facing away from the substrate 10 , and the second passivation layer 62 has an opening that exposes a portion of the source layer 51 .

[0123] S110 , forming a second electrode layer 82 .

[0124] Specifically, as shown in FIG. 3 j , after the second passivation layer 62 is formed, a second electrode layer 82 is formed on the side of the second passivation layer 62 away from the substrate 10 , and the second electrode layer 82 is connected to the source layer 51 through a via hole penetrating the second passivation layer 62 .

[0125] Specifically, in the embodiment of the present disclosure, the second electrode layer 82 is a pixel electrode, which is connected to the source layer 51 of the thin film transistor and is in a Slit shape to form an electric field with the first electrode layer 81 (common electrode).

[0126] It should be noted that the above embodiments of the present disclosure are bottom-gate, back-channel-etched (BCE) thin-film transistors, but the dual-active stack structure in the present disclosure is not limited to the aforementioned thin-film transistors. For example, the thin-film transistor may also be a thin-film transistor with an etch stop layer (ESL), and top-gate thin-film transistors may be modified accordingly, without any particular limitation in the present disclosure.

[0127] Figure 4a is a schematic diagram of a cross-sectional transmission electron bright-field image of a bottom-gate metal oxide thin-film transistor according to an embodiment of the present disclosure; Figure 4b is a schematic diagram of a scattered electron dark-field image of the bottom-gate metal oxide thin-film transistor according to an embodiment of the present disclosure; and Figure 4c is a diagram of the energy spectrum of each element in the active layer of the bottom-gate metal oxide thin-film transistor according to an embodiment of the present disclosure. As shown in Figures 4a, 4b, and 4c, the active layer 40 is divided into two layers, namely a first film layer 41 and a second film layer 42. The first film layer 41 is made of indium gallium zinc tin oxide, and the second film layer 42 is made of indium gallium zinc oxide. As can be clearly seen from Figure 4c, there is no tin in the second film layer 42. In actual production, the content of In in the first film layer 41 is 15-17 At% (At% represents atomic percentage), the content of Ga is 4-6 At%, the content of Zn is 16-20 At%, the content of Sn is 2-6 At%, and the In:Ga:Zn:Sn ratio is approximately 4:1:4:1.

[0128] FIG5 is a schematic diagram of the device performance of a bottom-gate metal oxide thin film transistor provided by an embodiment of the present disclosure. As shown in FIG5 , Vth represents the threshold voltage of the thin film transistor, and μ represents the electron mobility of the thin film transistor. In the figure, only the threshold voltage is 1V and the electron mobility is 20.6 cm 2 / V*s as an example.

[0129] In some embodiments, the threshold voltage of the thin film transistor is in the range of 1V to 2V.

[0130] In some embodiments, the electron mobility of the thin film transistor is in the range of 17 cm 2 / V*s~24cm 2 / V*s.

[0131] 5 , the thin film transistor is right-biased by 1.9V after 1 hour under the positive bias working state, and is left-biased by 2.5V after 1 hour under the light-exposed, negative bias working state. It can be seen that the bottom-gate metal oxide thin film transistor provided in the embodiment of the present disclosure has good anti-aging ability.

[0132] In some embodiments, under the effect of positive bias temperature stress, the positive shift of the threshold voltage of the thin film transistor is less than 3V.

[0133] In some embodiments, under the negative bias, temperature, and light stress, the negative shift of the threshold voltage of the thin film transistor is less than 4V.

[0134] Figure 6 is a Vds withstand voltage test diagram of the bottom-gate metal oxide thin film transistor provided by an embodiment of the present disclosure. As shown in Figure 6, Vds represents the voltage between the source and drain of the thin film transistor. It should be noted that when pressure is applied to the source and drain of thin film transistors in the prior art, the withstand Vds voltage is around 35V. It can be seen that the withstand Vds voltage of the bottom-gate metal oxide thin film transistor provided by the embodiment of the present disclosure is 63V, which is a significant improvement. In other words, the bottom-gate metal oxide thin film transistor provided by the embodiment of the present disclosure has a stronger Vds withstand voltage capability.

[0135] In some embodiments, the thin film transistor can withstand a voltage between the source and the drain that is not less than 63V.

[0136] Figure 7 is a schematic diagram showing how the device characteristics of the bottom-gate metal oxide thin film transistor provided in an embodiment of the present disclosure vary with the thickness of the first film layer 41; Figure 8 is a schematic diagram showing how the device characteristics of the bottom-gate metal oxide thin film transistor provided in an embodiment of the present disclosure vary with the thickness of the second film layer 42. As shown in Figures 7 and 8, the structure of the active layer 40, as well as the selection of the materials and thicknesses of the first film layer 41 and the second film layer 42 constituting the active layer 40, all affect the performance of the device.

[0137] It should be noted that since the top-gate metal oxide thin film transistor requires a conductor process, that is, the self-aligned active layer 40 is subjected to conductor processing, the stability of the processing will be relatively worse for materials with higher mobility, which can easily cause the characteristics of the entire thin film transistor to drift. That is, the process window capability of the top-gate metal oxide thin film transistor is poor, which will weaken the advantages of metal oxide in application. When the dual-active stacked structure in the embodiment of the present disclosure is applied to the top-gate metal oxide thin film transistor, the second film layer 42 can use indium gallium zinc tin oxide as the top active material, which can not only improve the process window problem of a single layer of high mobility material, but also avoid the problem of rapid current decay caused by the poor contact performance of the top active layer 40, thereby effectively improving the stability of the conductor process and enhancing the characteristic process window.

[0138] FIG9a to FIG9m are flow charts of a process for preparing a top-gate metal oxide thin film transistor according to an embodiment of the present disclosure. As shown in FIG9a to FIG9m , when preparing the top-gate metal oxide thin film transistor shown in FIG2 , the preparation method may include steps S21 to S213 , which are specifically as follows:

[0139] S21 , providing a base substrate 10 .

[0140] Specifically, as shown in FIG9 a , the base substrate 10 includes but is not limited to a glass substrate. In the embodiment of the present disclosure, the base substrate 10 is described as a glass substrate as an example.

[0141] S22 , forming a light shielding layer 11 .

[0142] Specifically, as shown in FIG9b , the step of forming the light-shielding layer 11 includes: forming a light-shielding metal layer on the base substrate 10, and patterning the light-shielding metal layer to form the final light-shielding layer 11. Methods for forming the light-shielding layer 11 include, but are not limited to, magnetron sputtering; patterning methods include, but are not limited to, photolithography and imprinting; and etching and transfer methods include, but are not limited to, wet etching and dry reaction.

[0143] It should be noted that since the thin film transistor in the embodiment of the present disclosure is a top-gate thin film transistor, a light shielding layer 11 is required to ensure that the active layer 40 of the thin film transistor is not affected by ambient light. The material of the light shielding layer 11 includes, but is not limited to, a molybdenum-based alloy and a corresponding copper-Cu and aluminum-Al composite metal structure.

[0144] S23 , forming a buffer layer 12 .

[0145] Specifically, as shown in FIG9 c , a buffer layer 12 is formed on the side of the light shielding layer 11 facing away from the base substrate 10 .

[0146] In some embodiments, the buffer layer 12 is made of silicon oxide, or a composite layer of silicon nitride and silicon oxide, and the thickness of the buffer layer 12 is 200 nm to 500 nm.

[0147] S24 , forming an active layer 40 .

[0148] Specifically, the active layer 40 includes a first film layer 41 and a second film layer 42 stacked in a direction away from the base substrate 10. As shown in Figure 9d, the steps of forming the active layer 40 include: forming a first conductive layer and a second conductive layer stacked on the side of the buffer layer 12 away from the base substrate 10, patterning the first conductive layer and the second conductive layer to form a first film layer 41 and a second film layer 42, and the first film layer 41 and the second film layer 42 form the final active layer 40. The material of the first film layer 41 is a high-mobility metal oxide, and the mobility of the material of the first film layer 41 is not less than the mobility of the material of the second film layer 42.

[0149] It should be noted that the mobility range of the high mobility metal oxide material mentioned in the embodiments of the present disclosure is not less than 20 cm 2 / V*s. The material of the first film layer 41 includes but is not limited to indium gallium oxide (IGO), indium tin zinc oxide (ITZO), indium gallium zinc tin oxide (IGZTO), etc. Since the mobility of the material of the first film layer 41 is not less than the mobility of the material of the second film layer 42, and the mobility range of the material of the first film layer 41 is not less than 20cm 2 / V*s, this setting can prevent the excessive increase of photoinduced defects and improve the problem of high leakage and easy burning of display devices due to high current density.

[0150] In some embodiments, the first conductive layer and the second conductive layer can be patterned using a mask-based process. Specifically, for example, a photoresist can be coated on the side of the first conductive layer and the second conductive layer facing away from the base substrate 10, and the photoresist can be exposed using a corresponding mask. The mask includes a light-transmitting area and a non-light-transmitting area. During the exposure process, the portion of the photoresist corresponding to the light-transmitting area is completely exposed, and the portion of the photoresist corresponding to the non-light-transmitting area is not exposed. Next, the exposed photoresist is developed to obtain a photoresist pattern, which includes a retained area corresponding to the light-transmitting area and an area to be removed corresponding to the non-light-transmitting area. Thereafter, the first conductive layer and the second conductive layer are etched using the photoresist pattern, for example, using a wet etching process to completely etch the area to be removed corresponding to the first conductive layer and the second conductive layer. Finally, the remaining photoresist is stripped off to form the first film layer 41 and the second film layer 42.

[0151] In some embodiments, the step of forming the active layer 40 further includes depositing a channel. A 30 nm thick ITZO layer may be deposited by magnetron sputtering as the channel of the thin film transistor, and then the channel is annealed to obtain the active layer 40 .

[0152] In some embodiments, the material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1. Specifically, in the embodiment of the present disclosure, the material of the first film layer 41 of the thin film transistor is a high-mobility metal oxide, and the material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1. The material used for the second film layer 42 is indium gallium zinc oxide, which mainly utilizes the relatively stable and balanced mobility and resistance of indium gallium zinc oxide. The mobility of indium gallium zinc oxide is about 10cm 2 / V*s. This intermediate mobility level can provide a certain amount of carriers, thereby compensating for the weak switching capability of the device caused by the first film layer 41 (i.e., the high-mobility layer). At the same time, the intermediate resistance level of the indium gallium zinc oxide can both limit the movement of carriers in the high-mobility layer to a certain extent, controlling the device to a reasonable off-state current level, and preventing the device from overheating and burning due to its own high resistance. The thin-film transistor provided by the disclosed embodiments can improve the problems of high leakage and easy burning of display devices due to high current density.

[0153] It should be noted that the material of the second film layer 42 in the disclosed embodiment includes, but is not limited to, indium gallium zinc oxide. In other words, any material with properties very similar to those of indium gallium zinc oxide can also be used to make the second film layer 42. As long as the second film layer 42 can work together with the high-mobility first film layer 41 to improve the high leakage and high current density issues of thin-film transistors, the switching capability of the display backplane and the product's service life can be improved.

[0154] Furthermore, in some embodiments, the material of the first film layer 41 is indium gallium zinc tin oxide or indium gallium oxide, and the thickness of the first film layer 41 is 10nm to 20nm; the thickness of the second film layer 42 is 10nm to 50nm. Specifically, in the embodiment of the present disclosure, the material of the first film layer 41 is indium gallium zinc tin oxide or indium gallium oxide, so that the first film layer 41 has a higher mobility. At the same time, the thickness of the first film layer 41 is between 10nm and 20nm to prevent excessive increase of photoinduced defects. The material of the second film layer 42 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:1, and the thickness of the second film layer 42 is between 10nm and 50nm. This arrangement utilizes the relatively stable and balanced mobility and resistance of indium gallium zinc oxide. The mobility of indium gallium zinc oxide is about 10cm 2 / V*s. This intermediate mobility level can provide a certain amount of carriers, thereby compensating for the weak switching capability of the device caused by the first film layer 41 (i.e., the high-mobility layer). At the same time, the intermediate resistance level of the indium gallium zinc oxide can both limit the movement of carriers in the high-mobility layer to a certain extent, controlling the device to a reasonable off-state current level, and preventing the device from overheating and burning due to its own high resistance. The thin-film transistor provided by the disclosed embodiments can improve the problems of high leakage and easy burning of display devices due to high current density.

[0155] S25 , forming a gate insulating layer 30 .

[0156] Specifically, as shown in FIG9e , a gate insulating layer 30 is formed on the side of the active layer 40 facing away from the base substrate 10 . The specific steps may refer to step S13 of preparing the gate insulating layer 30 of the bottom-gate thin film transistor.

[0157] In the following embodiment, the gate insulating layer 30 has a thickness of 100 nm to 300 nm. Preferably, the gate insulating layer 30 may include silicon oxide, and the thickness of the silicon oxide ranges from 10 nm to 30 nm.

[0158] S26 , forming a gate layer 20 .

[0159] 9f, a gate layer 20 is formed on the side of the gate insulating layer 30 facing away from the base substrate 10. The metal selection of the gate layer 20 can refer to step S12 of preparing the gate layer 20 of the bottom-gate thin film transistor.

[0160] Specifically, when the gate metal layer is patterned to form the final gate layer 20, the gate metal layer can be patterned using a mask-based process. Specifically, for example, a photoresist can be coated on the gate metal layer, and the photoresist can be exposed using a corresponding mask. The mask includes a light-transmitting area and a non-light-transmitting area. During the exposure process, the portion of the photoresist corresponding to the light-transmitting area is completely exposed, and the portion of the photoresist corresponding to the non-light-transmitting area is not exposed. Next, the exposed photoresist is developed to obtain a photoresist pattern, which includes a retained area corresponding to the light-transmitting area and an area to be removed corresponding to the non-light-transmitting area. Thereafter, the gate metal layer is etched using the photoresist pattern, for example, by using a wet etching process to completely etch the area to be removed corresponding to the gate metal layer. Finally, the remaining photoresist is stripped off to form the final gate layer 20.

[0161] It should be noted that after photolithography and etching of the gate metal layer, the gate insulating layer 30 is etched using the gate layer 20 as a mask to expose the active layer 40 before conducting. Specifically, the conducting process can be performed using a plasma of a gas (including a mixed gas) such as helium (He), argon (Ar), hydrogen (H2), or ammonia (NH3).

[0162] S27 . Form an interlayer insulating layer 90 .

[0163] Specifically, as shown in FIG9g , an interlayer insulating layer 90 is deposited on the side of the gate layer 20 facing away from the substrate 10 . The material of the interlayer insulating layer 90 includes, but is not limited to, silicon oxide, or a composite film of silicon nitride Si 3 N 4 and silicon oxide. Preferably, the thickness of the interlayer insulating layer 90 ranges from 300 nm to 600 nm.

[0164] Specifically, the interlayer insulating layer 90 is photolithographically and etched to form a through hole exposing a portion of the active layer 40 .

[0165] S28 , forming a source electrode layer 51 and a drain electrode layer 52 .

[0166] Specifically, as shown in Figure 9h, a source layer 51 and a drain layer 52 are deposited on the side of the interlayer insulating layer 90 facing away from the base substrate 10, and the source layer 51 and the drain layer 52 are respectively connected to the opposite sides of the active layer 40 through vias penetrating the interlayer insulating layer 90, that is, the source layer 51 and the drain layer 52 are respectively electrically connected to the source contact area and the drain contact area of ​​the active layer 40.

[0167] S29 , forming a first passivation layer 61 .

[0168] Specifically, as shown in FIG. 9 i , after the source layer 51 and the drain layer 52 are formed, a first passivation layer 61 is formed on the side of the source layer 51 and the drain layer 52 facing away from the base substrate 10 , and an organic material photolithography process is performed on the first passivation layer 61 .

[0169] S210 , forming a planarization layer 70 .

[0170] Specifically, as shown in FIG9 j , after the first passivation layer 61 is formed, a planarization layer 70 is formed on the side of the first passivation layer 61 facing away from the base substrate 10 , so as to make the surface of the thin film transistor planar.

[0171] S211 , forming a first electrode layer 81 .

[0172] Specifically, as shown in FIG9 k , after the planarization layer 70 is formed, a first electrode layer 81 is formed on the side of the planarization layer 70 facing away from the base substrate 10 . The material of the first electrode layer 81 is a transparent conductive material.

[0173] In the embodiment of the present disclosure, the first electrode layer 81 is a common electrode. The material of the first electrode layer 81 is a transparent conductive material. The transparent conductive material of the first electrode layer 81 can be indium tin oxide ITO.

[0174] S212 , forming a second passivation layer 62 .

[0175] Specifically, as shown in FIG91 , after the first electrode layer 81 is formed, a second passivation layer 62 is formed on the side of the first electrode layer 81 facing away from the base substrate 10 , and the second passivation layer 62 has an opening that exposes a portion of the source layer 51 .

[0176] S213 , forming a second electrode layer 82 .

[0177] Specifically, as shown in FIG9 m , after the second passivation layer 62 is formed, a second electrode layer 82 is formed on the side of the second passivation layer 62 away from the base substrate 10 , and the second electrode layer 82 is connected to the source layer 51 through a via hole penetrating the second passivation layer 62 .

[0178] Specifically, in the embodiment of the present disclosure, the second electrode layer 82 is a pixel electrode, which is connected to the source layer 51 of the thin film transistor and is in a Slit shape to form an electric field with the first electrode layer 81 (common electrode).

[0179] It should be noted that the preparation process in the embodiment of the present disclosure can be adjusted accordingly according to thin film transistors of different structures. As long as the active layer 40 adopts the dual active structure in the embodiment of the present disclosure, and the material of the first film layer 41 of the active layer 40 is a high-mobility metal oxide, and the material of the second film layer 42 is indium gallium zinc oxide with an atomic ratio of In:Ga:Zn=1:1:1 or a material with similar properties to indium gallium zinc oxide, the present disclosure does not impose any special restrictions on this.

[0180] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A thin film transistor, characterized in that: It comprises a substrate, and an active layer arranged on the substrate, wherein the active layer comprises a first film layer and a second film layer which are sequentially stacked in a direction away from the substrate; The material of the active layer is a metal oxide containing indium and gallium elements, the indium content in the first film layer is In1, and the indium content in the second film layer is In2, wherein 0≤[|In1-In2| / max(In1, In2)]≤0.5; the first film layer and the second film layer are amorphous, and the mobility of the material of the first film layer is greater than the mobility of the material of the second film layer.

2. The thin film transistor according to claim 1, characterized in that: The ratio of the thickness of the second film layer to the thickness of the first film layer ranges from 1 to 10.

3. The thin film transistor according to claim 2, characterized in that: It also includes a gate layer and a gate insulating layer located between the gate layer and the active layer; the first film layer is closer to the gate layer than the second film layer, and the thickness of the first film layer ranges from 5nm to 25nm, and the thickness of the second film layer ranges from 40nm to 120nm.

4. The thin film transistor according to claim 2, characterized in that: It also includes a gate layer and a gate insulating layer located between the gate layer and the active layer; the second film layer is closer to the gate layer than the first film layer, and the thickness of the first film layer ranges from 10nm to 20nm, and the thickness of the second film layer ranges from 10nm to 50nm.

5. The thin film transistor according to claim 2, characterized in that: The gallium content in the first film layer is Ga1, the gallium content in the second film layer is Ga2, Ga1>Ga2, and 1≤Ga1 / Ga2≤4.

6. The thin film transistor according to claim 5, characterized in that: The active layer further contains zinc element, the zinc element content in the first film layer is Zn1, and the zinc element content in the second film layer is Zn2, wherein Zn1>Zn2, and 1≤Zn1 / Zn2≤2.

7. The thin film transistor according to claim 5, characterized in that: The active layer further contains tin element, the tin element content in the first film layer is T1, and the tin element content in the second film layer is T2, wherein T1>T2≥0.

8. The thin film transistor according to claim 5, characterized in that: The ratio of the indium element to the gallium element in the first film layer is in the range of 2≤In1 / Ga1≤5.

9. The thin film transistor according to claim 5, characterized in that: The ratio of the indium element to the gallium element in the second film layer is in the range of 0≤In2 / Ga2≤2.

10. The thin film transistor according to claim 6, characterized in that: The ratio of the zinc element to the gallium element in the first film layer is in the range of 3≤Zn1 / Ga1≤5.

11. The thin film transistor according to claim 6, characterized in that: The ratio of the zinc element to the gallium element in the second film layer is in the range of 0≤Zn2 / Ga2≤2.

12. The thin film transistor according to claim 7, characterized in that: The ratio of the indium element to the tin element in the first film layer is in the range of 3≤In1 / T1≤5.

13. The thin film transistor according to any one of claims 1 to 12, characterized in that: The threshold voltage ranges from 1V to 2V.

14. The thin film transistor according to claim 13, characterized in that: The electron mobility range is 17 cm 2 / V*s~24cm 2 / V*s.

15. The thin film transistor according to claim 13, characterized in that: Under the effect of positive bias temperature stress, the positive shift of the threshold voltage is less than 3V.

16. The thin film transistor according to claim 13, characterized in that: Under the action of negative bias temperature and light stress, the negative shift of the threshold voltage is less than 4V.

17. The thin film transistor according to claim 13, characterized in that: The voltage between the source and drain terminals is no less than 63V.

18. A method for preparing a thin film transistor, characterized in that: include: Providing a substrate; forming an active layer; The active layer is formed by sequentially forming a first film layer and a second film layer in a stacked arrangement in a direction away from the substrate; the material of the active layer is a metal oxide containing indium and gallium, the indium content of the first film layer is In1, and the indium content of the second film layer is In2, wherein 0≤[|In1-In2| / max(In1, In2)]≤0.5; the first film layer and the The second film layer is amorphous, and the mobility of the material of the first film layer is greater than the mobility of the material of the second film layer.

19. The preparation method according to claim 18, characterized in that: The material of the second film layer is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn=1:1:

1.

20. The preparation method according to claim 19, characterized in that: Also includes: Before forming the active layer, a gate layer and a gate insulating layer are sequentially formed on the base substrate; After the active layer is formed, a source electrode layer and a drain electrode layer are formed, wherein the source electrode layer and the drain electrode layer are electrically connected to a source contact region and a drain contact region of the active layer, respectively.

21. The preparation method according to claim 20, characterized in that: The material of the first film layer is indium gallium zinc tin oxide, and the thickness of the first film layer ranges from 5nm to 25nm; the thickness of the second film layer ranges from 40nm to 120nm.

22. The preparation method according to claim 19, characterized in that: Also includes: Before forming the active layer, a light shielding layer and a buffer layer are sequentially formed on the base substrate; After forming the active layer, a gate layer, a gate insulating layer, an interlayer insulating layer, a source layer and a drain layer are formed, and the source layer and the drain layer are electrically connected to the source contact region and the drain contact region of the active layer, respectively.

23. The preparation method according to claim 22, characterized in that: The material of the first film layer is indium gallium zinc tin oxide or indium gallium oxide, and the thickness of the first film layer ranges from 10nm to 20nm; the thickness of the second film layer ranges from 10nm to 50nm.

24. A method for preparing a display substrate, characterized in that: A thin film transistor prepared by the method for preparing a thin film transistor according to any one of claims 18 to 23.

25. The preparation method according to claim 24, characterized in that: Also includes: forming a first passivation layer, wherein the first passivation layer is located on a side of the source electrode layer and the drain electrode layer away from the substrate; Forming a planarization layer, the planarization layer is located on the first passivation layer away from the substrate One side; forming a first electrode layer, wherein the first electrode layer is located on a side of the planarization layer away from the base substrate, and the material of the first electrode layer is a transparent conductive material; forming a second passivation layer, wherein the second passivation layer is located on a side of the first electrode layer away from the substrate; A second electrode layer is formed, where the second electrode layer is located on a side of the second passivation layer away from the base substrate, and the second electrode layer is connected to the source layer through a via hole penetrating the second passivation layer.

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