Photonic integrated circuit and manufacturing method thereof

Abstract

The invention relates to a photonic integrated circuit and a manufacturing method thereof. A photonic integrated circuit (PIC) comprising a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming a PIN or PN doped structure, the PIC comprising: a waveguide arranged to conduct light waves; an optical element connected to the waveguide, where the optical element in operation is in a reverse bias mode, and where the optical element comprises a contact layer arranged for connection to a voltage source; wherein the waveguide comprises a conductive contact proximate to the optical element, and wherein the PIC further comprises at least one isolation portion disposed between the optical element and the conductive contact. Corresponding methods of operation of such PICs are also presented herein.

Description

[0001] This application is a divisional application with application date of February 7, 2020, application number 202080012430.9, and invention name “Improved building blocks for electro-optically integrated indium phosphide-based phase modulators”, all contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates generally to the field of photonic integrated circuits, and in particular to an apparatus having reduced interference levels between different components of a photonic integrated circuit. Background Art

[0003] A photonic integrated circuit PIC or integrated optical circuit is a device that integrates multiple photonic functions. It is mainly different from an electronic integrated circuit in that a PIC provides functionality for information signals applied on light wavelengths in the visible or near infrared spectrum. Different components such as low-loss interconnect waveguides, power dividers, optical amplifiers, optical modulators, filters, lasers and detectors form a PIC. In general, a PIC includes both active components as well as passive components. Active components are, for example, semiconductor optical amplifiers SOA, electro-refractive modulators ERM, and passive components are, for example, waveguides.

[0004] Examples of PICs include monolithically tunable lasers, widely tunable lasers, externally modulated lasers and transmitters, integrated receivers. In such PICs, parameters of light, such as frequency and phase, are important, and information can be conveyed based on changes in one of these properties. Therefore, it is desirable to be able to finely control such parameters.

[0005] For example, the phase of light is adjusted by employing ERMs. ERMs change the phase by adjusting the refractive index of the material, which in turn can be controlled by affecting the electric field applied to the material. In normal practice, the electric field is precisely controlled by adjusting the bias voltage.

[0006] After testing, it seems that there is crosstalk between active components, which introduces additional electric fields, which in turn affect the phase of light passing through the active components. This is undesirable. In addition, this additional electric field is also observed on passive components (such as waveguides). As a result, the phase of the light passing through is changed beyond what is expected.

[0007] The present inventors have identified a problem with a standard phase modulator, which is an ERM in a common multi-project wafer MPW integration process, when used in reverse bias. This problem led to a discovery that also solves similar problems for other components in an Indium Phosphide InP MPW process, not just the phase modulator.

[0008] The problem was discovered during the characterization of a tunable laser with a filter based on three asymmetric Mach-Zehnder interferometers AMZI in series. This particular device was implemented in the MPW operation of Smart Photonics Operation 17, SP17 on an n-type doped substrate and packaged in a Technobis standard package. The layout of the device is schematically depicted in Figure 1 and refer to Figure 1 Further elaboration.

[0009] The device 1 has three AMZIs 10, 20, 30, each with two ERMs 11, 12; 21, 22; 31, 32; 2.118 mm in length, plus a so-called in-line ERM 40 to tune the cavity modes independently. All ERMs have 30 μm long isolation sections at both ends. The ERMs are operated using a voltage that places the pin junction of the device in reverse bias.

[0010] We find two related problems in this circuit. The first is that there can be a lot of electrical crosstalk between the different ERMs. A second, directly related problem is that the passive waveguide between the two ERMs becomes biased due to the bias of the surrounding ERMs and acts as a phase modulator. These problems become apparent in the results of the laser measurements presented here. In this measurement, the long waveguide arm of the coarsely tuned (minimum path length difference) AMZI was reverse biased with a voltage, Vset. The voltage levels of the other unbiased ERMs were measured using a Keithley source meter. The chip was grounded at the bottom n-contact. The measurements are given in Figure 2 Presented are the voltages recorded on the ERM, in 51 the short arm of the coarse-tuned AMZI; in 52 the long arm of the medium AMZI; in 53 the long arm of the fine-tuned AMZI, as a function of the voltage Vset.

[0011] The crosstalk to the different ERMs is clearly visible. This means that the passive waveguides between the ERMs and the MMIs have a certain voltage on the p-doped layer. Therefore, they will also act as phase modulators. More data on the tuning of the AMZIs are available, which also emphasize the role of the passive waveguides.

[0012] The cause of crosstalk is that the isolation section has a resistance of several megohms (MΩ), and the reverse biased pin diode structure has a similar or higher resistance. The reverse bias current at -4 volts (V) (in the dark) is 80 to 100 nanoamps (nA), which means a resistance of about 40 MΩ. Note that when light passes through the ERM, it affects the current through the ERM, thus affecting its effective resistance. This will affect the crosstalk to the passive waveguide section and other ERMs. Summary of the invention

[0013] In a first aspect of the present disclosure, a photonic integrated circuit PIC is proposed, comprising a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming a PIN or PN doped structure, the PIC comprising: a waveguide, the waveguide comprising a waveguide layer and arranged for guiding light waves, the waveguide layer being one of the plurality of semiconductor layers; an optical element, the optical element comprising a waveguide layer, the waveguide layer being one of the plurality of semiconductor layers, the waveguide and the waveguide layer of the optical element being connected to each other, wherein the optical element is in a reverse bias mode in operation, and wherein the optical element comprises a contact layer arranged for connection to a voltage source;

[0014] Wherein the waveguide comprises at least one electrically conductive contact proximate to the optical element, and wherein the PIC further comprises at least one isolating portion disposed between the contact layer and the at least one electrically conductive contact.

[0015] As understood in the art, a photonic integrated circuit PIC or integrated optical circuit is a device that integrates multiple photonic functions. A PIC, in turn, may consist of several active components and / or passive components. A PIC is typically formed by arranging several layers of semiconductor material on a substrate. These layers are doped so as to form a PIN or PN doped structure. Examples of such doped structures are shown in FIG. Figure 3b and described in detail in the corresponding sections below.

[0016] It has been identified that in the previous section, the inventors found that although isolation parts are included in the elements of the PIC, there are undesirable effects such as crosstalk between components or passive components (such as waveguides), thereby introducing additional phase modulation. The inventors found that by providing at least one additional conductive contact close to the contact layer, the optical element can be effectively isolated from the influence of adjacent optical elements.

[0017] According to one embodiment, at least one isolating portion is arranged between the optical element and the electrically conductive contact.

[0018] For example, the isolation portion may ensure that multiple ones of the semiconductor layers of the optical element and the waveguide are isolated so that not all semiconductor layers of the optical element are also directly connected to their respective corresponding semiconductor layers of the waveguide.

[0019] According to one embodiment, at least one electrically conductive contact is arranged on both sides of the optical element with respect to the direction of the light in the waveguide. This is a preferred arrangement to ensure improved isolation of the optical element in question.

[0020] According to one embodiment, the at least one conductive contact extends substantially over the entire waveguide. The inventors have considered it advantageous to ensure effective isolation of the waveguide by placing at least one conductive contact over substantially the entire waveguide. In this way, the waveguide remains passive and is not biased by adjacent electric fields.

[0021] In an exemplary embodiment, at least one of the conductive contacts is connected to electrical ground. This has the advantage that the isolation becomes more effective. The electrical grounding can be achieved by means of a grounding hole arranged to allow contact between the conductive contact and the n-doped layer, wherein the distance between the edge of the grounding hole and the waveguide is at least 10 μm, wherein the distance is measured in a direction perpendicular to the direction of light propagation in the waveguide. In a preferred embodiment, it may be advantageous to maintain a specific voltage on the metal contact.

[0022] As mentioned above, the length is measured in a direction perpendicular to the propagation direction of the light. The value of 10 μm is chosen so that any bias applied to the conductive contacts does not affect the propagation of light in the waveguide. Current technical limitations dictate that such a distance is currently at least 10 μm. A person skilled in the art understands that this distance may be further reduced in the future if technical improvements allow a reduction in this distance. The determining factor is that the distance should be chosen so that the bias applied to the conductive contacts does not affect the propagation of light in a way that is detrimental to the functioning of the device.

[0023] Preferably, at least one dimension of the cross section of the ground hole in a plane parallel to the propagation direction of light in the waveguide is at least 20 μm. This limitation is also a result of the technology currently used. Future technology may allow ground holes of smaller size.

[0024] According to one embodiment, the length of the conductive contact measured in the propagation direction of the light is at least 20 μm. The inventors believe that in order to achieve isolation in a more effective manner, it is necessary to ensure that the conductive contact extends at least 20 μm, and more preferably at least 50 μm.

[0025] According to any embodiment, the conductive contacts include any of titanium and / or gold and / or platinum. The inventors recognize that these are metals commonly used during the manufacture of such PICs. Those skilled in the art will also know other metals or materials with suitable conductivity that can be employed to achieve the purposes listed in this disclosure.

[0026] According to the present disclosure, the optical element is any one of the following:

[0027] - an electro-refractive modulator (ERM), and

[0028] -Photodetector.

[0029] The inventors believe that these two elements are most susceptible to the influence of the surrounding electric field and believe that it is beneficial to ensure the isolation of these two elements. For example, ERM modulates the phase of light by adjusting the refractive index of the material. The refractive index is in turn adjusted by changing the electric field. Therefore, if the ERM is not effectively isolated, undesirable or unexpected phase outputs will be observed.

[0030] According to one embodiment, the PIC comprises a plurality of conductive contacts, wherein the plurality of conductive contacts are connected to each other via a metal conductive layer. In such an embodiment, all conductive objects close to different optical elements are connected to each other. This may be advantageous because only one electrical ground may be required.

[0031] In a second aspect of the invention, there is provided a method of operating a photonic integrated device according to the present disclosure as described above, wherein a reverse bias voltage is applied to a conductive contact. The inventors consider that it is advantageous to connect the conductive contact to a voltage source and apply a reverse bias voltage thereto. This has the effect that it reduces propagation losses and stabilizes the optical path length to a higher degree than is currently the case. This is particularly useful when the applied reverse bias is applied to a conductive contact on a passive component, such as a waveguide.

[0032] In another embodiment of the second aspect of the present disclosure, a method of operating a photonic integrated device according to the present disclosure as described above is provided, wherein the conductive contact is connected to electrical ground. In addition to connecting the contact to reverse bias, the conductive contact may also be grounded. The present invention may be understood in more detail with reference to the accompanying drawings and their description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is a schematic layout of a tunable laser commonly used in photonic integrated circuits (PICs).

[0034] Figure 2 The voltage levels measured on different electrorefractive modulators ERMs are shown as a function of the voltage applied to the ERM in the long arm of the coarse tuning AMZI.

[0035] Figure 3a A cross section of a device according to the present disclosure is shown.

[0036] Figure 3b The different layers of a device according to the present disclosure are shown.

[0037] Figure 3c A cross section of a device according to the present disclosure is shown.

[0038] Figure 4 A cross section of a ground waveguide portion according to the present disclosure is shown.

[0039] Figure 5A three-dimensional sketch of a waveguide ridge having two isolated portions, a ground portion and an opening to a substrate layer is shown. DETAILED DESCRIPTION

[0040] Figure 1 A schematic layout of a tunable laser commonly used in photonic integrated circuits PIC is shown. The device 1 has three AMZIs 10, 20, 30, each with two ERMs 11, 12; 21, 22; 31, 32; 2.118 mm in length, plus a so-called in-line ERM 40 to independently tune the cavity mode. All ERMs have 30 μm long isolation sections at both ends. The ERMs are operated using a voltage that puts the pin junction of the device in reverse bias. The layout also includes a semiconductor optical amplifier SOA 41.

[0041] Figure 2 The voltage levels measured on different electro-refractive modulators ERMs as a function of the voltage applied to the ERM in the long arm of the coarse tuning AMZI are shown in 50. Presented are the voltages recorded on the ERMs, in 51 the short arm of the coarse tuning AMZI; in 52 the long arm of the medium AMZI; and in 53 the long arm of the fine tuning AMZI. In 54, presented are the measured voltages on the fine tuning AMZI when both ERMs in the cavity ERM and the medium tuning AMZI are grounded. This clearly demonstrates that by effectively grounding the optical element, interference from other adjacent optical elements can be effectively reduced. The latter observation points to possible solutions and improvements to the ERM building blocks. This is shown in Figure 3a , Figure 3b and Figure 3c Described in .

[0042] Figure 3a A cross section of a photonic integrated circuit according to the present disclosure is shown. Next to the ERM 11 there will be an isolation section 72 on both sides, and next to the isolation section 72 there will be another short ERM section that will be connected to ground 71. The waveguide 74 includes a waveguide layer 65 and is arranged for conducting light waves. According to the present disclosure, the waveguide 74 also includes a conductive contact 69 that allows connection to a voltage source or electrical ground.

[0043] The length of the isolation section determines to a large extent the dark current of the ERM. A typical length of the isolation section 72 is currently 50 μm. This length stems from the current design rules of the Smart Photonics process. However, if the etching depth of this section (down to about the intermediate layer III-1) is similar and if the application allows an increase in the dark current on the ERM, this length can in principle be shortened to about 20 μm. The 20 μm limitation stems from the manufacturing process of the currently used metallization process (lift-off process).

[0044] The length of the ground portion will also be 50 μm, determined by current design rules. It can be shorter. It is estimated that the current that will flow will be of the order of microamperes at most. Therefore, even a 20 μm long ground contact (a practical limit for current technology) is not expected to have excessive resistance. For the etching depth, it is important that the highly doped layer III-2 is completely etched away. Less etching depth in the waveguide for isolation is possible, but the current level from the ERM to the ground contact will start to rise. Whether this can be tolerated depends on the application of the circuit and electronic device. The metallization used for the ground contact can be the same as the metallization used for the phase modulator. For example, the contact is made of any of titanium / platinum / gold (Ti / Pt / Au), and the contact has a thickness of 300 nanometers (nm) of gold deposited by evaporation.

[0045] It should be noted that photonic integrated devices on InP are described here, but in principle other integration schemes using similar ridge waveguide technology and other semiconductor systems would present similar problems. However, we are not aware of other material systems being used commercially for this purpose.

[0046] In the current smart photonics integration scheme, such as Figure 3a The additional ground contacts 71 in the chip are all contacted by metal wiring on the chip surface. This will result in a large number of metal connections on the chip. Figure 3b The different layers are further elaborated with the help of

[0047] Figure 3b The different layers of a device according to the present disclosure are shown. Figure 3b and the corresponding description should be understood as examples. The features of the present disclosure are not limited to the precise values ​​presented here. Layer III-3, designated 61, is a p-type doped contact layer with a high doping concentration of about 1.5E19. A typical material used may be p-type doped InGaAs. Layer 61 is 300 nm thick. Layer III-2, designated 62, is also p-type doped, but has a density of about 1.5E19 per cubic centimeter (cm -3 ) A lower doping concentration of 1E18. Layer 62 is made of InP and has a thickness of 1000 nm.

[0048] Layer III-1, designated as 63, is a p-type doped layer made of InP and is approximately 300 nm thick. This layer has a thickness of approximately 1E17 cm -3 The layer II-2, designated as 64, is an n-type doped layer made of InP and is about 200 nm thick. The doping concentration is about 1E16 cm -3 The layer II-1 labeled 65 is an n-Q1.25 waveguide layer. The waveguide layer 65 has a wavelength of about 1E16 cm -3 doping concentration and is 500nm thick.

[0049] Layers I-2 and I-1, denoted 66 and 67 respectively, are both n-doped and have 1E17 cm -3 The sum of 1E18cm -3 They are all made of InP and have a thickness of 500 nm each. Layer 68 is the substrate on which all subsequent layers are assembled. It is also called I-0 and is typically doped with a concentration of 1E18 cm -3 to 4E18 cm -3 As mentioned above, these values ​​are only exemplary and not limiting.

[0050] Figure 3c A cross section of a device according to the present disclosure is shown. There are many issues to consider. Isolation in the vertical direction of the waveguide may need to be considered. The trench width next to the passive waveguide is 20 μm, as shown in FIG. Figure 3c The etch is deeper than the isolation etch, but the distance is typically three to five times, perhaps more and smaller.

[0051] Figure 4 A cross section of a grounded waveguide section according to the present disclosure is shown at 100. The present invention is more general in providing contacts on phase modulators. It is also applicable to other reverse biased components such as amplifiers used in detectors and in passive components. Another point is that it may be wise to contact all passive components and keep them at a reverse bias voltage of about 3 to 4 volts. There are many reasons for wanting to do this. Having contacts 102 on all passive devices solves the electrical isolation problem using far fewer required contacts (without changing the technology). The contact design of the passive components may be different from Figure 4 Slightly different.

[0052] The cross section of the waveguide will be similar to Figure 4The cross section in . If one wants to contact a passive device such as a multimode interference coupler, the waveguide section becomes significantly wider (e.g. 8μm instead of 2μm). Metallization of this wider structure can cause problems in manufacturing. The applied voltage also reduces the free carrier concentration in the waveguide, thereby reducing propagation losses by as much as 0.5dB per centimeter. It also cleans up free carriers generated in the passive waveguide by light passing through the waveguide (which causes increased absorption). The maximum power capacity of the passive waveguide may also be increased, but this needs to be studied. A third advantage is that photoinduced carriers generate phase noise on the optical signal. This can be a problem in very narrow linewidth CW lasers and will certainly play a role in mode-locked lasers. Due to thermal effects, the free carrier concentration varies with time, and the built-in potential of the PIN structure can cause the waveguide to forward bias itself in a way that is difficult to predict (like a solar cell). This light-generated current can enter anywhere in the p-type doped layer and flow to the waveguide section with lower intensity. Free carrier effects in passive waveguides are currently being studied.

[0053] Figure 5 A three-dimensional sketch 110 of a waveguide ridge having two isolation portions 112, a ground portion 113 and an opening 114 to a substrate layer 111 is shown. One possible way to avoid this is to make a local contact to the n-doped layer in the substrate, e.g. Figure 4 This would require a change in the existing processing scheme. A hole would have to be etched into the highly doped layer I-0 next to the waveguide where contact is made with the waveguide.

[0054] A metallization scheme such as the currently used Ti-Pt-Au layer system (typical thicknesses 60-75-500 nm respectively) and contact annealing may be used as it will provide a good ohmic contact on both n-doped InP and p-doped InGaAs. The dimension 116 of the opening 114 towards layer I-0 may be as long as the ground contact and it is estimated that it will need to be a minimum of 20 μm wide. Figure 5 In FIG. 1 , a 2 μm wide ridge waveguide is drawn to scale before planarization and metallization is applied to show the structure, with two 20 μm isolation sections, a 20 μm long ground section in the middle, and an opening for access to layer I-0. The opening 114 is 10 μm away 115 from the waveguide so as not to affect the propagation of light in the waveguide.

[0055] Since the current levels are expected to be limited to 1 μA or less, the resistance value of the contacts may be relatively high (e.g., several hundred Ω). The depth of the etched holes may be the same as that of the deep-etched ridge waveguides, in which case the metal will contact the lower-doped InP layer. This requires more research and experimentation.

[0056] In semi-insulating substrate technology, grounding of the p-side of the waveguide will be easier to achieve. In such technology solutions where a top n-contact layer is already available, this can be used to connect the top p-contact of the grounded waveguide section.

[0057] These combinations of two isolated sections and one grounded section can also be used with other reverse biased components. A specific example is a photodetector where it will prevent leakage current and dark current levels to other detectors or biased components as well as dark current due to photogenerated current in other passive waveguide components connected to the photodetector.

[0058] The electrical isolation of the phase modulator building blocks in smart photonics platforms needs to be addressed. A possible solution is to add ground contacts close to the phase modulator separated by the isolation section. The ground contacts can in principle be achieved by forming contacts locally on the n-side of the chip. It is arguable that having all passive components contacted and held at a ground voltage connected to the n-side, or a reverse bias voltage of a few volts, would reduce propagation losses and potentially stabilize the optical path length to a higher degree than is currently the case.

[0059] In general, the present invention includes the use of ground contacts and isolation sections to prevent crosstalk between any elements (both active and passive) in a smart photonics platform.The application of an electro-optic phase modulator is just one example of an active component.

Claims

1. A photonic integrated circuit, comprising: A plurality of conductive contacts connected to each other via a conductive layer; a waveguide comprising a first portion of a waveguide layer, and at least one conductive contact of the plurality of conductive contacts; an optical element comprising a second portion of the waveguide layer, and a contact layer for connecting to a voltage source; as well as An isolation portion is disposed between the contact layer and the at least one conductive contact.

2. The photonic integrated circuit according to claim 1, wherein: At least one of the following: The isolation portion is between the optical element and the at least one conductive contact; The at least one conductive contact is located on both sides of the optical element relative to the direction of the light wave in the waveguide; The isolation portion is between the optical element and the at least one conductive contact; or The at least one electrically conductive contact extends substantially across the entire waveguide.

3. The photonic integrated circuit according to claim 1 or 2, wherein: The at least one electrically conductive contact is connected to electrical ground.

4. A photonic integrated circuit according to any one of the preceding claims, comprising a grounding hole arranged for contact between the conductive contact and the n-doped layer, wherein The distance between the edge of the ground hole and the waveguide is at least 10 micrometers, the distance being measured in a direction perpendicular to a direction of propagation of light in the waveguide layer.

5. The photonic integrated circuit according to claim 4, wherein: At least one dimension of a cross-section of the ground hole in a plane parallel to a direction of propagation of light in the waveguide layer is at least 20 micrometers.

6. A photonic integrated circuit according to any one of the preceding claims, wherein: The at least one electrically conductive contact has a length, measured in the direction of propagation of light in the waveguide layer, of at least 20 micrometers.

7. A photonic integrated circuit according to any one of the preceding claims, wherein: The at least one electrically conductive contact includes at least one of titanium, gold, or platinum.

8. A photonic integrated circuit according to any one of the preceding claims, wherein: The optical element is at least one of the following: - an electrorefractive modulator, or -Photodetector.

9. A photonic integrated circuit according to any one of the preceding claims, comprising at least one of the following: an asymmetric Mach-Zehnder interferometer connected to the waveguide; or Connect a tunable laser to the waveguide.

10. A photonic integrated circuit according to any preceding claim, comprising a plurality of asymmetric Mach-Zehnder interferometers connected to the waveguide.

11. A photonic integrated circuit according to any one of the preceding claims, wherein: At least one of the following: The photonic integrated circuit includes a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming at least one of a PIN or PN structure, and the waveguide layer is one of the plurality of semiconductor layers; or The optical element is operable in a reverse biased mode.

12. A method for manufacturing a photonic integrated circuit, comprising: A plurality of conductive contacts connected to each other via a conductive layer; a waveguide comprising a first portion of a waveguide layer, and at least one conductive contact of the plurality of conductive contacts; an optical element comprising a second portion of the waveguide layer, and a contact layer for connecting to a voltage source; as well as An isolation portion is disposed between the contact layer and the at least one conductive contact.

13. The method according to claim 12, wherein: The isolation portion is between the optical element and the at least one conductive contact.

14. The method according to claim 12 or 13, wherein: The at least one electrically conductive contact is located on both sides of the optical element relative to the direction of the light wave in the waveguide.

15. The method according to any one of claims 12 to 14, wherein: The at least one electrically conductive contact extends substantially across the entire waveguide.

16. The method according to any one of claims 12 to 15, wherein the optical element comprises at least one of the following: - an electrorefractive modulator, or -Photodetector.

17. The method according to any one of claims 12 to 16, comprising at least one of the following: an asymmetric Mach-Zehnder interferometer connected to the waveguide; or Connect a tunable laser to the waveguide.

18. A method according to any one of claims 12 to 17, comprising a plurality of asymmetric Mach-Zehnder interferometers connected to the waveguide.

19. The method according to any one of claims 12 to 18, wherein: At least one of the following: The photonic integrated circuit includes a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming at least one of a PIN or PN structure, and the waveguide layer is one of the plurality of semiconductor layers; or The optical element is operable in a reverse biased mode.

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