Multi-processor synchronous reset control system

Abstract

The invention discloses a multi-processor synchronous reset control system, and relates to the technical field of processor reset control, the control system comprises a plurality of processors and a plurality of reset control modules; wherein the reset control modules are connected with the processors in a one-to-one correspondence manner; the output end of the reset control module is connected with a reset pin of each processor through a corresponding path; the reset control module is used for detecting the running state of the correspondingly connected processor and triggering the voltage change of the reset pin of each processor by adjusting the voltage of the output end of the reset control module when the processor runs abnormally; and each processor executes a reset operation based on the voltage change of the self reset pin. According to the technical scheme, when one processor runs abnormally, other processors can respond rapidly, and automatic synchronous reset of the multiple processors in the system is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of processor reset control, and in particular to a multi-processor synchronous reset control system. Background Art

[0002] In the design of processor peripheral circuits, the reset circuit is indispensable. Its main function is to provide a clear signal to reset the processor state to the initial or known safe state in the event of power failure, software crash, hardware abnormality or other situations where the processor needs to be restarted; For multi-processor systems, each processor is usually reset individually. However, this decentralized reset control method may result in other processors being unable to respond in time or reset synchronously when one processor fails to work properly due to a fault. In this case, one processor may fail to work properly while other processors continue to execute tasks, which may lead to resource conflicts, data inconsistencies or drive disorders within the system. In extreme cases, it may even cause serious accidents such as "machine explosions". Summary of the invention

[0003] In order to solve the problem that in a multi-processor system, when one processor fails to work normally due to a fault, other processors cannot respond in time or reset synchronously, thereby causing resource conflicts, data inconsistency or drive disorder within the system, and even machine crash accidents, the present application provides a multi-processor synchronous reset control system.

[0004] In a first aspect, the present application provides a multi-processor synchronous reset control system, which adopts the following technical solution: A multi-processor synchronous reset control system comprises a plurality of processors and a plurality of reset control modules; wherein the reset control modules are connected to the processors one by one; and the output end of the reset control module is connected to the reset pin of each processor through a corresponding path; The reset control module is used to detect the operating status of the corresponding connected processor, and when the processor operates abnormally, it triggers the voltage change of the reset pin of each processor by adjusting the voltage of its own output terminal; Each processor performs a reset operation based on the voltage change of its own reset pin.

[0005] By adopting the above technical solution, each processor is connected to a corresponding reset control module for real-time detection of the operating status of the processor, and adjusting the output voltage according to the detection result, for example, from a high level to a low level; at the same time, since the output end of the reset control module is connected to the reset pin of each processor through different paths, when the output voltage of the reset control module changes, the reset pin voltage of each processor also changes accordingly, so that each processor performs a reset operation. Through such a design, when a processor operates abnormally, other processors can respond quickly, realizing automatic synchronous reset of multiple processors in the system, avoiding internal system resource conflicts, data inconsistency or drive disorder, and even machine explosion accidents.

[0006] In a specific implementation scheme, the multiple processors include a first processor and a second processor, and the multiple reset control modules include a first reset control module and a second reset control module; an input end of the first reset control module is connected to the first processor; an input end of the second reset control module is connected to the second processor; The path between the output end of the first reset control module and the reset pin of the first processor includes a diode D11, and the first reset control module is connected to the cathode of the diode D11; The path between the output end of the first reset control module and the reset pin of the second processor includes a diode D12, and the first reset control module is connected to the cathode of the diode D12; The path between the output end of the second reset control module and the reset pin of the first processor includes a diode D2, and the second reset control module is connected to the cathode of the diode D2; The output end of the second reset control module is connected to the reset pin of the second processor.

[0007] By adopting the above technical solution, when the system includes two processors, by adding a unidirectional conducting diode at the corresponding position in the path, when no reset is required, the output terminals of the first reset control module and the second reset control module maintain a high level, and the reset pins of the first processor and the second processor also maintain a high level; when a processor operates abnormally, the corresponding connected reset control module will set the output terminal level to a low level, the diode will be turned on, so that the reset pin levels of the first processor and the second processor are pulled low, and both processors perform a reset operation.

[0008] In a specific implementation scheme, when the first processor operates normally, the reset pin of the first processor is at a high level; when the second processor operates normally, the reset pin of the second processor is at a high level; The first reset control module and the second reset control module are used to adjust the voltage of their own output terminals from a high level to a low level when detecting that the corresponding connected processor operates abnormally; When the voltage at the output end of the first reset control module is adjusted to a low level, the diode D11 and the diode D12 are both turned on, and the voltage of the reset pin of the first processor and the voltage of the reset pin of the second processor are pulled down, and the first processor and the second processor perform a reset operation synchronously; When the voltage at the output end of the second reset control module is adjusted to a low level, the voltage at the reset pin of the second processor is pulled down, and the diode D2 is turned on to pull down the voltage at the reset pin of the first processor, and the first processor and the second processor synchronously perform a reset operation.

[0009] In a specific implementation scheme, the control system further includes a manual reset module; the manual reset module is connected to one or more of the multiple reset control modules; The manual reset module sends a manual reset signal to a connected reset control module in response to a manual reset operation; The reset control module determines that the user performs a reset operation based on the manual reset signal, and triggers a voltage change of the reset pin of each processor by adjusting the voltage of its own output terminal.

[0010] By adopting the above technical solution, by adding a manual reset module in the structure and connecting it to the input end of any one or more reset control modules, when the user needs to reset all processors according to actual conditions, all processors can be reset synchronously only through the manual reset module, thereby realizing the manual synchronous reset function of the processors.

[0011] In a specific implementation scheme, the manual reset module includes a resistor R1, a resistor R2 and a pull-in switch S1; After the resistor R1 and the resistor R2 are connected in series, one end is connected to the power supply voltage VCC and the other end is grounded; the middle node between the resistor R1 and the resistor R2 is connected to the input end of the corresponding reset control module through the pull-in switch S1.

[0012] In a specific feasible implementation scheme, the pull-in switch S1 switches from an open state to a closed state in response to a manual reset operation, and the supply voltage VCC is divided by the resistor R2 and the resistor R1 to increase the voltage at one end of the reset control module connected to the manual reset module, and the reset control module determines that the user performs a reset operation.

[0013] In a specific implementation manner, the plurality of processors further include a third processor to an nth processor, and the plurality of reset control modules further include a third reset control module to an nth reset control module; Wherein, the input ends of the third reset control module to the nth reset control module are connected to the third processor to the nth processor in a one-to-one correspondence; For each reset control module from the third reset control module to the nth reset control module, the output end of the reset control module is connected to the reset pin of the processor corresponding to the reset control module through a diode in series; the output end of the reset control module is also connected to the first node through a diode in series; the output end of the reset control module is also connected to the second node through a diode in series; The first node is an intermediate connection node between the reset pin of the second processor and the diode D12; the second node is an intermediate connection node between the second reset control module and the diode D2.

[0014] By adopting the above technical solution, when the system includes three or more processors, for the added reset control module, the output end of the reset control module is divided into three paths, one path is connected to the reset pin of the corresponding processor through a diode, one path is connected to the first node through a diode, and the other path is connected to the second node. When any processor in the system is abnormal, through such a connection method, not only can the synchronous reset of each processor be achieved, but also the regular connection is provided, which is easy to expand the system. Only the reset control module corresponding to the processor and three diodes need to be added to incorporate the processor that needs to be synchronously reset into the system, which greatly reduces the cost and the system has a faster response speed.

[0015] In a specific implementation scheme, when the third processor to the nth processor operate normally, the reset pins of the third processor to the nth processor are at a high level; the third reset control module to the nth reset control module are used to adjust the voltage of their own output terminal from a high level to a low level when detecting that the corresponding connected processor operates abnormally; When the voltage at the output end of the first reset control module is adjusted to a low level, the diode D11 and the diode D12 are both turned on, and the voltages of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; the first processor to the nth processor synchronously perform the reset operation; When the voltage at the output end of the second reset control module is adjusted to a low level, the diode D2 is turned on, and the voltages of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; the first processor to the nth processor synchronously perform the reset operation; When the voltage at the output end of any reset control module from the output end of the third reset control module to the nth reset control module is adjusted to a low level, the diode between the voltage-adjusted reset control module and the first node is turned on, the voltage of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; the first processor to the nth processor synchronously execute the reset operation.

[0016] In a specific implementation scheme, when the voltage of the first node is pulled low, the voltage of the reset pin of the second processor is pulled low, and the second processor performs a reset operation; When the voltage of the second node is pulled low, the diode D2 is turned on, the voltage of the reset pin of the first processor is pulled low, and the first processor performs a reset operation; and the diode connected between the reset pin of the i-th processor and the second node is turned on, where i=3, 4, 5, ...n; the voltage of the reset pins of the third to n-th processors is pulled low, and the third to n-th processors perform a reset operation.

[0017] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: The control system of the present application connects each processor to a corresponding reset control module for real-time detection of the operating status of the processor and adjusts the output voltage according to the detection result, for example, from a high level to a low level; at the same time, since the output end of the reset control module is connected to the reset pin of each processor through different paths, when the output voltage of the reset control module changes, the reset pin voltage of each processor also changes accordingly, so that each processor performs a reset operation. Through such a design, when a processor operates abnormally, other processors can respond quickly to achieve automatic synchronous reset of multiple processors in the system, avoiding internal system resource conflicts, data inconsistencies or drive disorders, and even machine explosion accidents. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the overall architecture of a multi-processor synchronous reset control system in an embodiment of the present application; Figure 2 This is a schematic diagram of a connection structure when there are two processors in the system in the embodiment of the present application; Figure 3 This is a schematic diagram of a connection structure when there are three processors in the system in the embodiment of the present application; Figure 4 This is a schematic diagram of a connection structure when there are four or more processors in the system in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0020] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0021] In the description of the embodiments of the present application, the term "multiple" means two or more than two. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals.

[0022] The present application embodiment provides a multi-processor synchronous reset control system, such as Figure 1 As shown, the system includes multiple processors and multiple reset control modules; wherein the reset control modules are connected to the processors one by one; the output end of the reset control module is connected to the reset pin of each processor through a corresponding path; The reset control module is used to detect the operating status of the corresponding connected processor, and when the processor operates abnormally, it triggers the voltage change of the reset pin of each processor by adjusting the voltage of its own output terminal; Each processor performs a reset operation based on the voltage change of its own reset pin.

[0023] Generally speaking, when the reset pin of the processor is at a high level, the processor is not reset, and when the reset pin of the processor becomes a low level, the processor is reset.

[0024] The operation state of the processor includes the power supply voltage operation state and / or the program operation state, and the processor operation abnormality includes the processor power supply voltage abnormality and / or the processor program operation abnormality; Exemplarily, when detecting that the processor power supply voltage is abnormal, the reset control module may use a corresponding voltage detection circuit, and when the processor power supply voltage undergoes a sudden change, such as power-on, power-off, or a large voltage fluctuation, the reset control module determines that the processor is operating abnormally; Exemplarily, when detecting the running status of the processor program, the reset control module can use the peripheral watchdog timer to identify software errors and hardware failures of the processor; when the peripheral watchdog timer does not receive a response from the processor within the set time, that is, the processor fails to "feed the dog" within the specified time, the reset control module determines that the processor is operating abnormally.

[0025] The control system of the present application connects each processor to a corresponding reset control module for real-time detection of the operating status of the processor and adjusts the output voltage according to the detection result, for example, from a high level to a low level; at the same time, since the output end of the reset control module is connected to the reset pin of each processor through different paths, when the output voltage of the reset control module changes, the reset pin voltage of each processor also changes accordingly, so that each processor performs a reset operation. Through such a design, when a processor operates abnormally, other processors can respond quickly to achieve automatic synchronous reset of multiple processors in the system, avoiding internal system resource conflicts, data inconsistencies or drive disorders, and even machine explosion accidents.

[0026] In one possible implementation, refer to Figure 2 , the multiple processors include a first processor and a second processor, the multiple reset control modules include a first reset control module and a second reset control module; the input end of the first reset control module is connected to the first processor; the input end of the second reset control module is connected to the second processor; The path between the output end of the first reset control module and the reset pin of the first processor includes a diode D11, and the first reset control module is connected to the cathode of the diode D11; The path between the output end of the first reset control module and the reset pin of the second processor includes a diode D12, and the first reset control module is connected to the cathode of the diode D12; The path between the output end of the second reset control module and the reset pin of the first processor includes a diode D2, and the second reset control module is connected to the cathode of the diode D2; The output end of the second reset control module is connected to the reset pin of the second processor.

[0027] In a possible implementation manner, when the first processor operates normally, the reset pin voltage of the first processor is at a high level; when the second processor operates normally, the reset pin voltage of the second processor is at a high level; The first reset control module and the second reset control module are used to adjust the voltage of their own output terminals from a high level to a low level when detecting that the corresponding connected processor operates abnormally; When the voltage at the output end of the first reset control module is adjusted to a low level, the diode D11 and the diode D12 are both turned on, and the voltage of the reset pin of the first processor and the voltage of the reset pin of the second processor are pulled down, and the first processor and the second processor perform a reset operation synchronously; When the voltage at the output end of the second reset control module is adjusted to a low level, the voltage at the reset pin of the second processor is pulled down, and the diode D2 is turned on to pull down the voltage at the reset pin of the first processor, and the first processor and the second processor synchronously perform a reset operation.

[0028] In the above connection mode, when the system includes two processors, by adding a unidirectional conducting diode at the corresponding position in the path, when no reset is required, the output voltage of the first reset control module and the second reset control module remains at a high level, and the reset pins of the first processor and the second processor also remain at a high level; when a processor operates abnormally, the correspondingly connected reset control module will set the output voltage low, and the corresponding diode will be turned on, so that the reset pin voltage of the first processor and the second processor is pulled down, and the two processors perform the reset operation synchronously.

[0029] In a possible implementation, the multi-processor synchronous reset control system further includes a manual reset module; the manual reset module is connected to one or more of the multiple reset control modules; Figure 1 and Figure 2 As shown, the manual reset module is connected to the input end of the first reset control module.

[0030] The manual reset module sends a manual reset signal to a connected reset control module in response to a manual reset operation; The reset control module determines that the user performs a reset operation based on the manual reset signal, and triggers a voltage change of the reset pin of each processor by adjusting the voltage of its own output terminal; Likewise, each processor performs a reset operation based on the voltage change of its own reset pin.

[0031] Furthermore, the manual reset module can adjust the voltage of its own output terminal in response to the manual reset operation, so that the reset control module can sense whether the user has performed the reset operation.

[0032] By adding a manual reset module to the structure and connecting it to the input end of any one or more reset control modules, when the user needs to reset all processors according to actual conditions, all processors can be reset synchronously only through the manual reset module, thereby realizing the manual synchronous reset function of the processors.

[0033] In one possible implementation, refer to Figure 2 , the manual reset module includes a resistor R1, a resistor R2 and a pull-in switch S1; After the resistor R1 and the resistor R2 are connected in series, one end is connected to the power supply voltage VCC and the other end is grounded; the middle node between the resistor R1 and the resistor R2 is connected to the input end of the corresponding reset control module through the pull-in switch S1.

[0034] The following is a detailed description of the working principle of this part: The pull-in switch S1 switches from an open state to a closed state in response to a manual reset operation, and the supply voltage VCC is divided by the resistor R2 and the resistor R1 to increase the voltage at one end of the reset control module connected to the manual reset module, and the reset control module determines that the user performs a reset operation.

[0035] That is to say, when the user does not press the suction switch S1 and does not perform the manual reset operation, the suction switch S1 is disconnected, and the end connected between the reset control module and the manual reset module is at a low level; When the user presses the pull-in switch S1 to perform a reset operation, the pull-in switch S1 is closed, and the power supply voltage VCC is divided by the resistor R2 and the resistor R1, and the level of one end connected to the reset control module and the manual reset module is pulled up, and the reset control module determines that the user performs a reset operation; Therefore, the reset control module can determine whether the user has performed a manual reset operation by sensing the voltage at one end connected to the manual reset module. And after the pull-in switch S1 is pressed, it will automatically disconnect after a certain period of time, which is convenient for the user's operation next time.

[0036] In one possible implementation, refer to Figure 3 , when there are three processors that need to be detected in the system, the multiple processors further include a third processor, and the multiple reset control modules further include a third reset control module; Wherein, the input end of the third reset control module is correspondingly connected to the third processor; The output end of the third reset control module is connected to the reset pin of the third reset control module through a diode in series, and the output end of the third reset control module is connected to the cathode of the diode, that is, D31 in the figure; the output end of the third reset control module is also connected to the first node through a diode in series, and the output end of the third reset control module is connected to the cathode of the diode, that is, D32 in the figure; the output end of the third reset control module is also connected to the second node through a diode in series, and the output end of the third reset control module is connected to the anode of the diode, that is, D33 in the figure; The first node is an intermediate connection node between the reset pin of the second processor and the diode D12; the second node is an intermediate connection node between the second reset control module and the diode D2.

[0037] When the third processor operates normally, the reset pin of the third processor is at a high level; the third reset control module is used to adjust the voltage of its output terminal from a high level to a low level when it detects that the third processor operates abnormally; Through such a connection mode: when the voltage at the output end of the first reset control module is adjusted to a low level, the diodes D11 and D12 are both turned on, and the voltages of the first node and the second node are pulled down, so that the diode D33 is turned on, and the reset pin voltage of the third processor is also pulled down; the first processor to the third processor synchronously perform the reset operation; When the voltage at the output end of the second reset control module is adjusted to a low level, the diode D2 is turned on, and the voltages of the first node and the second node are pulled down, and the diode D33 is also turned on, and the reset pin voltage of the third processor is also pulled down; the first processor to the third processor synchronously perform the reset operation; When the voltage at the output end of the third reset control module is adjusted to a low level, the diode connected between the output end of the third reset control module and the reset pin of the third processor is turned on, that is, the diode D31, and the voltage of the reset pin of the third processor is pulled down; at the same time, the diode between the third reset control module and the first node is turned on, that is, the diode D32, thereby pulling down the voltages of the first node and the second node, so that the reset pin voltages of the first processor and the second processor are both pulled down; the first processor to the third processor synchronously perform the reset operation.

[0038] Furthermore, when the number of processors in the system is four or more, for the connection from the fourth processor to the nth processor, it is only necessary to refer to the relevant connection of the third processor, and a comprehensive description is given below: In one possible implementation, refer to Figure 4 , the multiple processors further include a third processor to an nth processor, and the multiple reset control modules further include a third reset control module to an nth reset control module; n≥3, n is an integer.

[0039] Wherein, the input ends of the third reset control module to the nth reset control module are connected to the third processor to the nth processor in a one-to-one correspondence; For each reset control module from the third reset control module to the nth reset control module, the output end of the reset control module is connected to the reset pin of the processor corresponding to the reset control module through a diode connected in series, and the output end of the reset control module is connected to the cathode of the diode; the output end of the reset control module is also connected to the first node through a diode connected in series, and the output end of the reset control module is connected to the cathode of the diode; the output end of the reset control module is also connected to the second node through a diode connected in series, and the output end of the reset control module is connected to the anode of the diode; The first node is an intermediate connection node between the reset pin of the second processor and the diode D12; the second node is an intermediate connection node between the second reset control module and the diode D2.

[0040] Those skilled in the art can understand that the output end of the above-mentioned reset control module is connected to the reset pin of the processor corresponding to the reset control module after being connected in series with a diode, that is, the output end of the third reset control module is connected to the reset pin of the third processor after being connected in series with a diode... The output end of the nth reset control module is connected to the reset pin of the nth processor after being connected in series with a diode.

[0041] For ease of understanding, the following Figure 4 , the connection relationship between the newly added third reset control module and the nth reset control module is explained: The output end of the third reset control module is connected to the reset pin of the third processor through a series diode D31, and the output end of the third reset control module is connected to the cathode of the diode D31; the output end of the third reset control module is also connected to the first node through a series diode D32, and the output end of the third reset control module is connected to the cathode of the diode D32; the output end of the third reset control module is also connected to the second node through a series diode D33, and the output end of the third reset control module is connected to the anode of the diode D33.

[0042] Similarly, the output end of the fourth reset control module is connected to the reset pin of the fourth processor through a series diode D41, and the output end of the fourth reset control module is connected to the cathode of the diode D41; the output end of the fourth reset control module is also connected to the first node through a series diode D42, and the output end of the fourth reset control module is connected to the cathode of the diode D42; the output end of the fourth reset control module is also connected to the second node through a series diode D43, and the output end of the fourth reset control module is connected to the anode of the diode D43.

[0043] Similarly, the output end of the nth reset control module is connected to the reset pin of the nth processor through a series diode Dn1, and the output end of the nth reset control module is connected to the cathode of the diode Dn1; the output end of the nth reset control module is also connected to the first node through a series diode Dn2, and the output end of the nth reset control module is connected to the cathode of the diode Dn2; the output end of the nth reset control module is also connected to the second node through a series diode Dn3, and the output end of the nth reset control module is connected to the anode of the diode Dn3. The third reset control module to the nth reset control module all adopt such a connection method, which will not be described one by one here.

[0044] Therefore, when the system contains three or more processors, for the added reset control module, the output end of the reset control module is divided into three paths, one path is connected to the reset pin of the corresponding processor through a diode, one path is connected to the first node through a diode, and the other path is connected to the second node. When any processor in the system is abnormal, through such a connection method, not only can the synchronous reset of each processor be achieved, but also the regular connection is easy to expand the system. Only the reset control module corresponding to the processor and three diodes need to be added to incorporate the processor that needs to be synchronously reset into the system, which greatly reduces the cost and the system has a faster response speed.

[0045] In a possible implementation, when the system includes three or more processors whose operating states need to be detected, the working process is as follows: When the third to nth processors operate normally, the reset pins of the third to nth processors are at a high level; the third to nth reset control modules are used to adjust the voltage of their own output terminals from a high level to a low level when detecting that the corresponding connected processors operate abnormally; When the voltage at the output end of the first reset control module is adjusted to a low level, the diode D11 and the diode D12 are both turned on, and the voltages of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; the first processor to the nth processor synchronously perform the reset operation; When the voltage at the output end of the second reset control module is adjusted to a low level, the diode D2 is turned on, and the voltages of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; the first processor to the nth processor synchronously perform the reset operation; When the voltage at the output end of any reset control module from the output end of the third reset control module to the nth reset control module is adjusted to a low level, the diode between the voltage-adjusted reset control module and the first node is turned on, the voltage of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; the first processor to the nth processor synchronously execute the reset operation.

[0046] For example, when the voltage at the output end of the third reset control module is adjusted to a low level, the diode between the third reset control module and the first node is turned on, that is, the diode D32 is turned on, thereby pulling down the voltages of the first node and the second node; similarly, when the voltage at the output end of the nth reset control module is a low level, the diode between the nth reset control module and the first node is turned on, that is, the diode Dn2 is turned on, thereby pulling down the voltages of the first node and the second node.

[0047] The following specifically describes the principle that the first processor to the nth processor synchronously perform the reset operation when the voltages of the first node and the second node are pulled low during the operation of the system: When the voltage of the first node is pulled low, the voltage of the reset pin of the second processor is pulled low, and the second processor performs a reset operation; When the voltage of the second node is pulled low, the diode D2 is turned on, and the voltage of the reset pin of the first processor is pulled low, and the first processor performs a reset operation; and because the voltage of the second node is pulled low, the diode connected between the reset pin of the i-th processor and the second node can be turned on, where i=3, 4, 5, ... n; that is, the diode connected between the reset pin of the third processor and the second node is turned on, the diode connected between the reset pin of the fourth processor and the second node is turned on ... the diode connected between the reset pin of the n-th processor and the second node is turned on, that is, Figure 4 The diodes D31 and D33 are turned on, the diodes D41 and D43 are turned on, ... the diodes Dn1 and Dn3 are turned on; thereby the voltage of the reset pins of the third to nth processors is pulled down, and the third to nth processors perform a reset operation.

[0048] Those skilled in the art can understand that, according to the same principle, if there is a manual reset module in the structure, then the reset control module connected to the manual reset module senses the voltage at the corresponding connection end, determines that the user performs a reset operation, and then adjusts the voltage at its own output end from a high level to a low level, and the corresponding diode is turned on, thereby still achieving synchronous reset of multiple processors, which will not be elaborated here.

[0049] In actual use, the system usually does not contain too many processors, and the commonly used ones are the main DSP, the secondary DSP and the CPLD. For example, the first processor is the main DSP, the second processor is the secondary DSP, and the third processor is the CPLD.

[0050] To further facilitate understanding, the following is a complete description of the system's working process when a processor runs abnormally in the entire system: When the voltage at the output end of the first reset control module is adjusted to a low level, the diode D11 is turned on to pull down the reset pin voltage of the first processor, and the first processor performs a reset operation; the diode D12 is turned on to pull down the reset pin voltage of the second processor, the first node and the second node voltages, and the second processor performs a reset operation; and, since the second node voltage is pulled down, the diode D33 and the diode D31 are turned on to pull down the reset pin voltage of the third processor, and the third processor performs a reset operation; since the second node voltage is pulled down, the diode D43 and the diode D41 are turned on to pull down the reset pin voltage of the fourth processor, and the fourth processor performs a reset operation... until the second node voltage is pulled down, the diode Dn3 and the diode Dn1 are turned on to pull down the reset pin voltage of the nth processor, and the nth processor performs a reset operation; therefore, the first processor to the nth processor synchronously perform the reset operation.

[0051] When the voltage at the output end of the second reset control module is adjusted to a low level, the reset pin voltage of the second processor, the first node and the second node voltages are pulled down, and the second processor performs a reset operation; the diode D2 is turned on, the reset pin voltage of the first processor is pulled down, and the first processor performs a reset operation; similarly, referring to the above description, since the second node voltage is pulled down, the diode D33 and the diode D31 are turned on, the reset pin voltage of the third processor is pulled down, and the third processor performs a reset operation; since the second node voltage is pulled down, the diode D43 and the diode D41 are turned on, the reset pin voltage of the fourth processor is pulled down, and the fourth processor performs a reset operation... until the second node voltage is pulled down, the diode Dn3 and the diode Dn1 are turned on, the reset pin voltage of the nth processor is pulled down, and the nth processor performs a reset operation; therefore, the first processor to the nth processor synchronously perform the reset operation.

[0052] When the voltage at the output end of the third reset control module is adjusted to a low level, the diode D32 is turned on to pull down the voltages of the first node and the second node, so that the first processor to the nth processor can synchronously perform the reset operation, which will not be repeated here.

[0053] When the voltage at the output end of the fourth reset control module is adjusted to a low level, the diode D42 is turned on to pull down the voltages of the first node and the second node, so that the first processor to the nth processor can synchronously perform the reset operation, which will not be repeated here.

[0054] Those skilled in the art will appreciate that when the voltage at the output end of the fifth reset control module, the sixth reset control module, the seventh reset control module... or the nth reset control module is adjusted to a low level, the first processor to the nth processor may synchronously execute a reset operation. The principle may refer to the above description and will not be elaborated here one by one.

[0055] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A multi-processor synchronous reset control system, characterized in that: It includes multiple processors and multiple reset control modules; wherein the reset control modules are connected to the processors one by one; the output end of the reset control module is connected to the reset pin of each processor through a corresponding path; The reset control module is used to detect the operating status of the corresponding connected processor, and when the processor operates abnormally, it triggers the voltage change of the reset pin of each processor by adjusting the voltage of its own output terminal; Each processor performs a reset operation based on the voltage change of its own reset pin.

2. The multi-processor synchronous reset control system according to claim 1, characterized in that: The multiple processors include a first processor and a second processor, and the multiple reset control modules include a first reset control module and a second reset control module; an input end of the first reset control module is connected to the first processor; an input end of the second reset control module is connected to the second processor; The path between the output end of the first reset control module and the reset pin of the first processor includes a diode D11, and the first reset control module is connected to the cathode of the diode D11; The path between the output end of the first reset control module and the reset pin of the second processor includes a diode D12, and the first reset control module is connected to the cathode of the diode D12; The path between the output end of the second reset control module and the reset pin of the first processor includes a diode D2, and the second reset control module is connected to the cathode of the diode D2; The output end of the second reset control module is connected to the reset pin of the second processor.

3. The multi-processor synchronous reset control system according to claim 2, characterized in that: When the first processor operates normally, the reset pin voltage of the first processor is at a high level; when the second processor operates normally, the reset pin voltage of the second processor is at a high level; The first reset control module and the second reset control module are used to adjust the voltage of their own output terminals from a high level to a low level when detecting that the corresponding connected processor operates abnormally; When the voltage at the output end of the first reset control module is adjusted to a low level, the diode D11 and the diode D12 are both turned on, and the voltage of the reset pin of the first processor and the voltage of the reset pin of the second processor are pulled down, and the first processor and the second processor perform a reset operation synchronously; When the voltage at the output end of the second reset control module is adjusted to a low level, the voltage at the reset pin of the second processor is pulled down, and the diode D2 is turned on to pull down the voltage at the reset pin of the first processor, and the first processor and the second processor synchronously perform a reset operation.

4. The multi-processor synchronous reset control system according to claim 1, characterized in that: It also includes a manual reset module; the manual reset module is connected to one or more of the multiple reset control modules; The manual reset module sends a manual reset signal to a connected reset control module in response to a manual reset operation; The reset control module determines that the user performs a reset operation based on the manual reset signal, and triggers a voltage change of the reset pin of each processor by adjusting the voltage of its own output terminal.

5. The multi-processor synchronous reset control system according to claim 4, characterized in that: The manual reset module includes a resistor R1, a resistor R2 and a pull-in switch S1; After the resistor R1 and the resistor R2 are connected in series, one end is connected to the power supply voltage VCC and the other end is grounded; the middle node between the resistor R1 and the resistor R2 is connected to the input end of the corresponding reset control module through the pull-in switch S1.

6. The multi-processor synchronous reset control system according to claim 5, characterized in that: The pull-in switch S1 switches from an open state to a closed state in response to a manual reset operation, and the supply voltage VCC is divided by the resistor R2 and the resistor R1 to increase the voltage at one end of the reset control module connected to the manual reset module, and the reset control module determines that the user performs a reset operation.

7. The multi-processor synchronous reset control system according to claim 2, characterized in that: The plurality of processors further include a third processor to an nth processor, and the plurality of reset control modules further include a third reset control module to an nth reset control module; Wherein, the input ends of the third reset control module to the nth reset control module are connected to the third processor to the nth processor in a one-to-one correspondence; For each reset control module from the third reset control module to the nth reset control module, the output end of the reset control module is connected to the reset pin of the processor corresponding to the reset control module through a diode in series; the output end of the reset control module is also connected to the first node through a diode in series; the output end of the reset control module is also connected to the second node through a diode in series; The first node is an intermediate connection node between the reset pin of the second processor and the diode D12; the second node is an intermediate connection node between the second reset control module and the diode D2.

8. The multi-processor synchronous reset control system according to claim 7, characterized in that: When the third to nth processors operate normally, the reset pins of the third to nth processors are at a high level; the third to nth reset control modules are used to adjust the voltage of their own output terminals from a high level to a low level when detecting that the corresponding connected processors operate abnormally; When the voltage at the output end of the first reset control module is adjusted to a low level, the diode D11 and the diode D12 are both turned on, and the voltages of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; the first processor to the nth processor synchronously perform the reset operation; When the voltage at the output end of the second reset control module is adjusted to a low level, the diode D2 is turned on, and the voltages of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; the first processor to the nth processor synchronously perform the reset operation; When the voltage of any reset control module output terminal from the output terminal of the third reset control module to the nth reset control module is adjusted to a low level, the diode between the reset control module with voltage adjustment and the first node is turned on, and the voltage of the first node and the second node are pulled down, so that the reset pin voltages of the first processor to the nth processor are all pulled down; The first processor to the nth processor synchronously perform a reset operation.

9. The multi-processor synchronous reset control system according to claim 8, characterized in that: When the voltage of the first node is pulled low, the voltage of the reset pin of the second processor is pulled low, and the second processor performs a reset operation; When the voltage of the second node is pulled low, the diode D2 is turned on, the voltage of the reset pin of the first processor is pulled low, and the first processor performs a reset operation; and the diode connected between the reset pin of the i-th processor and the second node is turned on, where i=3, 4, 5, ...n; the voltage of the reset pins of the third to n-th processors is pulled low, and the third to n-th processors perform a reset operation.

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