Novel system and method for remotely upgrading FPGA (field programmable gate array) program by SOC (system on chip)

Abstract

The invention discloses a novel system and method for remotely upgrading an FPGA program through an SOC chip. The method comprises the steps that a write bit stream enabling command is sent to the FPGA chip, the preparation state of the write bit stream enabling command is monitored, and a preset upgrade package file is sent after erasure is confirmed to be completed. And the system continuously monitors the write bit stream and the check state to ensure that the data is correctly written and checked. In the upgrading process, if interruption occurs, the FPGA loads and recovers the bit stream to keep stable, and attempts to upgrade again after the system is restarted. In addition, after the upgrade package file is sent, a bit stream end mark is sent to trigger the FPGA to store data. Before upgrading, the system also obtains the version number of the current FPGA program and compares the version number with the version number of the upgrade package file, and upgrading is carried out only when the current version is low. According to the method, the upgrading process is simplified, the FPGA program upgrading efficiency and reliability are improved, and better use experience and maintenance convenience are provided for users.

Description

Technical Field

[0001] The present invention relates to the field of FPGA program upgrade technology, in particular to a novel system and method for remotely upgrading FPGA programs on a SOC chip. Background Art

[0002] In electronic devices and systems, field programmable gate arrays (FPGAs) are widely used due to their high flexibility and reconfigurability. FPGAs allow users to program and modify hardware logic according to actual needs after the device is deployed, thereby meeting the ever-changing application requirements. However, with the continuous deepening and expansion of FPGA applications, how to efficiently and reliably upgrade its programs has become an urgent problem to be solved.

[0003] In the traditional FPGA program upgrade method, it is usually necessary to use a specific upgrade interface or external device to complete the upgrade process. This method not only increases the complexity and cost of the system, but also various unstable factors may occur during the upgrade process, such as communication interruption, data loss, etc., which may lead to upgrade failure or system crash. Especially in some critical application scenarios, such as router connectivity detection systems, any errors in the upgrade process may cause the failure of the entire system, thereby affecting the normal operation of the network and the user experience. In addition, traditional FPGA program upgrade methods often lack effective status monitoring and error handling mechanisms. During the upgrade process, users cannot understand the status and progress of the upgrade in real time, nor can they handle and recover in time when errors occur. This not only reduces the reliability and efficiency of the upgrade, but also brings inconvenience and additional maintenance costs to users.

[0004] Therefore, it is necessary to provide a new system and method for remotely upgrading FPGA programs on SOC chips to solve the problems of complex upgrade operations, lack of status monitoring and error handling mechanisms, and insufficient interrupt recovery during FPGA program upgrades in the prior art. Summary of the invention

[0005] The purpose of the present invention is to provide a novel system and method for remotely upgrading FPGA programs on SOC chips, which is used to solve the problems of complex upgrading operations, lack of status monitoring and error handling mechanisms, and insufficient interrupt recovery during FPGA program upgrading in the prior art.

[0006] The present invention solves the above problems through the following technical solutions:

[0007] A novel system and method for remotely upgrading FPGA programs of a SOC chip, comprising a SOC main control chip and an FPGA chip, wherein the SOC main control chip comprises a plurality of universal ports; the SOC main control chip and the FPGA chip are communicatively connected via the plurality of universal ports, and the plurality of universal ports comprise a status indication port and a plurality of communication protocol ports;

[0008] When performing an FPGA program upgrade, the SOC main control chip sends a write bitstream enable command to the FPGA chip through the multiple communication protocol ports, and monitors the command preparation state of the status indication port. When it is detected that the command preparation state is in the first state, the erase completion flag returned by the FPGA chip is read, a preset FPGA program upgrade package file is obtained, and the FPGA program upgrade package file is sent to the FPGA chip; the SOC main control chip monitors the write bitstream completion state of the status indication port. When it is detected that the write bitstream completion state is in the first state, the write bitstream completion flag returned by the FPGA chip is read, and the SOC main control chip The SOC main control chip sends a read bit stream enable command to the FPGA chip, so that the FPGA chip performs verification based on the read bit stream enable command; the SOC main control chip monitors the verification status of the status indication port, and when it is detected that the verification status is the first state, reads the verification completion flag returned by the FPGA chip, sends an open switch enable command to the FPGA chip, and monitors the open switch completion status of the status indication port, when the open switch completion status is the first state, reads the open switch completion flag returned by the FPGA chip, and sends a hot start enable command to restart the SOC main control chip to complete the FPGA program upgrade.

[0009] Furthermore, if the FPGA program upgrade process is interrupted, when the system for remotely upgrading the FPGA program with the new SOC chip is restarted, the FPGA chip loads the recovery bit stream, and the SOC main control chip detects the version number of the recovery bit stream and triggers the FPGA program upgrade again.

[0010] Furthermore, after the FPGA program upgrade package file is sent, the SOC main control chip sends a bit stream end mark to the FPGA chip, and the FPGA chip stores the FPGA program upgrade package file according to the bit stream end mark.

[0011] Furthermore, it also includes: before performing an FPGA program upgrade, the SOC main control chip obtains the current FPGA program version number, and determines whether the current FPGA program version number is different from the preset FPGA program upgrade package file version number; if the current FPGA program version number is lower than the preset FPGA program upgrade package file version number, the FPGA program is upgraded.

[0012] A FPGA program upgrade method, applied to a SOC main control chip, comprising:

[0013] Send a write bit stream enable command to the FPGA chip and monitor the command readiness status of the status indicator port;

[0014] When it is detected that the command preparation state is the first state, read the erase completion flag returned by the FPGA chip, send a preset FPGA program upgrade package file to the FPGA chip, and monitor the write bit stream completion state of the status indication port;

[0015] When it is monitored that the write bit stream completion state is the first state, read the FPGA write bit stream completion flag, send a read bit stream enable command to the FPGA chip, so that the FPGA chip performs verification based on the read bit stream enable command, and monitor the verification state of the status indication port;

[0016] When it is detected that the verification state is the first state, the FPGA verification completion flag is read, a switch enable command is sent to the FPGA chip, and the switch completion state of the status indication port is monitored;

[0017] When the switch-on completion state is the first state, the switch-on completion flag is read, and a restart is performed based on the sent hot start enable command to complete the FPGA program upgrade.

[0018] Further, it is characterized in that if the FPGA program upgrade process is interrupted, when the SOC main control chip is restarted, the FPGA chip loads the recovery bit stream, and the method also includes: when the version number of the recovery bit stream is detected, the FPGA program upgrade is triggered again.

[0019] Furthermore, it also includes: after the FPGA program upgrade package file is sent, a bit stream end mark is sent to the FPGA chip, so that the FPGA chip stores the FPGA program upgrade package file according to the bit stream end mark.

[0020] Furthermore, before performing an FPGA program upgrade, the method also includes: obtaining a current FPGA program version number, and determining whether the current FPGA program version number is different from a preset FPGA program upgrade package file version number; if the current FPGA program version number is lower than the preset FPGA program upgrade package file version number, performing an FPGA program upgrade.

[0021] Compared with the prior art, the present invention has the following advantages and beneficial effects: the present invention utilizes multiple general ports (GPIO ports) of the SOC main control chip to establish a stable communication connection with the FPGA chip, and realizes efficient and reliable upgrading of the FPGA program through precise status indication and error handling mechanism. This method not only simplifies the upgrading process, improves the reliability and efficiency of the upgrading, but also provides users with better usage experience and maintenance convenience. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the system structure of the present invention;

[0023] Figure 2 The figure is a flow chart of the method of the present invention. DETAILED DESCRIPTION

[0024] To make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described in detail below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, and the embodiments of the present invention are not limited thereto. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0025] In the following description, the terms "first\second\third" and the like are only used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0026] Embodiment 1:

[0027] Combined with Figure 1 As shown, a novel system for remotely upgrading FPGA programs of SOC chips includes a SOC main control chip and an FPGA chip, wherein the SOC main control chip includes a plurality of universal ports; the SOC main control chip and the FPGA chip are communicatively connected via the plurality of universal ports, and the plurality of universal ports include a status indication port and a plurality of communication protocol ports;

[0028] When performing an FPGA program upgrade, the SOC main control chip sends a write bitstream enable command to the FPGA chip through the multiple communication protocol ports, and monitors the command preparation state of the status indication port. When it is detected that the command preparation state is in the first state, the erase completion flag returned by the FPGA chip is read, a preset FPGA program upgrade package file is obtained, and the FPGA program upgrade package file is sent to the FPGA chip; the SOC main control chip monitors the write bitstream completion state of the status indication port. When it is detected that the write bitstream completion state is in the first state, the write bitstream completion flag returned by the FPGA chip is read, and the SOC main control chip The SOC main control chip sends a read bit stream enable command to the FPGA chip, so that the FPGA chip performs verification based on the read bit stream enable command; the SOC main control chip monitors the verification status of the status indication port, and when it is detected that the verification status is the first state, reads the verification completion flag returned by the FPGA chip, sends an open switch enable command to the FPGA chip, and monitors the open switch completion status of the status indication port, when the open switch completion status is the first state, reads the open switch completion flag returned by the FPGA chip, and sends a hot start enable command to restart the SOC main control chip to complete the FPGA program upgrade.

[0029] Specifically, the core structure of an FPGA program upgrade system includes a SOC main control chip and an FPGA chip, which are connected to each other through multiple general ports, namely GPIO ports. Among these general ports, one is specially designated as a status indication port, namely RDready, which is used to reflect the current status information of the FPGA chip. In addition, there are multiple communication protocol ports, such as SCLK, CS, MOSI and MISO, which jointly support data transmission during the FPGA program upgrade process. When the FPGA needs to be upgraded, the SOC main control chip will first send a write bit stream enable command to the FPGA chip through those communication protocol ports. The purpose of this command is to start the write bit stream process of the FPGA chip, that is, to write new program data to the FPGA. At the same time, the SOC main control chip will continue to monitor the status indication port RDready to determine whether the FPGA chip is ready to receive subsequent data. Once the status indication port shows that the command preparation state is the first state, such as a logic high level 1, this means that the FPGA chip has completed the necessary preparations and can receive data. At this time, the SOC main control chip will read the erase completion flag returned by the FPGA chip to confirm that the old program data has been erased. Next, the SOC main control chip will obtain the preset FPGA program upgrade package file, which contains the new program data, and then send it to the FPGA chip through the communication protocol port. In the process of sending data, the SOC main control chip will continue to monitor the status indication port to confirm whether the write bitstream process is successfully completed. When the status indication port shows that the write bitstream completion status is the first state, it means that the new program data has been successfully written into the FPGA chip. At this time, the SOC main control chip will read the write bitstream completion flag returned by the FPGA chip and send a read bitstream enable command to the FPGA chip. The purpose of this command is to allow the FPGA chip to start verifying the newly written program data to ensure the integrity and accuracy of the data. During the verification process, the SOC main control chip will also monitor the status indication port to track the progress of the verification. When the status indication port shows that the verification status is the first state, it means that the verification is successful and there is no problem with the new program data. At this time, the SOC main control chip will read the verification completion flag returned by the FPGA chip and send an open switch enable command to the FPGA chip. This command is to allow the FPGA chip to switch to the new program version so that it can start using it. After the FPGA chip successfully turns on the switch of the new program version, the SOC main control chip will monitor the status indication port again to confirm whether the switch status is stable. When the status indication port shows that the switch-on completion status is the first state, it means that the FPGA chip has successfully switched to the new program version. At this time, the SOC main control chip will read the switch-on completion flag returned by the FPGA chip and send a hot start enable command.This command will trigger the restart of the SOC main control chip, thus completing the entire FPGA program upgrade process. After the restart, the FPGA chip will run the new program version.

[0030] For example, taking reading the FPGA version number as an example to illustrate the communication method, in the serial port remote upgrade method provided by the Logos series FPGA devices, the PC first needs to send 0xe7 0xe7 0xe7 0xe7 0x80, a total of 5 bytes, and then wait for the FPGA's response. The interaction format between Soc main control chip and FPGA is as follows: both interact through two bytes of CMD+DATA. The communication between Soc main control chip and FPGA realizes the sending method of the above 5 bytes as follows: when Soc main control chip writes data, the corresponding CMD is written as 0x00, that is, CMD+DATA is written, a total of two bytes; when Soc main control chip reads data, the corresponding CMD is read as 0x80. First, Soc main control chip writes 0x80 to FPGA. After the first byte, Soc main control chip obtains the data to be read from MISO signal; each time Soc main control chip interacts with FPGA, it is a question-and-answer format, that is, first initiate a command, and then read the response data. After the command is initiated, the internal FPGA needs to execute for a period of time, so it is necessary to wait until the internal state of FPGA is ready before reading, and judge whether the internal return data of FPGA is ready by judging RDready signal:

[0031] When RDready is 0, it means that FPGA is not ready yet and needs to wait;

[0032] When RDready is 1, it means that the FPGA is ready and can initiate SPI read.

[0033] Specifically, the Soc main control chip initiates 5 SPI transmissions, namely:

[0034] 0x00+0xE7, 0x00+0xE7, 0x00+0xE7, 0x00+0xE7, 0x00+0x80

[0035] The Soc main control chip reads the RDready signal until RDready is 1;

[0036] The Soc main control chip initiates SPI reading, first writes read CMD 0x80, and then reads a byte, that is, 0x80+RDdata is a read. After each read, it determines whether RDready is 0. If it is not 0, the SPI reading is initiated in a loop until RDready is 0.

[0037] Through such a design, the FPGA program upgrade system can achieve efficient and reliable program updates. During the entire process, the SOC main control chip and the FPGA chip communicate and control through multiple universal ports to ensure the accuracy and stability of data transmission. At the same time, the system also tracks the upgrade progress and status through the monitoring status indicator port so that problems can be handled in a timely manner.

[0038] As an implementation method, if the FPGA program upgrade process is interrupted, when the system for remotely upgrading the FPGA program with the new SOC chip is restarted, the FPGA chip loads the recovery bit stream, and after the SOC main control chip detects the version number of the recovery bit stream, it triggers the FPGA program upgrade again.

[0039] Specifically, the FPGA chip configures its internal logic functions by loading specific bitstream files, which contain instructions that define how the FPGA works. If the upgrade is interrupted during the upgrade process, such as due to a sudden power outage, the FPGA may be left in an incomplete or inconsistent state, resulting in failure to work properly. In order to solve this problem, a new system and method are designed to deal with upgrade interruptions when remotely upgrading the FPGA program. Specifically, when an interruption occurs during the FPGA program upgrade (for example, a sudden power outage at some point in the upgrade process), the system will take a series of recovery measures. When the system restarts, the FPGA chip will not try to load the upgrade file that may be damaged or incomplete, but will load a predefined recovery bitstream, which is usually called a "GOLDEN bitstream". The GOLDEN bitstream is a bitstream file in a known good state that contains instructions to ensure that the FPGA can basically operate and respond. The purpose of loading the GOLDEN bitstream is to restore the FPGA to a stable and predictable state, thereby avoiding unpredictable behavior caused by upgrade interruptions. Next, the SOC (system-on-chip) main control chip in the system will play a role. After the SOC main control chip detects that the FPGA has been loaded with the GOLDEN bitstream, it will read the version number of the restored bitstream. This step is to confirm the current state of the FPGA and ensure the correctness of subsequent operations. Once the version number is confirmed, the SOC main control chip will trigger the upgrade process of the FPGA program again. This upgrade will start from scratch, using a complete, unaffected bitstream file to ensure that the FPGA can be successfully upgraded to the expected new version.

[0040] For example, suppose a user is remotely upgrading the FPGA program for the smart door lock at home to improve its security and functionality. If during the upgrade process, there is a sudden power outage at home, the upgrade is forced to be interrupted. When the power is restored and the system is restarted, the FPGA chip in the smart door lock will not try to continue loading the potentially damaged upgrade file, but will first load a safe GOLDEN bitstream to ensure that the basic functions of the door lock are not affected. Subsequently, the SOC main control chip in the smart door lock will detect the loading of the GOLDEN bitstream, and after confirming its version number, it will start the upgrade process again, this time ensuring that the upgrade is completed completely and without error.

[0041] In this way, even if an interruption occurs during the FPGA program upgrade, the bit stream can be restored by loading and re-triggering the upgrade to ensure that the FPGA can eventually be successfully upgraded to the expected state, thereby ensuring the normal operation and performance of the device.

[0042] As an implementation mode, after the FPGA program upgrade package file is sent, the SOC main control chip sends a bit stream end mark to the FPGA chip, and the FPGA chip stores the FPGA program upgrade package file according to the bit stream end mark.

[0043] Specifically, when the SOC main control chip sends the upgrade package files to the FPGA chip, these files contain the bitstream information that defines the new functions of the FPGA. Once the transmission of these files is completed, the SOC main control chip will send a special signal to the FPGA chip, which is called the "bitstream end flag". The function of this flag is to tell the FPGA chip that the currently transmitted bitstream data has ended and that subsequent processing or storage operations can begin. After receiving this bitstream end flag, the FPGA chip will know that the upgrade package file has been received completely and correctly. At this time, the FPGA chip will store the received bitstream data according to the internal logic and preset program. This storage process may be to write the bitstream data to the internal memory of the FPGA chip, or to save it to an external storage device, depending on the design and implementation of the system. In order to ensure the reliability and stability of the upgrade process, this storage operation is usually performed after some verification and inspection. For example, the FPGA chip may verify the received bitstream data to ensure that there is no data loss or error. Once the verification passes, the FPGA chip will store the bitstream data in the specified location and prepare for subsequent upgrade operations.

[0044] For example, when you download a new software installation package on your computer, the computer will receive a download completion notification (similar to the end of bitstream mark) when the download is complete. Then, based on this notification, the computer will store the downloaded installation package file on the hard disk. After that, you can choose to install the software at any time without worrying about the downloaded file being lost or damaged.

[0045] Similarly, during the FPGA program upgrade process, the sending and receiving of the bitstream end flag, as well as the subsequent storage operation, are important links to ensure that the upgrade process proceeds smoothly and the FPGA chip can be correctly upgraded to the new version.

[0046] As an implementation method, it also includes: before performing an FPGA program upgrade, the SOC main control chip obtains the current FPGA program version number, and determines whether the current FPGA program version number is different from the preset FPGA program upgrade package file version number; if the current FPGA program version number is lower than the preset FPGA program upgrade package file version number, the FPGA program is upgraded.

[0047] Specifically, before upgrading the FPGA program, the SOC main control chip will first obtain the program version number running in the current FPGA chip. This version number is an identifier used to indicate the specific version of the current FPGA program. The way to obtain the version number may be by reading a specific register or memory location inside the FPGA chip. Next, the SOC main control chip will compare the obtained current FPGA program version number with the version number of the preset FPGA program upgrade package file. The preset version number is usually determined when the upgrade package file is generated, and it indicates the FPGA program version targeted by this upgrade package. If the comparison result shows that the current FPGA program version number is lower than the preset upgrade package file version number, it means that the current FPGA program needs to be updated. At this time, the SOC main control chip will trigger the upgrade process of the FPGA program and write the data in the upgrade package file into the FPGA chip to update the configuration of its internal logic. The importance of this step is that it can prevent unnecessary upgrade operations and avoid wasting resources and time. If the version number of the current FPGA program is the same as or higher than the version number of the upgrade package file, then there is no need to upgrade because the FPGA is already running the latest or more advanced version.

[0048] For example, just like the mobile phone operating system needs to be updated regularly, but before updating, the phone will first check the current system version. If the current version is already the latest, the phone will not update; if the current version is older, the phone will prompt to update. Similarly, during the FPGA program upgrade process, the SOC main control chip will first check the version number of the current FPGA program before deciding whether to upgrade.

[0049] Embodiment 2:

[0050] Based on Example 1, Figure 2 As shown, as another implementation of the present application, a novel method for remotely upgrading FPGA program of SOC chip is applied to SOC main control chip, including:

[0051] S100, sending a write bit stream enable command to the FPGA chip, and monitoring the command preparation state of the status indication port;

[0052] S200, when it is detected that the command preparation state is the first state, reading the erase completion flag returned by the FPGA chip, sending a preset FPGA program upgrade package file to the FPGA chip, and monitoring the write bit stream completion state of the status indication port;

[0053] S300, when it is monitored that the write bit stream completion state is the first state, read the FPGA write bit stream completion flag, send a read bit stream enable command to the FPGA chip, so that the FPGA chip performs verification based on the read bit stream enable command, and monitor the verification state of the status indication port;

[0054] S400, when it is detected that the verification state is the first state, reading the FPGA verification completion flag, sending a switch enable command to the FPGA chip, and monitoring the switch completion state of the status indication port;

[0055] S500: When the switch-on completion state is the first state, read the switch-on completion flag, and restart based on the sent hot start enable command to complete the FPGA program upgrade.

[0056] Specifically, first, the upgrade method starts with sending a write bitstream enable command to the FPGA chip. Bitstream is the data stream that configures the internal logic structure of the FPGA, and writing bitstream is the process of writing new configuration data into the FPGA. After sending this command, the system will continue to monitor the state of a specific status indication port on the FPGA, which is called the command preparation state. The purpose of this step is to confirm that the FPGA is ready to receive subsequent bitstream data. When the command preparation state is detected to reach the preset first state (usually meaning that the FPGA is ready), the system will read the erase completion flag returned by the FPGA chip. This flag indicates that the old configuration data inside the FPGA has been cleared, making room for receiving new data. Subsequently, the system will send a preset FPGA program upgrade package file to the FPGA, which contains new configuration data for defining the internal logic of the FPGA. While sending the upgrade package file, the system continues to monitor the write bitstream completion state of the status indication port to confirm that the data has been successfully written into the FPGA. Once the write bitstream completion state is detected to reach the first state, it means that the new bitstream data has been successfully loaded into the FPGA, and the system will read an FPGA write bitstream completion flag as confirmation. Next, to ensure that the newly loaded data is correct, the system sends a read bitstream enable command to the FPGA. This command triggers the FPGA to verify its internal configuration data, and the system tracks this process by monitoring the verification status of the status indicator port. When the verification status shows the first state, it means that the data verification inside the FPGA has passed, and the system then reads an FPGA verification completion flag. At this time, the system sends an open switch enable command to the FPGA, which is usually used to activate the new configuration of the FPGA so that it starts running according to the newly loaded logic. The system again monitors the open switch completion status of the status indicator port to ensure that the new configuration has been correctly activated. Finally, when the open switch completion status reaches the first state, the system reads an open switch completion flag as the last confirmation step of the entire upgrade process. At this time, the system restarts the FPGA or the entire system based on the hot start enable command sent. Hot start is to restart the device without turning off the power, so that the new FPGA configuration can take effect immediately, thus completing the upgrade process of the entire FPGA program.

[0057] To give an example of a practical application scenario, in a smart home system, the SOC main control chip is responsible for managing multiple components including the FPGA. When the FPGA function needs to be updated to support new smart home devices, the above upgrade method can be used to safely write the new bitstream data into the FPGA, and through the verification and restart steps, the smooth implementation of the new function can be ensured.

[0058] As an implementation method, if the FPGA program upgrade process is interrupted, when the SOC main control chip restarts, the FPGA chip loads the recovery bit stream, and the method further includes: after detecting the version number of the recovery bit stream, triggering the FPGA program upgrade again.

[0059] Specifically, the recovery bitstream is a preset configuration data, which usually contains the basic functions and necessary logic of the FPGA chip to ensure that the FPGA can be restored to a stable and workable state after the upgrade process is interrupted. The purpose of loading the recovery bitstream is to prevent the FPGA from being in an undefined or unstable state after the upgrade fails, thereby affecting the normal operation of the entire system. In this strategy, when the system detects that the recovery bitstream has been successfully loaded and recognizes its version number, it will trigger the upgrade process of the FPGA program again. This is because although the recovery bitstream can ensure the basic functions of the FPGA, it may not contain all the latest functions or optimizations. Therefore, by triggering the upgrade again, it can be ensured that the FPGA can eventually be loaded with the latest and complete configuration data.

[0060] For example, in an industrial automation system, the FPGA is responsible for controlling critical mechanical components. If a power outage occurs while the FPGA program is being upgraded, the upgrade process may be forced to abort. At this time, when the system is powered on again and started, the FPGA will automatically load the recovery bitstream to ensure that the mechanical components can continue to operate in basic mode. However, in order to restore to a complete and latest functional state, the system will automatically try to upgrade the FPGA program again after detecting the version number of the recovery bitstream.

[0061] This mechanism ensures that even if an unexpected interruption occurs during the upgrade process, the FPGA can recover to a stable state after the system restarts and has the opportunity to try to load the latest configuration data again. This strategy greatly improves the reliability and stability of FPGA program upgrades and reduces the risk of system downtime or loss of function due to upgrade failures.

[0062] As an implementation method, it also includes: after the FPGA program upgrade package file is sent, a bit stream end mark is sent to the FPGA chip, so that the FPGA chip stores the FPGA program upgrade package file according to the bit stream end mark.

[0063] Specifically, during the FPGA program upgrade process, it is crucial to ensure the integrity and correctness of the data. The sending of the bitstream end flag is to provide a clear signal at the end of the data transmission, telling the FPGA chip that it can safely store the received data in its internal memory. In this way, even if a power outage or other unexpected situation occurs later, the stored bitstream data will not be lost because they have been safely stored inside the FPGA chip.

[0064] Let's take a specific example to illustrate this process: suppose you are upgrading the program of an FPGA chip used for image processing. The upgrade package file contains new image processing algorithms and logic. In the process of sending this upgrade package file, the system will divide the data packet into multiple small parts according to the preset protocol and send them to the FPGA chip in sequence. When the last data packet is sent, the system will send a bit stream end flag to the FPGA chip. After receiving this flag, the FPGA chip will know that the currently transmitted bit stream data has ended, so it will combine all the received data packets to form a complete upgrade package file and store it in the internal memory.

[0065] In this way, we can ensure that the data transmission and storage are complete and correct during the FPGA program upgrade process. This greatly improves the reliability and stability of the upgrade and reduces the risk of upgrade failure due to data loss or damage. Therefore, in the FPGA program upgrade method, sending the bit stream end flag and triggering the FPGA chip to store data is a very important step.

[0066] As an implementation method, before performing an FPGA program upgrade, the method also includes: obtaining a current FPGA program version number, and determining whether the current FPGA program version number is different from a preset FPGA program upgrade package file version number; if the current FPGA program version number is lower than the preset FPGA program upgrade package file version number, performing an FPGA program upgrade.

[0067] Specifically, the process of obtaining the current FPGA program version number usually involves reading the version information stored inside the FPGA chip. This information may be preset when the FPGA chip leaves the factory, or it may be written during the last upgrade process. Once the current version number is obtained, the system will compare it with the preset upgrade package file version number. The purpose of the comparison is to determine whether an upgrade is necessary. If the version number of the current FPGA program is already higher than or equal to the version number of the upgrade package file, it means that the current FPGA program is already the latest or more advanced version, so there is no need to upgrade. On the contrary, if the version number of the current FPGA program is lower than the version number of the upgrade package file, the system will recognize that an upgrade is necessary and then start the upgrade process.

[0068] Let's take an example of a real application scenario to illustrate this process: In an intelligent transportation system, the FPGA chip is responsible for processing the control logic of the traffic light. If the system detects that the current FPGA program version number is 1.0, and the preset upgrade package file version number is 2.0, then the system will recognize that an upgrade is required. In this case, the system will send a write bitstream enable command to the FPGA chip, monitor the status indication port, send the upgrade package file, perform verification, and finally complete the upgrade according to the upgrade method described above.

[0069] Through this step, we can ensure that the upgrade is only performed when it is really necessary, thus avoiding unnecessary upgrade processes, saving system resources, and reducing potential risks caused by incorrect upgrades. Therefore, before upgrading the FPGA program, obtaining the current version number and comparing it with the upgrade package file version number is a very important and practical step.

[0070] Although the present invention is described herein with reference to the illustrative embodiments of the present invention, the above embodiments are only preferred embodiments of the present invention, and the embodiments of the present invention are not limited to the above embodiments. It should be understood that those skilled in the art can design many other modifications and embodiments, which will fall within the scope and spirit of the principles disclosed in this application.

Claims

1. A new system for remotely upgrading FPGA programs on SOC chips, characterized in that: It comprises a SOC main control chip and an FPGA chip, wherein the SOC main control chip comprises a plurality of universal ports; the SOC main control chip and the FPGA chip are communicatively connected via the plurality of universal ports, and the plurality of universal ports comprise a status indication port and a plurality of communication protocol ports; When performing an FPGA program upgrade, the SOC main control chip sends a write bitstream enable command to the FPGA chip through the multiple communication protocol ports, and monitors the command preparation state of the status indication port. When it is detected that the command preparation state is in the first state, the erase completion flag returned by the FPGA chip is read, a preset FPGA program upgrade package file is obtained, and the FPGA program upgrade package file is sent to the FPGA chip; the SOC main control chip monitors the write bitstream completion state of the status indication port. When it is detected that the write bitstream completion state is in the first state, the write bitstream completion flag returned by the FPGA chip is read, and the SOC main control chip The SOC main control chip sends a read bit stream enable command to the FPGA chip, so that the FPGA chip performs verification based on the read bit stream enable command; the SOC main control chip monitors the verification status of the status indication port, and when it is detected that the verification status is the first state, reads the verification completion flag returned by the FPGA chip, sends an open switch enable command to the FPGA chip, and monitors the open switch completion status of the status indication port, when the open switch completion status is the first state, reads the open switch completion flag returned by the FPGA chip, and sends a hot start enable command to restart the SOC main control chip to complete the FPGA program upgrade.

2. The system for remotely upgrading FPGA program of the new SOC chip according to claim 1 is characterized in that: If the FPGA program upgrade process is interrupted, when the system for remotely upgrading the FPGA program with the new SOC chip is restarted, the FPGA chip loads the recovery bit stream, and the SOC main control chip detects the version number of the recovery bit stream and triggers the FPGA program upgrade again.

3. The system according to claim 1, characterized in that When the FPGA program upgrade package file is sent completely, the SOC main control chip sends a bit stream end mark to the FPGA chip, and the FPGA chip stores the FPGA program upgrade package file according to the bit stream end mark.

4. The system for remotely upgrading FPGA program of the new SOC chip according to claim 1 is characterized in that: Also includes: Before performing an FPGA program upgrade, the SOC main control chip obtains the current FPGA program version number, and determines whether the current FPGA program version number is different from the preset FPGA program upgrade package file version number. If the current FPGA program version number is lower than the preset FPGA program upgrade package file version number, the FPGA program is upgraded.

5. A novel method for remotely upgrading FPGA program of SOC chip, characterized in that: Applied to SOC main control chips, including: Send a write bit stream enable command to the FPGA chip and monitor the command readiness status of the status indicator port; When it is detected that the command preparation state is the first state, read the erase completion flag returned by the FPGA chip, send a preset FPGA program upgrade package file to the FPGA chip, and monitor the write bit stream completion state of the status indication port; When it is monitored that the write bit stream completion state is the first state, read the FPGA write bit stream completion flag, send a read bit stream enable command to the FPGA chip, so that the FPGA chip performs verification based on the read bit stream enable command, and monitor the verification state of the status indication port; When it is detected that the verification state is the first state, the FPGA verification completion flag is read, a switch enable command is sent to the FPGA chip, and the switch completion state of the status indication port is monitored; When the switch-on completion state is the first state, the switch-on completion flag is read, and a restart is performed based on the sent hot start enable command to complete the FPGA program upgrade.

6. The method for remotely upgrading FPGA program of the novel SOC chip according to claim 5 is characterized in that: If the FPGA program upgrade process is interrupted, when the SOC main control chip restarts, the FPGA chip loads the recovery bit stream, and the method further includes: after detecting the version number of the recovery bit stream, triggering the FPGA program upgrade again.

7. The method for remotely upgrading FPGA program of the novel SOC chip according to claim 5 is characterized in that: Also includes: After the FPGA program upgrade package file is sent, a bit stream end mark is sent to the FPGA chip, so that the FPGA chip stores the FPGA program upgrade package file according to the bit stream end mark.

8. The method for remotely upgrading FPGA program of the novel SOC chip according to claim 5 is characterized in that: Before performing an FPGA program upgrade, the method further includes: obtaining a current FPGA program version number, and determining whether the current FPGA program version number is different from a preset FPGA program upgrade package file version number; if the current FPGA program version number is lower than the preset FPGA program upgrade package file version number, performing an FPGA program upgrade.

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