Quantitative transaction processor based on RISC-V instruction extension

Abstract

The invention discloses a quantitative transaction processor based on RISC-V instruction extension, and the processor comprises a quantitative transaction strategy dedicated instruction set which is used for achieving a quantitative transaction strategy and a technical index; and the quantitative transaction processor micro-architecture is used for realizing the special instruction set and realizing quantitative transaction. By adopting the technical scheme of the invention, the efficiency of calculating various transaction strategies and technical indexes can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a quantitative trading processor based on RISC-V instruction extension. Background Art

[0002] With the development of the financial field, a technical investment decision, namely quantitative trading, was born. Quantitative trading refers to replacing human subjective judgment with advanced mathematical models, using computer technology to select a variety of "high probability" events that can bring excess returns from a large amount of historical data to formulate strategies, greatly reducing the impact of investor sentiment fluctuations and avoiding irrational investment decisions when the market is extremely enthusiastic or pessimistic. Driven by computer systems, software technology and algorithm theory, quantitative trading and strategies have developed rapidly. However, timeliness is an important constraint in the financial field. With the increase in strategy complexity and the increase in computing efficiency requirements, the efficiency improvement brought by the optimization algorithm is far from enough, and dedicated processors are needed to further improve efficiency. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a quantitative trading processor based on RISC-V instruction extension, which can improve the efficiency of calculating various trading strategies and technical indicators.

[0004] To achieve the above object, the present invention adopts the following technical solution:

[0005] A quantitative trading processor based on RISC-V instruction extension, comprising:

[0006] A special instruction set for quantitative trading strategies, used to implement quantitative trading strategies and technical indicators;

[0007] The quantitative trading processor microarchitecture is used to implement the above-mentioned dedicated instruction set and realize quantitative trading.

[0008] Preferably, the quantitative trading strategy dedicated instruction set includes: control instructions, operation instructions and memory access instructions; wherein,

[0009] The control instructions include: synchronization instructions and loop instructions;

[0010] The operation instructions include: indicator operation instructions and vector operation instructions. The indicator operation instructions include: moving average instruction MA, average true fluctuation range instruction ATR, relative strength index instruction RSI, trend indicator instruction CCI, standard deviation indicator instruction STD, channel range indicator instruction Range and turtle technical indicator instruction Turtle. The vector operation instructions include: vector addition and subtraction instructions and vector logical operation instructions;

[0011] Memory access instructions include: vector access and transfer instructions.

[0012] Preferably, the quantitative trading processor micro-architecture includes: an instruction fetch unit, an execution unit and a strategy calculation unit; wherein,

[0013] The instruction fetch unit is used to pre-fetch, sort, distribute and schedule different types of instructions;

[0014] The execution unit is used to distribute different instruction types to corresponding computing units for execution, and is also used to maintain the data dependency of the instructions;

[0015] The strategy calculation unit is used to receive strategy instructions, perform internal operator configuration, and calculate various strategies and technical indicators.

[0016] Preferably, the policy calculation unit includes: a policy unit decoder, a vector load import module and a vector register, a policy unit write back module and an operator module; wherein,

[0017] The policy unit decoder is used to fully decode the custom instructions, obtain all instruction information, including the configuration information of the policy calculation, the address of the processed data, the type of operation and the read and write operation information, and pass it to the operator module;

[0018] Vector load import module and vector registers are used to store vector data and implement vector load import instructions;

[0019] The policy unit write-back module is used to save the calculation results of each instruction and write the results back to the correct location through configuration information;

[0020] The operator module is used to implement the calculation of trading strategies, technical indicators and vector operations, including the MA moving average operator, the ATR fluctuation range operator, the RSI relative strength operator, the CCI trend indicator operator, the STD standard deviation operator, the Range channel range indicator operator and the Turtle technical indicator operator.

[0021] Preferably, the address generator in the instruction acquisition unit is connected to the pre-branch prediction module and the bus control module to generate an instruction address. The bus control module is connected to the bus interface unit and the instruction memory, and is connected to the pre-decoding module and the value distribution module in the execution unit through a selector. The value distribution module is connected to the control instruction judgment module and the arithmetic operation unit, the long instruction unit, the load storage unit and the policy decoder in the policy calculation execution unit, which are respectively used to execute different types of instructions; the policy decoder is connected to the data interface and the operator module, and is used to assign policy instructions to different modules according to their types. The data interface module is connected to the vector register through the vector load import module, and is also connected to the policy unit write back module; the execution unit is connected to the write back register module together with the delivery module through the write back arbitration selector.

[0022] Preferably, the instruction execution process is as follows: the instruction will be pre-stored in the instruction memory, the address generator will generate the instruction address PC and give it to the bus control module, the bus control module will fetch the instruction corresponding to the PC and give it to the pre-decoding module and the value distribution module; if the instruction is a jump instruction, the jump address will be directly generated after pre-branch prediction; if it is not a jump instruction, the value distribution module will distribute it to the arithmetic operation unit, the long instruction unit, the load storage unit and the strategy calculation execution unit according to different instruction types; if it is a trading strategy instruction, the instruction will be fully decoded by the strategy unit decoder. The data information is input into the data interface module for obtaining the data required for the instruction through the external data memory, and the calculation information is input into the operator module. The internal operator is scheduled and configured according to the calculation information. The operator module also receives the calculation data input from the vector register, which is input into the write-back arbitration selector through the strategy write-back module, and is written back to the correct register position after being determined by the delivery module.

[0023] The present invention aims at accelerating the quantitative trading strategy, and uses a dedicated processor to achieve improvement in the calculation efficiency of the strategy compared with general-purpose processors and software acceleration. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0025] Figure 1 This is an overall micro-architecture diagram of a quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0026] Figure 2The hardware structure diagram of the control instructions in the quantitative trading processor based on RISC-V instruction extension according to the embodiment of the present invention;

[0027] Figure 3 This is a hardware structure diagram of the MA operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0028] Figure 4 The hardware structure diagram of the ATR operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0029] Figure 5 The hardware structure diagram of the RSI operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0030] Figure 6 The hardware structure diagram of the CCI operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0031] Figure 7 The hardware structure diagram of the STD operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0032] Figure 8 This is a hardware structure diagram of the Range operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0033] Fig. 9 This is a hardware structure diagram of the Turtle operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0034] Fig.10 The hardware structure diagram of the memory access instruction in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0035] Fig.11 Schematic diagram of instruction dependency problem. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Embodiment 1:

[0039] like Figure 1 As shown, an embodiment of the present invention further provides a quantitative trading processor based on RISC-V instruction extension, including:

[0040] A dedicated instruction set for quantitative trading strategies, used to implement quantitative trading strategies and technical indicators at the instruction level;

[0041] The quantitative trading processor microarchitecture is used to implement quantitative trading based on a dedicated instruction set.

[0042] As an implementation method of an embodiment of the present invention, a special instruction set for quantitative trading strategies is shown in Table 1, and is divided into three types according to the type of instruction: control instructions, operation instructions, and memory access instructions. The control instructions mainly include synchronization instructions and loop instructions, etc.; the operation instructions mainly include indicator operation instructions and vector operation instructions. The indicator operation instructions include moving average instructions MA, average true fluctuation range instructions ATR, relative strength index instructions RSI, trend indicator instructions CCI, standard deviation indicator instructions STD, channel range indicator instructions Range and turtle technical indicator instructions Turtle. The vector operation instructions are mainly basic vector operation instructions, that is, vector addition and subtraction instructions, and also include vector logical operation instructions, that is, vector AND, OR, and NOT instructions; the memory access instructions are mainly vector access and transfer instructions.

[0043] Table 1

[0044]

[0045] Furthermore, control instructions are divided into synchronization instructions and loop instructions. Synchronization instructions are used to solve the instruction dependency problem between different instruction queues, and loop instructions are used to improve the efficiency of repeated execution of a certain part of instructions. The structure of the control instruction is shown in Table 2. The opcode, funct3 and funct7 fields correspond to the operation code (0001011) and function code of the control instruction respectively. The rs1 field is the PC address of the source instruction, the rs2 field is the control enable signal, and the rd field is the PC address of the destination instruction. The hardware implementation of the control instruction is shown in Table 2. Figure 2 As shown, it consists of several AND gates, with the input being the instruction machine code and the output being the control instruction type. After the instruction is decoded, if it is a loop instruction, the PC of the instruction that needs to be looped is returned to the instruction fetch module. After decoding, if it is a synchronization instruction, the synchronization instruction is inserted between the PCs of the two target instructions.

[0046] Table 2

[0047]

[0048] Furthermore, operation instructions are the key part of the instruction set, which are divided into index operation instructions and vector operation instructions.

[0049] Furthermore, the indicator operation instructions are shown in Table 3, 1-7. The opcode and funct3 fields are the operation code (0101011) and function code of the indicator operation instruction, respectively. The rs1 and rs2 fields are the addresses of the closing price and the highest price data required by the indicator, respectively. The imm field is the time span or the lowest price. The rd field is the address where the indicator calculation result is stored. The hardware structure of the moving average indicator MA operator consists of an adder, a divider, an accumulator and a selector. The connection relationship is as follows: Figure 3 As shown in the figure, the hardware structure of the Average True Range indicator ATR operator consists of three subtractors, one adder, two absolute value calculators, one accumulator, one divider and two selectors. The connection relationship is as follows: Figure 4 As shown in the figure, the hardware structure of the relative strength index RSI operator consists of an adder, three subtractors, two accumulators, four dividers and a selector. The connection relationship is as follows: Figure 5 As shown in the figure, the hardware structure of the trend indicator CCI operator consists of three adders, two subtractors, one multiplier, four dividers, two accumulators, an absolute value calculator and a selector. The connection relationship is as follows: Figure 6 As shown in the figure, the hardware structure of the standard deviation indicator STD operator consists of two adders, a subtractor, a multiplier, two dividers, two accumulators, a square root and a selector. The connection relationship is as follows: Figure 7 As shown in the figure, the hardware structure of the channel range indicator Range operator consists of two subtractors, two maximum value finders, two minimum value finders and two selectors. The connection relationship is as follows: Figure 8 As shown in the figure, the hardware structure of the Turtle operator consists of a maximum value finder, a minimum value finder and two selectors. The connection relationship is as follows: Fig. 9 shown.

[0050] Table 3

[0051]

[0052] Furthermore, the vector operation instructions include vector basic operation instructions and vector logic operation instructions. The vector basic operation instructions include vector addition and subtraction instructions. The instruction structure is shown in Table 3, No. 8-9. The opcode and funct3 fields correspond to the operation code (1011011) and function code of the vector basic operation instruction, respectively. The rs1 and rs2 fields are the addresses of the input vectors, the imm field is the vector size, and the rd field is the address where the output vector is stored after calculation. The vector logic operation instructions are shown in Table 3, No. 10-11. The opcode and funct3 fields correspond to the operation code (1011011) and function code of the scalar arithmetic operation instruction, respectively. The rs1 and rs2 fields are the addresses of the input vectors, the imm field is the vector size, and the rd field is the address where the vector calculation result is stored.

[0053] Furthermore, the memory access instruction includes the vector access instruction. The instruction structure of the memory access instruction is shown in Table 4. The opcode and funct3 fields correspond to the operation code (1111011) and function code of the memory access instruction respectively. The rs1 and offset fields are the base address and offset address of the vector respectively. The imm field is the vector size. The rd field is the address of the destination register. The hardware implementation of the memory access instruction is as follows: Fig.10 As shown, it is used to realize data transfer between memory and register.

[0054] Table 4

[0055]

[0056] As an implementation method of an embodiment of the present invention, a quantitative trading processor micro-architecture includes: an instruction fetch unit, an execution unit and a strategy calculation unit.

[0057] Furthermore, the instruction fetch unit is used to implement the instruction queue design, and the instruction enters the corresponding instruction queue through the pre-decoder. In the microarchitecture, there are three types of instruction queues: control instruction queue, operation instruction queue, and memory access instruction queue. Different queues are issued out of order, and the same queues are executed in order. However, there may be a situation where the instructions between different queues have dependencies. For example, Fig.11 As shown in the figure, the execution of instruction C can only be carried out after the execution of instruction A is completed, and the execution of instruction E can only be carried out after the execution of instruction D is completed. At this time, it is necessary to introduce synchronization instructions to solve this problem. Synchronization instruction S is introduced between two dependent instructions. The synchronization instruction will start the execution of instruction C and instruction E after the execution of instruction A and instruction D is completed. Although this will lead to a decrease in instruction parallelism, it will reduce unnecessary data conflicts caused by instruction dependencies and greatly reduce the possibility of processor exceptions.

[0058] Furthermore, the execution unit receives instructions sent by the instruction fetch unit, first determines the instruction type, and distributes it to different processing units according to the instruction queue, including the arithmetic operation unit, the long instruction unit, and the load storage unit. It also includes write-back arbitration, which writes the results back to the corresponding memory or register according to different instructions. The execution unit is used to implement the basic instruction set of the processor.

[0059] Furthermore, the policy calculation unit includes a policy unit decoding module, a data interface, a vector register, a policy unit write-back module, and several execution operators. The policy unit decoding module receives the instruction of the operation type, and it first decodes it, including parsing the format of the instruction, identifying the operation type, extracting parameters, etc. After decoding, the policy unit decoding module will configure the function of the operator according to the instruction content. The operator here includes the arithmetic logic unit ALU and the hardware implementation module of each instruction mentioned in S1. The policy unit decoding module will configure the operator to perform a specific task, including setting the operator's operation mode, precision requirements, resource allocation, etc. After the configuration is completed, the policy unit decoding module will start the operator and put it into an enabled state, that is, ready to perform the calculation task. At the same time, the policy unit decoding module will also drive the data interface, which is the channel for the system to interact with external storage or memory. The data interface is responsible for reading the necessary input data from the memory or other data source to provide source data for the operator's operation. After the operation is completed, the operator writes the generated result to the corresponding memory location in the system through the data interface. The policy execution unit also includes a data storage part, including DMA, Cache, NRAM neuron memory, WRAM weight memory, and DRAM data memory. When the storage module receives the memory access instruction, it reads the neuron data from DRAM to NRAM and the weight data to WRAM. After receiving the read data enable of the operation module, it reads the neuron data from NRAM, pre-processes the neuron data, and then sends it to the MFU matrix operation unit. After receiving the instruction, the MFU receives the pre-processed neuron data from the VFU and reads the weight data from WRAM. After the operation, the result is written back to NRAM. If an indicator operation instruction is received, the required data is taken from DRAM and sent to the SFU to calculate the technical indicators and write the result back to DRAM.

[0060] The processor of the embodiment of the present invention realizes the calculation of technical indicators and trading strategies by designing seven quantitative trading technical indicator instructions and expanding the strategy operator execution unit. The processor uses the characteristic that different trading strategies have repeated mathematical operations, analyzes and disassembles trading strategies, designs instructions for repeated operations, and uses the scalability of the RISC-V architecture to realize the integration of technical indicator operators, effectively improving the calculation efficiency of trading strategies and technical indicators.

[0061] The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A quantitative trading processor based on RISC-V instruction extension, characterized in that: include: A special instruction set for quantitative trading strategies, used to implement quantitative trading strategies and technical indicators; The quantitative trading processor microarchitecture is used to implement the above-mentioned dedicated instruction set and realize quantitative trading.

2. The quantitative trading processor based on RISC-V instruction extension according to claim 1, characterized in that: The special instruction set for quantitative trading strategies includes: control instructions, operation instructions and memory access instructions; among them, The control instructions include: synchronization instructions and loop instructions; The operation instructions include: indicator operation instructions and vector operation instructions. The indicator operation instructions include: moving average instruction MA, average true fluctuation range instruction ATR, relative strength index instruction RSI, trend indicator instruction CCI, standard deviation indicator instruction STD, channel range indicator instruction Range and turtle technical indicator instruction Turtle. The vector operation instructions include: vector addition and subtraction instructions and vector logical operation instructions; Memory access instructions include: vector access and transfer instructions.

3. The quantitative trading processor based on RISC-V instruction extension according to claim 2 is characterized in that: The quantitative trading processor microarchitecture includes: instruction fetch unit, execution unit and strategy calculation unit; among them, The instruction fetch unit is used to pre-fetch, sort, distribute and schedule different types of instructions; The execution unit is used to distribute different instruction types to corresponding computing units for execution, and is also used to maintain the data dependency of the instructions; The strategy calculation unit is used to receive strategy instructions, perform internal operator configuration, and calculate various strategies and technical indicators.

4. The quantitative trading processor based on RISC-V instruction extension according to claim 3 is characterized in that: The policy calculation unit includes: a policy unit decoder, a vector load import module and a vector register, a policy unit write back module and an operator module; wherein, The policy unit decoder is used to fully decode the custom instructions, obtain all instruction information, including the configuration information of the policy calculation, the address of the processed data, the type of operation and the read and write operation information, and pass it to the operator module; Vector load import module and vector registers are used to store vector data and implement vector load import instructions; The policy unit write-back module is used to save the calculation results of each instruction and write the results back to the correct location through configuration information; The operator module is used to implement the calculation of trading strategies, technical indicators and vector operations, including the MA moving average operator, the ATR fluctuation range operator, the RSI relative strength operator, the CCI trend indicator operator, the STD standard deviation operator, the Range channel range indicator operator and the Turtle technical indicator operator.

5. The quantitative trading processor based on RISC-V instruction extension according to claim 4 is characterized in that: The address generator in the instruction acquisition unit is connected to the pre-branch prediction module and the bus control module to generate an instruction address. The bus control module is connected to the bus interface unit and the instruction memory, and is connected to the pre-decoding module and the value distribution module in the execution unit through a selector. The value distribution module is connected to the control instruction judgment module and the arithmetic operation unit, the long instruction unit, the load storage unit and the policy decoder in the policy calculation execution unit, which are respectively used to execute different types of instructions; the policy decoder is connected to the data interface and the operator module, and is used to allocate to different modules according to the type of policy instructions. The data interface module is connected to the vector register through the vector load import module, and is also connected to the policy unit write back module; the execution unit is connected to the write back register module together with the delivery module through the write back arbitration selector.

6. The quantitative trading processor based on RISC-V instruction extension according to claim 5 is characterized in that: The instruction execution process is as follows: the instruction will be stored in the instruction memory in advance, the address generator will generate the instruction address PC and give it to the bus control module, the bus control module will fetch the instruction corresponding to the PC and give it to the pre-decoding module and the value distribution module; if the instruction is a jump instruction, the jump address will be directly generated after pre-branch prediction; if it is not a jump instruction, the value distribution module will distribute it to the arithmetic operation unit, long instruction unit, load storage unit and strategy calculation execution unit according to different instruction types; if it is a trading strategy instruction, the instruction will be fully decoded by the strategy unit decoder. The data information is input into the data interface module to obtain the data required for the instruction through the external data memory, and the calculation information is input into the operator module to schedule and configure the internal operator according to the calculation information. The operator module also receives the calculation data input from the vector register, which is input into the write-back arbitration selector through the strategy write-back module and written back to the correct register position after being determined by the delivery module.

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