Multi-path laser coherent combination SPGD algorithm verification platform based on FPGA

Abstract

The invention belongs to the field of coherent synthesis, and discloses a multi-path laser coherent synthesis SPGD algorithm verification platform based on an FPGA, which is used for solving the problem that the SPGD algorithm is inaccurately simulated by MATALAB software. Software and hardware of a simulation system are combined, and the SPGD algorithm and related simulation modules are deployed in an FPGA board card; establishing a software simulation optical path in the computer; then the FPGA is connected with a computer through a gigabit Ethernet interface, and a data interaction channel is established; then an instruction is sent to the FPGA through the computer to set internal parameters of the SPGD algorithm, and SPGD algorithm simulation is started; then the FPGA sends the positive voltage value and the negative voltage value obtained through calculation by the SPGD algorithm to the computer, and after the computer software simulates the optical path to receive the positive voltage data and the negative voltage data, ADC data is obtained through calculation and sent to the FPGA; and finally, realizing simulation of the SPGD algorithm through circular data interaction between the FPGA and the computer. According to the method, simulation of the SPGD algorithm in a complex experiment environment can be simulated, the simulation accuracy is improved, and the experiment success rate is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of laser coherent synthesis, and in particular to a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA. Background Art

[0002] High-energy lasers are widely used in many fields such as industry, aerospace, and military. However, due to its own physical characteristics, the output power of a single laser is also limited. Through laser synthesis technology, coherent synthesis of multiple laser beams can effectively increase the output power of the laser.

[0003] The main methods of laser coherent synthesis include heterodyne method, multi-jitter method, particle swarm algorithm, genetic algorithm, stochastic parallel gradient descent algorithm (SPGD) algorithm, and machine learning. Among them, the SPGD algorithm was proposed by Vorontsov of the US Army Research Institute in 1997. Because the algorithm has a simple logical structure and is easy to implement, it has been widely improved and applied in laser coherent synthesis systems. In the process of improving these algorithms, the algorithms are mainly simulated based on MATALAB, but this simulation method cannot simulate the real experimental system well, resulting in a large error between the simulation results and the experimental results. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA. Compared with the traditional idealized simulation based on MATALB, the verification platform can simulate a simulation environment close to the experimental system and improve the accuracy of the simulation. When improving the SPGD algorithm, it is helpful to discover the shortcomings in the algorithm improvement and improve the success rate of further conversion of the simulation algorithm to the experiment.

[0005] The technical solution of the present invention to solve the above technical problems is:

[0006] A multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA includes the following steps:

[0007] (S1), before the Ethernet module sends data or after receiving data, the data passes through the cross-clock domain module, and the cross-clock domain module caches the data according to the different clock frequencies of SPGD;

[0008] (S2), after the instruction sent by the computer passes through the cross-clock domain module, the instruction parsing module parses the instruction according to the custom instruction set format to obtain the SPGD algorithm parameters;

[0009] (S3), the random sequence module generates multiple sets of pseudo-random sequences R through the linear feedback register n ;

[0010] (S4), the SPGD algorithm module obtains the disturbance voltage δu through calculation n , forward voltage dv + , negative voltage dv - , Update voltage U n ;

[0011] (S5), the DAC data conversion module in the DAC and ADC data conversion module converts the positive voltage and negative voltage values ​​calculated by the SPGD algorithm module into DAC data, and sends the DAC data to the computer through the Ethernet module;

[0012] (S6), the ADC data conversion module in the DAC and ADC data conversion module converts the ADC data received by the cross-clock domain module into a voltage value that can be calculated by the SPGD algorithm module;

[0013] (S7), after the computer simulates the optical path to obtain the positive voltage and negative voltage sent by the FPGA, the corresponding evaluation function J is obtained through calculation. + , J - ADC data and send the data to FPGA.

[0014] Preferably, in step (S1), the cross-clock domain module uses an asynchronous FIFO to establish a data buffer area, writes the data at the end with a slower clock frequency into the FIFO for caching, and determines whether the data is read from the end with a faster clock frequency through the data non-empty flag signal output by the FIFO.

[0015] Preferably, in step (S2), the instruction parsing module uses a custom instruction format to receive instructions sent by the computer, and the instructions are divided into three modes: SPGD startup mode, SPGD reset mode, and SPGD parameter adjustment mode.

[0016] Preferably, in step (S2), the SPGD startup mode is 1 byte in length, the SPGD reset instruction is 1 byte in length, and the SPGD parameter adjustment mode is 9 bytes.

[0017] Preferably, in step (S2), the 9 bytes of the SPGD parameter adjustment mode include: 1 byte mode instruction, 3 bytes update voltage coefficient instruction, 2 bytes disturbance voltage coefficient instruction, 2 bytes system delay instruction, and 1 byte ADC average sampling number instruction.

[0018] Preferably, in step (S4), the disturbance voltage δu n , forward voltage dv + , negative voltage dv - , Update voltage U nThe calculation steps are as follows:

[0019] (S4-1), if the pseudo-random sequence R n is equal to 1, then the disturbance voltage δu n = b, if the pseudo-random sequence R n is equal to 0, then the disturbance voltage δ n =-b, where b is the disturbance voltage coefficient;

[0020] (S4-2), forward voltage dv + =U n +δ n , negative voltage dv - =U n -δ n ;

[0021] (S4-3), update voltage U n+1 =U n +a*δu n *ΔJ, where the change in performance evaluation function ΔJ = J + -J - .

[0022] Preferably, in step (S5), the DAC conversion module in the DAC and ADC data conversion module converts the positive and negative voltage values ​​calculated by the SPGD algorithm module into input data corresponding to the DAC module according to the mapping relationship between input data and output voltage of different DAC modules.

[0023] Preferably, in step (S6), the ADC conversion module in the DAC and ADC data conversion module converts the ADC data input by the cross-clock domain module into a voltage value corresponding to the ADC module according to the mapping relationship between the input voltage and output data of different ADC modules.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the present invention combines FPGA hardware with a computer software simulation environment, realizes data interaction between FPGA and computer through Ethernet UDP protocol, FPGA runs the SPGD algorithm, and the software simulation environment in the computer simulates the experimental environment. The simulation system established by this method can simulate the experimental environment more accurately, thereby improving the accuracy of the simulation results.

[0026] 2. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the present invention can switch different modes by sending different instructions in the data interaction between FPGA and computer through Ethernet UDP protocol: SPGD startup mode, SPGD reset mode, SPGD parameter adjustment mode. The SPGD startup mode can start the SPGD algorithm for calculation, the SPGD reset mode can reset various parameters in the SPGD algorithm, and the SPGD parameter adjustment mode can change the update voltage coefficient, disturbance voltage coefficient, system delay, and ADC average sampling number. This is conducive to the adjustment of parameters in the SPGD algorithm and improves the convenience of the simulation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a structural block diagram of an FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the present invention.

[0028] Figure 2 The present invention is a flowchart of a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below in conjunction with embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0030] See also Figure 1 The relationship between the modules in the FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform of the present invention is shown in the figure. The Ethernet module serves as the communication interface between the FPGA and the computer; the cross-clock domain module establishes a data buffer area to ensure that data is not lost when the DAC and ADC data conversion modules, the instruction parsing module and the Ethernet module interact with each other; the instruction parsing module parses the instructions sent by the computer to provide calculation parameters for the SPGD algorithm; the DAC and ADC data conversion module converts the positive and negative voltages calculated by the SPGD into DAC data, and converts the ADC data sent by the computer into voltage values; the random sequence module and the SPGD algorithm module jointly implement the SPGD algorithm; the simulated optical path simulates the optical path operation on the computer side.

[0031] See also Figure 2 The present invention provides a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA, which includes the following steps:

[0032] (S1), the computer sends instructions to the FPGA to set the parameters in the SPGD algorithm; the FPGA uses the xc7z020clg400-2 chip of Xilinx;

[0033] (S2), the Ethernet module receives the instruction, passes through the cross-clock domain module, and then passes through the instruction parsing module to obtain the SPGD algorithm parameters, and sends the parsed parameters to the SPGD algorithm module;

[0034] (S3), the SPGD algorithm module sets internal parameters and starts the SPGD algorithm simulation;

[0035] (S4), SPGD algorithm module calculates the disturbance voltage δu n , forward voltage dv + , negative voltage dv - , Update voltage U n And send the positive voltage and negative voltage to the DAC and ADC data conversion module;

[0036] (S5), the DAC conversion module in the DAC and ADC data conversion module converts the positive voltage and the negative voltage into DAC data, and sends it to the Ethernet module through the cross-clock domain module;

[0037] (S6), the Ethernet module sends the DAC data to the analog optical path of the computer;

[0038] (S7), the simulated optical path on the computer side calculates the evaluation function J by receiving the positive voltage and negative voltage respectively. + , J - ADC data and send the ADC data to the FPGA Ethernet module;

[0039] (S8), the Ethernet module sends the received ADC data to the DAC and ADC data conversion module through the cross-clock domain module;

[0040] (S9), the ADC conversion module in the DAC and ADC data conversion module converts the ADC data into a voltage value and sends it to the SPGD algorithm module.

[0041] See also Figure 2 In step (S2), the Ethernet module, the cross-clock domain module, and the instruction parsing module are constructed as follows:

[0042] (S2-1) Ethernet module, using UDP protocol to exchange data with the computer;

[0043] (S2-2) A cross-clock domain module uses an asynchronous FIFO to establish a data buffer area, writes the data at the end with a slower clock frequency into the FIFO for buffering, and determines whether the data is read out from the end with a faster clock frequency through a non-empty flag signal output by the FIFO;

[0044] (S2-3) The instruction parsing module uses a custom instruction format to receive instructions sent by the computer. The instructions are divided into three modes: SPGD startup mode, SPGD reset mode, and SPGD parameter adjustment mode. The SPGD startup mode is 1 byte long (the instruction is AF); the SPGD reset instruction is 1 byte long (the instruction is A0); the SPGD parameter adjustment mode is 9 bytes, and the 9 bytes of the SPGD parameter adjustment mode include: 1 byte mode instruction (the instruction is: AA), 3 bytes update voltage coefficient instruction, 2 bytes perturb voltage coefficient instruction, 2 bytes system delay instruction, 1 byte ADC average sampling number instruction, the voltage coefficient instruction, the perturbation voltage coefficient instruction, the system delay instruction, and the ADC average sampling number instruction all use the fixed-point number Q10 format.

[0045] See also Figure 2 In step (S4), the SPGD algorithm module is constructed as follows:

[0046] (S4-1), random sequence module, generates random sequence R through linear shift feedback register n , and send the generated random sequence to the SPGD algorithm module;

[0047] (S4-2), if the pseudo-random sequence R n is equal to 1, then the disturbance voltage δu n = b, if the pseudo-random sequence R n is equal to 0, then the disturbance voltage δ n =-b, where b is the disturbance voltage coefficient;

[0048] (S4-3), forward voltage dv + =U n +δ n , negative voltage dv - =U n -δ n ;

[0049] (S4-4), update voltage U n+1 =U n +a*δu n *ΔJ, where the change in performance evaluation function ΔJ = J + -J - .

[0050] See also Figure 2In step (S5), the construction of the DAC conversion module in the DAC and ADC data conversion module includes the following steps: the length of the DAC module input data is set to 16 bits, the output voltage range is set to 0-5V, and the DAC module input data and output voltage are linearly mapped; the DAC conversion module converts the positive and negative voltage values ​​calculated by the SPGD algorithm module into the input data corresponding to the DAC module.

[0051] See also Figure 2 In step (S9), the construction of the ADC conversion module in the DAC and ADC data conversion module includes the following steps: the input voltage range of the ADC module is set to 0-5V, the length of the output data is set to 12 bits, and the input voltage and output data of the ADC module are linearly mapped; the ADC conversion module converts the input ADC data into a corresponding voltage value.

Claims

1. A multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA, characterized in that: The simulation system includes , the following steps: (S1), before the Ethernet module sends data or after receiving data, the data passes through the cross-clock domain module, and the cross-clock domain module caches the data according to the different clock frequencies of SPGD; (S2), after the instruction sent by the computer passes through the cross-clock domain module, the instruction parsing module parses the instruction according to the custom instruction set format to obtain the SPGD algorithm parameters; (S3), the random sequence module generates multiple sets of pseudo-random sequences R through the linear feedback register n ; (S4), the SPGD algorithm module obtains the disturbance voltage δu through calculation n , forward voltage dv + , negative voltage dv - , Update voltage U n ; (S5), the DAC data conversion module in the DAC and ADC data conversion module converts the positive voltage and negative voltage values ​​calculated by the SPGD algorithm module into DAC data, and sends the DAC data to the computer through the Ethernet module; (S6), the ADC data conversion module in the DAC and ADC data conversion module converts the ADC data received by the cross-clock domain module into a voltage value that can be calculated by the SPGD algorithm module; (S7), after the computer simulates the optical path to obtain the positive voltage and negative voltage sent by the FPGA, the corresponding evaluation function J is obtained through calculation. + , J - ADC data and send the data to FPGA.

2. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform according to claim 1, characterized in that: In step (S1), the cross-clock domain module uses an asynchronous FIFO to establish a data buffer area, writes the data at the end with a slower clock frequency into the FIFO for buffering, and determines whether the data is read out from the end with a faster clock frequency through the data non-empty flag signal output by the FIFO.

3. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform according to claim 1, characterized in that: In step (S2), the instruction parsing module uses a custom instruction format to receive instructions sent by the computer. The instructions are divided into three modes: SPGD startup mode, SPGD reset mode, and SPGD parameter adjustment mode.

4. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform according to claim 3 is characterized in that: The SPGD startup mode is 1 byte in length, the SPGD reset instruction is 1 byte in length, and the SPGD parameter adjustment mode is 9 bytes.

5. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform according to claim 4, characterized in that: The 9 bytes of the SPGD parameter adjustment mode include: 1 byte mode instruction, 3 bytes update voltage coefficient instruction, 2 bytes disturbance voltage coefficient instruction, 2 bytes system delay instruction, and 1 byte ADC average sampling number instruction.

6. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform according to claim 1, characterized in that: In step (S4), the disturbance voltage δu n , forward voltage dv + , negative voltage dv - , Update voltage U n The calculation steps are as follows: (S4-1), if the pseudo-random sequence R n is equal to 1, then the disturbance voltage δu n = b, if the pseudo-random sequence R n is equal to 0, then the disturbance voltage δ n =-b, where b is the disturbance voltage coefficient; (S4-2), forward voltage dv + =U n +δ n , negative voltage dv - =U n -δ n ; (S4-3), update voltage U n+1 =U n +a*δu n *ΔJ, where the change in performance evaluation function ΔJ=J + -J - .

7. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform according to claim 1, characterized in that: In step (S5), the DAC conversion module in the DAC and ADC data conversion module converts the positive and negative voltage values ​​calculated by the SPGD algorithm module into input data corresponding to the DAC module according to the mapping relationship between the input data and the output voltage of different DAC modules.

8. The FPGA-based multi-channel laser coherent synthesis SPGD algorithm verification platform according to claim 1, characterized in that: In step (S6), the ADC conversion module in the DAC and ADC data conversion module converts the ADC data input by the cross-clock domain module into a voltage value corresponding to the ADC module according to the mapping relationship between the input voltage and output data of different ADC modules.

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