Method and device for optimizing target time sequence path, storage medium and electronic equipment
By combining functional modules in the timing violation path and optimizing the timing path, the cost problem in the existing technology is solved, low-cost timing convergence is achieved, and the accuracy and reliability of integrated circuit design is improved.
Patent Information
- Application Number
- CN202411345722.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-01-03
AI Technical Summary
The prior art is costly when optimizing timing paths, resulting in difficulty in timing convergence and increasing device area and power consumption.
By determining the intermediate nodes in the timing violation path and performing functional module merging operations, the timing path is optimized, logical sharing and logic optimization are realized, and costs are reduced.
The time series paths are optimized at low cost, and the effect of timing convergence is achieved, resource waste is reduced, and the accuracy and reliability of integrated circuit design are improved.
Smart Images
Figure CN119249992A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present application relate to the computer field, and more specifically, to a method and device for optimizing a target timing path, a storage medium, and an electronic device. Background Art
[0002] The current physical design of integrated circuits mainly includes two design processes, flattened physical design and hierarchical physical design. Among them, the design idea of hierarchical physical design is top-down, and it is divided into different functional modules according to the functions to be realized by the entire device. Therefore, each functional module needs to be fully and accurately estimated in the early stage of design, otherwise it may lead to the failure of timing convergence of the timing path in the back-end synthesis process. Most related technologies achieve timing convergence by adding or replacing electronic components, but there is a problem of increasing device area and power consumption. Summary of the invention
[0003] Embodiments of the present application provide a method and apparatus, a storage medium, and an electronic device for optimizing a target timing path, so as to at least solve the problem of high cost of optimizing the timing path in the related art.
[0004] According to an embodiment of the present application, a method for optimizing a target timing path is provided, which is applied to a system on chip, wherein the system on chip includes multiple system components, and the method includes: determining a timing violation path between a first system component and a second system component from multiple timing paths between the multiple system components, wherein each of the timing paths includes multiple timing nodes, one timing node corresponds to a functional module of the system component, the delay of the timing violation path is greater than a preset delay, and the starting timing node of the timing violation path is the functional module of the first system component, and the ending timing node is The functional module of the second system component, the first system component and the second system component are components among the multiple system components; determining the timing node closest to the start timing node among the multiple intermediate timing nodes included in the timing violation path to obtain the target intermediate timing node; determining the functional module of the target timing node based on the merge operation performed on the functional module of the target intermediate timing node and the functional module of the start timing node; determining the timing path between the target timing node and the end timing node as the target timing path between the first system component and the second system component.
[0005] In an exemplary embodiment, after determining the timing path between the target timing node and the end timing node as the target timing path between the first system component and the second system component, the method further includes: calculating the total path delay of the target timing path based on the time when the first preset signal is transmitted from the target timing node to the end timing node; and determining the target timing path as a target timing violation path when the total path delay of the target timing path is greater than the preset delay.
[0006] In an exemplary embodiment, when the total path delay of the above-mentioned target timing path is greater than the above-mentioned preset delay, after the above-mentioned target timing path is determined as a target timing violation path, the above-mentioned method also includes: determining the timing node closest to the target start timing node among the multiple target intermediate timing nodes included in the above-mentioned target timing violation path, and obtaining a first target intermediate timing node; determining the functional module of the first target timing node based on a merge operation performed on the functional module of the above-mentioned first target intermediate timing node and the functional module of the above-mentioned target start timing node; determining the timing path between the above-mentioned first target timing node and the target end timing node as the first target timing path between the above-mentioned first system component and the above-mentioned second system component, wherein the delay of the above-mentioned first target timing path is less than the above-mentioned preset delay.
[0007] In an exemplary embodiment, determining a timing violation path between a first system component and a second system component from a plurality of timing paths between the plurality of the above-mentioned system components includes: based on a transmission direction of a second preset signal, identifying a plurality of timing paths between the plurality of the above-mentioned system components, wherein the transmission direction of the second preset signal includes at least one of the following: a first input system component transmits to a first output system component, a first input system component transmits to a first trigger system component, a first trigger system component transmits to a second trigger system component, and a first trigger system component transmits to a first output system component, wherein the first input system component, the first output system component, the first trigger system component and the second trigger system are all components among the plurality of the above-mentioned system components; calculating a total path delay of each of the above-mentioned timing paths based on a time when the second preset signal is transmitted from a starting system component to an ending system component, wherein the starting system component includes the first input system component and the first trigger system component, and the ending system component includes the second trigger system component and the first output system component; determining a timing path whose total path delay is greater than the preset delay as the above-mentioned timing violation path.
[0008] In an exemplary embodiment, before determining the timing node closest to the above-mentioned starting timing node among the multiple intermediate timing nodes included in the above-mentioned timing violation path and obtaining the target intermediate timing node, the above-mentioned method also includes: traversing the N intermediate timing nodes connected to the above-mentioned starting timing node in the above-mentioned timing violation path, and storing the N above-mentioned intermediate timing nodes visited into an access queue, wherein the above-mentioned access queue is used to store the above-mentioned intermediate timing nodes visited, the N above-mentioned intermediate timing nodes are timing nodes stored in the above-mentioned access queue in an access order, and the above-mentioned N is a natural number greater than or equal to 1.
[0009] In an exemplary embodiment, determining the timing node closest to the starting timing node among the multiple intermediate timing nodes included in the timing violation path to obtain the target intermediate timing node includes: obtaining the coordinates of the starting timing node and the coordinates of the multiple intermediate timing nodes; respectively calculating the Manhattan distance between each of the intermediate timing nodes and the starting timing node to obtain multiple Manhattan distances, wherein the Manhattan distance D(i, j)=|x i -x j |+|y i -y j |, the above (x i ,y i ) is the coordinate of the starting time sequence node, and the above (x j ,y j ) are the coordinates of the intermediate timing node; the intermediate timing node closest to the starting timing node is determined as the target intermediate timing node.
[0010] In an exemplary embodiment, determining the functional module of the target timing node based on a merge operation performed on the functional module of the target intermediate timing node and the functional module of the starting timing node includes: obtaining multiple first interface information of the functional module of the target intermediate timing node and multiple second interface information of the functional module of the starting timing node, wherein the first interface information includes the input and output functions of the first interface of the functional module of the target intermediate timing node, and the second interface information includes the input and output functions of the second interface of the functional module of the starting timing node; based on the first interface information and the second interface information, merging the first target interface and the second target interface to determine the target interface, wherein the first target interface has the same input and output functions as the second target interface, and the first target interface is an interface among the multiple first interfaces, and the second target interface is an interface among the multiple second interfaces; based on the target interface, merging the first target system component and the second target system component to determine the functional module of the target timing node, wherein the first target system component is a component in the functional module of the target intermediate timing node, and the second target system component is a component in the functional module of the starting timing node.
[0011] According to another embodiment of the present application, there is provided an apparatus for optimizing a target timing path, which is applied to a system on chip, wherein the system on chip includes a plurality of system components, and the apparatus includes: a first determining module, which is used to determine a timing violation path between a first system component and a second system component from a plurality of timing paths between the plurality of the system components, wherein each of the timing paths includes a plurality of timing nodes, one of the timing nodes corresponds to a functional module of the system component, a delay of the timing violation path is greater than a preset delay, and a starting timing node of the timing violation path is a functional module of the first system component, and an ending timing node is a functional module of the second system component. a functional module of a component, wherein the first system component and the second system component are both components among the plurality of system components; a second determining module, for determining a timing node closest to the start timing node among the plurality of intermediate timing nodes included in the timing violation path, to obtain a target intermediate timing node; a third determining module, for determining the target timing node based on a merge operation performed on the functional module of the target intermediate timing node and the functional module of the start timing node; and a fourth determining module, for determining the timing path between the target timing node and the end timing node as the target timing path between the first system component and the second system component.
[0012] In an exemplary embodiment, the above-mentioned device also includes: a first calculation module, which is used to determine the timing path between the above-mentioned target timing node and the above-mentioned end timing node as the target timing path between the above-mentioned first system component and the above-mentioned second system component, and then calculate the total path delay of the above-mentioned target timing path based on the time when the first preset signal is transmitted from the above-mentioned target timing node to the above-mentioned end timing node; a fifth determination module, which is used to determine the above-mentioned target timing path as a target timing violation path when the total path delay of the above-mentioned target timing path is greater than the above-mentioned preset delay.
[0013] In an exemplary embodiment, the above-mentioned device also includes: a sixth determination module, which is used to determine the target timing path as a target timing violation path after the total path delay of the above-mentioned target timing path is greater than the above-mentioned preset delay, and then determine the timing node closest to the target start timing node among the multiple target intermediate timing nodes included in the above-mentioned target timing violation path to obtain a first target intermediate timing node; a seventh determination module, which is used to determine the functional module of the first target timing node based on a merge operation performed on the functional module of the above-mentioned first target intermediate timing node and the functional module of the above-mentioned target start timing node; and an eighth determination module, which is used to determine the timing path between the above-mentioned first target timing node and the target end timing node as the first target timing path between the above-mentioned first system component and the above-mentioned second system component, wherein the delay of the above-mentioned first target timing path is less than the above-mentioned preset delay.
[0014] In an exemplary embodiment, the first determination module includes: a first identification submodule, used to identify multiple timing paths between the multiple system components based on the transmission direction of the second preset signal, wherein the transmission direction of the second preset signal includes at least one of the following: the first input system component transmits to the first output system component, the first input system component transmits to the first trigger system component, the first trigger system component transmits to the second trigger system component, and the first trigger system component transmits to the first output system component, and the first input system component, the first output system component, the first trigger system component and the second trigger system are all components among the multiple system components; a first calculation submodule, used to calculate the total path delay of each of the timing paths based on the time when the second preset signal is transmitted from the starting system component to the ending system component, wherein the starting system component includes the first input system component and the first trigger system component, and the ending system component includes the second trigger system component and the first output system component; a first determination submodule, used to determine the timing path whose total path delay is greater than the preset delay as the timing violation path.
[0015] In an exemplary embodiment, the above-mentioned device also includes: a first traversal module, which is used to determine the timing node closest to the above-mentioned starting timing node among the multiple intermediate timing nodes included in the above-mentioned timing violation path, and before obtaining the target intermediate timing node, traverse the N intermediate timing nodes connected to the above-mentioned starting timing node in the above-mentioned timing violation path, and store the N above-mentioned intermediate timing nodes visited in an access queue, wherein the above-mentioned access queue is used to store the above-mentioned intermediate timing nodes visited, and the N above-mentioned intermediate timing nodes are timing nodes stored in the above-mentioned access queue in an access order, and the above-mentioned N is a natural number greater than or equal to 1.
[0016] In an exemplary embodiment, the second determination module includes: a first acquisition submodule, used to acquire the coordinates of the starting timing node and the coordinates of the plurality of intermediate timing nodes; a second calculation submodule, used to respectively calculate the Manhattan distance between each of the intermediate timing nodes and the starting timing node to obtain a plurality of Manhattan distances, wherein the Manhattan distance D(i, j)=|x i -x j |+|y i -y j |, the above (x i ,y i ) is the coordinate of the starting time sequence node, and the above (x j ,y j ) is the coordinate of the above-mentioned intermediate timing node; the second determination submodule is used to determine the intermediate timing node closest to the above-mentioned starting timing node as the above-mentioned target intermediate timing node.
[0017] In an exemplary embodiment, the third determination module includes: a second acquisition submodule, used to acquire multiple first interface information of the functional module of the target intermediate timing node and multiple second interface information of the functional module of the starting timing node, wherein the first interface information includes the input and output functions of the first interface of the functional module of the target intermediate timing node, and the second interface information includes the input and output functions of the second interface of the functional module of the starting timing node; a third determination submodule, used to merge the first target interface and the second target interface based on the first interface information and the second interface information to determine the target interface, wherein the first target interface has the same input and output functions as the second target interface, and the first target interface is an interface among the multiple first interfaces, and the second target interface is an interface among the multiple second interfaces; a first merging submodule, used to merge the first target system component and the second target system component based on the target interface to determine the functional module of the target timing node, wherein the first target system component is a component in the functional module of the target intermediate timing node, and the second target system component is a component in the functional module of the starting timing node.
[0018] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when running.
[0019] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
[0020] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.
[0021] Through the present application, the timing node closest to the starting timing node among the multiple intermediate timing nodes included in the timing violation path is determined to obtain the target intermediate timing node; the functional module of the target timing node is determined based on the merge operation performed on the functional module of the target intermediate timing node and the functional module of the starting timing node; the timing path between the target timing node and the ending timing node is determined as the target timing path between the first system component and the second system component. Since the present application determines the timing node closest to the starting timing node in the timing violation path, and merges the functional module of the timing node closest to the starting timing node with the functional module of the starting timing node, the merged module can perform logic sharing and logic optimization, therefore, it can solve the problem of high cost of optimizing the timing path in the related art, realize low-cost optimization of the timing path, and achieve the effect of timing convergence. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a hardware structure block diagram of a server device of a method for optimizing a target timing path according to an embodiment of the present application;
[0023] Figure 2 is a flow chart of a method for optimizing a target timing path according to an embodiment of the present application;
[0024] Figure 3 A method for optimizing a target timing path according to a specific embodiment of the present application is shown in FIG. Figure 1 ;
[0025] Figure 4 A method for optimizing a target timing path according to a specific embodiment of the present application is shown in FIG. Figure 2 ;
[0026] Figure 5 is a flow chart of a method for optimizing a target timing path according to a specific embodiment of the present application;
[0027] Figure 6 It is a structural block diagram of a device for optimizing a target timing path according to an embodiment of the present application. DETAILED DESCRIPTION
[0028] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0030] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 1 is a hardware structure block diagram of a server device of a method for optimizing a target timing path according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.
[0031] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as a computer program corresponding to a method for optimizing a target timing path in an embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to a server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0032] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.
[0033] In this embodiment, a method for optimizing a target timing path is provided, which is applied to a system on chip, wherein the system on chip includes multiple system components. Figure 2 is a flow chart of a method for optimizing a target timing path according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps:
[0034] Step S202, determining a timing violation path between a first system component and a second system component from a plurality of timing paths between a plurality of system components, wherein each timing path includes a plurality of timing nodes, one timing node corresponds to a functional module of a system component, a delay of the timing violation path is greater than a preset delay, and a starting timing node of the timing violation path is a functional module of the first system component, an ending timing node is a functional module of the second system component, and the first system component and the second system component are both components among the plurality of system components;
[0035] Optionally, the system on chip is an integrated circuit that integrates multiple functional modules, including a processor core, memory, input and output interfaces, and other functional modules.
[0036] Optionally, the system components include but are not limited to triggers, logic gates, transmission gates, transistors, resistors, and capacitors. The functional modules of the system components include but are not limited to: processor, memory controller, input / output controller, power management module, clock management module, interrupt controller, communication interface module, display controller, audio processor, security module, sensor interface, and control logic.
[0037] Optionally, the timing path is a path for signal transmission in an integrated circuit.
[0038] Step S204, determining a timing node closest to the start timing node among multiple intermediate timing nodes included in the timing violation path, and obtaining a target intermediate timing node;
[0039] Step S206, determining the functional module of the target timing node based on the merging operation performed on the functional module of the target intermediate timing node and the functional module of the starting timing node;
[0040] Step S208: determine the timing path between the target timing node and the end timing node as the target timing path between the first system component and the second system component.
[0041] Optionally, assume that an integrated circuit includes system components such as trigger A, logic gate L1, logic gate L2, logic gate L3, trigger B, etc., and the functional modules are respectively an input controller, a clock management module, a memory controller, a power management module, and an output controller, wherein trigger A is a first system component, trigger B is a second system component, and there are three timing paths from trigger A to trigger B: trigger A (signal source)-logic gate L1-trigger B (signal end point), trigger A (signal source)-logic gate L2-trigger B (signal end point), trigger A (signal source)-logic gate L3 -When the timing path of trigger B (signal end point), the logic gate assumes that the target timing violation path is trigger A (signal source) - logic gate L1 - logic gate L2 - logic gate L3, trigger B (signal end point), where the timing violation path is: trigger A (signal source) - logic gate L1 - trigger B (signal end point), the intermediate timing node is logic gate L1, and the timing node closest to the starting timing node trigger A, that is, the target intermediate timing node is logic gate L1. After merging trigger A and logic gate L1, the target timing path is obtained: trigger A (signal source) logic gate L1 - trigger B (signal end point).
[0042] Through the above steps, the timing node closest to the starting timing node among the multiple intermediate timing nodes included in the timing violation path is determined to obtain the target intermediate timing node; the functional module of the target timing node is determined based on the merge operation performed on the functional module of the target intermediate timing node and the functional module of the starting timing node; the timing path between the target timing node and the ending timing node is determined as the target timing path between the first system component and the second system component. Since the present application determines the timing node closest to the starting timing node in the timing violation path, and merges the functional module of the timing node closest to the starting timing node with the functional module of the starting timing node, the merged module can perform logic sharing and logic optimization, therefore, it can solve the problem of high cost of optimizing the timing path in the related art, realize low-cost optimization of the timing path, and achieve the effect of timing convergence.
[0043] In an exemplary embodiment, after determining the timing path between the target timing node and the end timing node as the target timing path between the first system component and the second system component, the method further includes: calculating the total path delay of the target timing path based on the time when the first preset signal is transmitted from the target timing node to the end timing node; and determining the target timing path as a target timing violation path when the total path delay of the target timing path is greater than the preset delay.
[0044] Optionally, to determine whether a timing path meets the timing requirements, it is to look at the total path delay on the timing path. The total path delay includes but is not limited to the logic delay and propagation delay during the signal transmission process. If the total path delay is within the specified range, then this timing path meets the timing requirements, otherwise it is a timing violation path, where the total path delay is cross-module and can be measured in units of logic cones. Evaluating the total path delay in units of logic cones can more accurately determine whether the signal can meet the timing requirements during transmission. For example, suppose there is a simple timing path from the output of trigger A to the input of trigger B. This timing path includes the following parts: 1ns of output delay from the data input of trigger A to the arrival of the clock signal of trigger A, 2ns of logic delay of the signal through the logic gate or combinational logic, 3ns of propagation delay of the signal on the interconnect, and 1ns of input delay from the arrival of the input of trigger B to the arrival of the clock signal of trigger B. The total path delay is 1ns+2ns+3ns+1ns=7ns. If the clock cycle of trigger B is 1Ons, and the set time margin of the clock cycle is 2ns, then trigger B needs to receive the signal within 8ns. Since the total path delay is 7ns, which is less than 8ns, this timing path meets the timing requirements. Suppose there is a digital circuit that contains a trigger driven by a clock signal. The output of the trigger drives a series of logic gates and finally reaches the input of another trigger. The following are the parts in the logic cone: trigger A (signal source), logic gate L1, logic gate L2, logic gate L3, trigger B (signal destination), where the clock cycle of trigger A is 10ns, trigger B needs to receive the signal within 8ns to meet the set time margin requirements, the output delay of trigger A is 2ns, the delay of logic gate L1 is 3ns, the delay of logic gate L2 is 4ns, and the delay of logic gate L3 is 5ns. The total delay is 2ns+3ns+4ns+5ns=12ns, which exceeds the set time margin of trigger B, so this timing path does not meet the timing requirements. This embodiment can more accurately identify and evaluate timing risks by determining the total path delay of the target timing path, thereby improving the accuracy and reliability of integrated circuit design.
[0045] In an exemplary embodiment, when the total path delay of the above-mentioned target timing path is greater than the above-mentioned preset delay, after the above-mentioned target timing path is determined as a target timing violation path, the above-mentioned method also includes: determining the timing node closest to the target start timing node among the multiple target intermediate timing nodes included in the above-mentioned target timing violation path, and obtaining a first target intermediate timing node; determining the functional module of the first target timing node based on a merge operation performed on the functional module of the above-mentioned first target intermediate timing node and the functional module of the above-mentioned target start timing node; determining the timing path between the above-mentioned first target timing node and the target end timing node as the first target timing path between the above-mentioned first system component and the above-mentioned second system component, wherein the delay of the above-mentioned first target timing path is less than the above-mentioned preset delay.
[0046] Optionally, assuming that the target timing violation path is trigger A (signal source)-logic gate L1-logic gate L2-logic gate L3, trigger B (signal end point), the timing node closest to the target starting timing node trigger A is logic gate L1, the target starting timing node trigger A and the first target intermediate timing node logic gate L1 are merged to obtain the functional module of the first target timing node, and the new timing path is trigger A logic gate L1 (signal source)-logic gate L2-logic gate L3-trigger B (signal end point). If the delay of the new timing path is greater than the above-mentioned preset delay, assuming that the timing node closest to the target starting timing node trigger A logic gate L1 is logic gate L2, the target starting timing node trigger A logic gate L1 and the first target intermediate timing node logic gate L2 are merged to obtain the functional module of the first target timing node, and the new timing path is trigger A logic gate L1 logic gate L2 (signal source)-logic gate L3-trigger B (signal end point). If the delay of the timing path is less than the preset delay, the path is the first target timing path between trigger A and trigger B, otherwise the above operation is repeated: determine the timing node closest to the target starting timing node, merge the functional modules of the two timing nodes to determine a new timing path, until the delay of the timing path is less than the preset delay to obtain the first target timing path. This embodiment realizes low-cost optimization of the timing path and achieves the purpose of timing convergence by merging the functional modules of the timing node closest to the starting timing node in the timing violation path with the functional modules of the starting timing node.
[0047] In an exemplary embodiment, determining a timing violation path between a first system component and a second system component from a plurality of timing paths between the plurality of the above-mentioned system components includes: based on a transmission direction of a second preset signal, identifying a plurality of timing paths between the plurality of the above-mentioned system components, wherein the transmission direction of the second preset signal includes at least one of the following: a first input system component transmits to a first output system component, a first input system component transmits to a first trigger system component, a first trigger system component transmits to a second trigger system component, and a first trigger system component transmits to a first output system component, wherein the first input system component, the first output system component, the first trigger system component and the second trigger system are all components among the plurality of the above-mentioned system components; calculating a total path delay of each of the above-mentioned timing paths based on a time when the second preset signal is transmitted from a starting system component to an ending system component, wherein the starting system component includes the first input system component and the first trigger system component, and the ending system component includes the second trigger system component and the first output system component; determining a timing path whose total path delay is greater than the preset delay as the above-mentioned timing violation path.
[0048] Optionally, when performing timing analysis on an integrated circuit, the following four types of timing paths are included according to the transmission direction of the signal: input to trigger, trigger to trigger, trigger to output, and input to output. Timing path 1 Input buffer A-trigger A: Assuming that the time for input buffer A to send a signal is 10ns and the time for trigger A to receive a signal is 13ns, the total path delay of the timing path is 3ns < the preset delay of 4ns, and timing path 1 is not a timing violation path. Timing path 2 Trigger A to Trigger B: Assuming that the time for trigger A to send a signal is 8ns and the time for trigger B to receive a signal is 10ns, the total path delay of the timing path is 2ns > the preset delay of 1ns, and timing path 2 is a timing violation path. Timing path 3 Trigger A to output buffer A: Assuming that the time for trigger A to send a signal is 8ns and the time for output buffer A to receive a signal is 10ns, the total path delay of the timing path is 2ns < the preset delay of 4ns, and the timing path is not a timing violation path. Timing path 4 from input buffer A to output buffer A: Assume that the time for input buffer A to send a signal is 10ns, the time for output buffer A to receive a signal is 13ns, the total path delay of the timing path is 3ns < the preset delay of 4ns, and timing path 4 is not a timing violation path. This embodiment can more accurately identify and evaluate timing risks by determining the total path delay of the target timing path, thereby improving the accuracy and reliability of integrated circuit design.
[0049] In an exemplary embodiment, before determining the timing node closest to the above-mentioned starting timing node among the multiple intermediate timing nodes included in the above-mentioned timing violation path and obtaining the target intermediate timing node, the above-mentioned method also includes: traversing the N intermediate timing nodes connected to the above-mentioned starting timing node in the above-mentioned timing violation path, and storing the N above-mentioned intermediate timing nodes visited into an access queue, wherein the above-mentioned access queue is used to store the above-mentioned intermediate timing nodes visited, the N above-mentioned intermediate timing nodes are timing nodes stored in the above-mentioned access queue in an access order, and the above-mentioned N is a natural number greater than or equal to 1.
[0050] Optionally, a breadth-first search may be used to traverse N intermediate timing nodes connected to the start timing node in the timing violation path. Figure 3 As shown, Figure 3 A method for optimizing a target timing path according to a specific embodiment of the present application is shown in FIG. Figure 1 , assuming that the timing path from trigger A to trigger C and trigger D is a timing violation path, firstly, trigger A is used as the starting timing node, and the system component B directly connected to trigger A is accessed, and the system component B is stored in the access queue as the intermediate timing node B, and then the trigger C and trigger D directly connected to the system component B are accessed, that is, the trigger C and trigger D fanned out by trigger A are accessed, and the complete timing violation fan-out path is trigger A-system component B-trigger C, trigger A-system component B-trigger D. This embodiment achieves the purpose of accurately determining the timing violation fan-out paths across all module levels of the hierarchical integrated circuit by determining multiple intermediate timing nodes included in the timing violation.
[0051] In an exemplary embodiment, determining the timing node closest to the starting timing node among the multiple intermediate timing nodes included in the timing violation path to obtain the target intermediate timing node includes: obtaining the coordinates of the starting timing node and the coordinates of the multiple intermediate timing nodes; respectively calculating the Manhattan distance between each of the intermediate timing nodes and the starting timing node to obtain multiple Manhattan distances, wherein the Manhattan distance D(i, j)=|x i -x j |+|y i -y j |, the above (x i ,y i ) is the coordinate of the starting time sequence node, and the above (x j ,y j ) are the coordinates of the intermediate timing node; the intermediate timing node closest to the starting timing node is determined as the target intermediate timing node.
[0052] Optionally, assuming that there is a simplified integrated circuit layout, the timing violation path includes the following timing nodes and their coordinates (expressed in a simplified two-dimensional space): starting timing node-trigger A-coordinate (3, 3), intermediate timing node-logic gate L1-coordinate (4, 3), intermediate timing node-logic gate L2-coordinate (3, 4), intermediate timing node-trigger B-coordinate (2, 3), and ending timing node-trigger C: coordinate (3, 2). The Manhattan distance is calculated as follows: logic gate L1-D (A, L1) = |3-4| + |3-3| = 1, logic gate L2-D (A, L2) = |3-3| + |3-4| = 1, trigger BD (A, B) = |3-2| + |3-3| = 1. This embodiment solves the problem of simulation, verification, and functional engineering change orders (Engineering Change Orders) caused by excessive flattening of modules or cancellation of the original hierarchical structure in the hierarchical physical design of integrated circuits by determining the intermediate timing node closest to the starting timing node. Order, referred to as ECO) insertion and other difficulties, and achieved the goal of solving timing violation problems with minimal module parallelization.
[0053] In an exemplary embodiment, determining the functional module of the target timing node based on a merge operation performed on the functional module of the target intermediate timing node and the functional module of the starting timing node includes: obtaining multiple first interface information of the functional module of the target intermediate timing node and multiple second interface information of the functional module of the starting timing node, wherein the first interface information includes the input and output functions of the first interface of the functional module of the target intermediate timing node, and the second interface information includes the input and output functions of the second interface of the functional module of the starting timing node; based on the first interface information and the second interface information, merging the first target interface and the second target interface to determine the target interface, wherein the first target interface has the same input and output functions as the second target interface, and the first target interface is an interface among the multiple first interfaces, and the second target interface is an interface among the multiple second interfaces; based on the target interface, merging the first target system component and the second target system component to determine the functional module of the target timing node, wherein the first target system component is a component in the functional module of the target intermediate timing node, and the second target system component is a component in the functional module of the starting timing node.
[0054] Optionally, the interface information of the functional module includes but is not limited to signal name, interface type, interface width, and the input and output functions include but are not limited to signal transmission, data synchronization, interface protocol support, level conversion, signal buffering, signal amplification, signal shaping, digital / analog conversion, error detection and correction, power management, grounding and signal return, signal isolation, communication rate adjustment, temperature and environment monitoring, configuration and control. Assume that there is an integrated circuit for digital signal processing, and the target timing violation path is: trigger A-logic gate L1-flip-flop C, where the starting timing node trigger A is a clock distribution module responsible for distributing the system clock, and the functional module has two second interfaces: I2C1 (for data input) and CLK1 (for clock output), and the target intermediate timing node logic gate L1 is a data processing module responsible for processing input data, and the functional module has two first interfaces: I2C2 (for data output) and CLK2 (for clock input). Based on the first interface information of the target intermediate timing node logic gate L1 and the second interface information of the starting timing node trigger A, it is found that I2C1 and I2C2 have the same data input and output functions, and CLK1 and CLK2 have the same clock function, so I2C1 and I2C2 can be merged into the target interface I2C, CLK1 and CLK2 can be merged into the target interface CLK, and the clock output component of the clock distribution module can be merged with the data input component of the data processing module to form a functional module of the target timing node, which can process data while receiving the clock signal. This embodiment can improve the timing synchronization between functional modules of different system components in the integrated circuit by ensuring the consistency of the interface function, and achieves the purpose of ensuring that the data and clock signals between the functional modules after the merge operation can be seamlessly transmitted. At the same time, merging interfaces with similar functions can reduce resource waste, and achieve the purpose of improving the utilization of hardware and software resources and reducing hardware costs.
[0055] The present application is described below in conjunction with specific embodiments:
[0056] In this specific embodiment, Figure 5 is a flow chart of a method for optimizing a target timing path according to a specific embodiment of the present application. Figure 5 As shown, the specific steps include:
[0057] S502, start;
[0058] S504, such as Figure 3 As shown, Figure 3 A method for optimizing a target timing path according to a specific embodiment of the present application is shown in FIG. Figure 1, assuming that the timing path from trigger A to trigger C and trigger D is known to be the timing violation path. First, take trigger A as the starting timing node, access the system component B directly connected to trigger A, store system component B as the intermediate timing node B in the access queue, and then access trigger C and trigger D directly connected to system component B, that is, access trigger C and trigger D fanned out by trigger A, and determine that the complete timing violation fan-out path is trigger A-system component B-trigger C, trigger A-system component B-trigger D;
[0059] S506, starting from the starting timing node, moving forward with Manhattan distance, setting the functional module of the timing node closest to the starting timing node as the module to be flattened: starting timing node-trigger A-coordinate (3, 3), system component B-coordinate (2, 3), calculating the Manhattan distance: system component BD(A, B)=|3-3|+|2-3|=1, determining that the module to be flattened is the functional module of system component B;
[0060] S508, eliminate module boundaries, and merge the functional modules of the starting timing node and the modules to be flattened: The starting timing node trigger A is a clock distribution module responsible for distributing the system clock. The functional module has two second interfaces: I2C 1 (for data input) and CLK1 (for clock output). The target intermediate timing node system component B is a data processing module responsible for processing input data. The functional module has two first interfaces: 12C2 (for data output) and CLK2 (for clock input). Based on the first interface information of the target intermediate timing node system component B and the second interface information of the starting timing node trigger A, it is found that 12C1 and I2C2 have the same data input and output functions, and CLK1 and CLK2 have the same clock function. Therefore, I2C1 and 12C2 can be merged into the target interface I2C, CLK1 and CLK2 can be merged into the target interface CLK, and the clock output component of the clock distribution module can be merged with the data input component of the data processing module to form a functional module of the target timing node, such as Figure 4 As shown, Figure 4 A method for optimizing a target timing path according to a specific embodiment of the present application is shown in FIG. Figure 2 ;
[0061] S510, performing logic sharing and logic optimization on the merged modules;
[0062] S512, if there is still a timing violation in the timing path after merging the functional modules, then determine the next module to be flattened and go to S508, otherwise go to S514;
[0063] S514, end.
[0064] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.
[0065] In the present embodiment, a device for optimizing a target timing path is also provided, which is applied to a system on chip, wherein the system on chip includes a plurality of system components, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, which have been described and will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.
[0066] Figure 6 is a structural block diagram of a device for optimizing a target timing path according to an embodiment of the present application, such as Figure 6 As shown, the device comprises:
[0067] A first determining module 602 is used to determine a timing violation path between a first system component and a second system component from a plurality of timing paths between the plurality of the system components, wherein each of the timing paths includes a plurality of timing nodes, one timing node corresponds to a functional module of the system component, a delay of the timing violation path is greater than a preset delay, and a starting timing node of the timing violation path is a functional module of the first system component, an ending timing node is a functional module of the second system component, and the first system component and the second system component are both components among the plurality of the system components;
[0068] A second determining module 604 is used to determine the timing node closest to the start timing node among the multiple intermediate timing nodes included in the timing violation path, and obtain a target intermediate timing node;
[0069] A third determining module 606, configured to determine a target timing node based on a merging operation performed on the functional module of the target intermediate timing node and the functional module of the starting timing node;
[0070] The fourth determining module 608 is used to determine the timing path between the target timing node and the end timing node as the target timing path between the first system component and the second system component.
[0071] In an exemplary embodiment, the above-mentioned device also includes: a first calculation module, which is used to determine the timing path between the above-mentioned target timing node and the above-mentioned end timing node as the target timing path between the above-mentioned first system component and the above-mentioned second system component, and then calculate the total path delay of the above-mentioned target timing path based on the time when the first preset signal is transmitted from the above-mentioned target timing node to the above-mentioned end timing node; a fifth determination module, which is used to determine the above-mentioned target timing path as a target timing violation path when the total path delay of the above-mentioned target timing path is greater than the above-mentioned preset delay.
[0072] In an exemplary embodiment, the above-mentioned device also includes: a sixth determination module, which is used to determine the target timing path as a target timing violation path after the total path delay of the above-mentioned target timing path is greater than the above-mentioned preset delay, and then determine the timing node closest to the target start timing node among the multiple target intermediate timing nodes included in the above-mentioned target timing violation path to obtain a first target intermediate timing node; a seventh determination module, which is used to determine the functional module of the first target timing node based on a merge operation performed on the functional module of the above-mentioned first target intermediate timing node and the functional module of the above-mentioned target start timing node; and an eighth determination module, which is used to determine the timing path between the above-mentioned first target timing node and the target end timing node as the first target timing path between the above-mentioned first system component and the above-mentioned second system component, wherein the delay of the above-mentioned first target timing path is less than the above-mentioned preset delay.
[0073] In an exemplary embodiment, the first determination module includes: a first identification submodule, used to identify multiple timing paths between the multiple system components based on the transmission direction of the second preset signal, wherein the transmission direction of the second preset signal includes at least one of the following: the first input system component transmits to the first output system component, the first input system component transmits to the first trigger system component, the first trigger system component transmits to the second trigger system component, and the first trigger system component transmits to the first output system component, and the first input system component, the first output system component, the first trigger system component and the second trigger system are all components among the multiple system components; a first calculation submodule, used to calculate the total path delay of each of the timing paths based on the time when the second preset signal is transmitted from the starting system component to the ending system component, wherein the starting system component includes the first input system component and the first trigger system component, and the ending system component includes the second trigger system component and the first output system component; a first determination submodule, used to determine the timing path whose total path delay is greater than the preset delay as the timing violation path.
[0074] In an exemplary embodiment, the above-mentioned device also includes: a first traversal module, which is used to determine the timing node closest to the above-mentioned starting timing node among the multiple intermediate timing nodes included in the above-mentioned timing violation path, and before obtaining the target intermediate timing node, traverse the N intermediate timing nodes connected to the above-mentioned starting timing node in the above-mentioned timing violation path, and store the N above-mentioned intermediate timing nodes visited in an access queue, wherein the above-mentioned access queue is used to store the above-mentioned intermediate timing nodes visited, and the N above-mentioned intermediate timing nodes are timing nodes stored in the above-mentioned access queue in an access order, and the above-mentioned N is a natural number greater than or equal to 1.
[0075] In an exemplary embodiment, the second determination module includes: a first acquisition submodule, used to acquire the coordinates of the starting timing node and the coordinates of the plurality of intermediate timing nodes; a second calculation submodule, used to respectively calculate the Manhattan distance between each of the intermediate timing nodes and the starting timing node to obtain a plurality of Manhattan distances, wherein the Manhattan distance D(i, j)=|x i -x j |+|y i -y j |, the above (x i ,y i ) is the coordinate of the starting time sequence node, and the above (x j ,y j) is the coordinate of the above-mentioned intermediate timing node; the second determination submodule is used to determine the intermediate timing node closest to the above-mentioned starting timing node as the above-mentioned target intermediate timing node.
[0076] In an exemplary embodiment, the third determination module includes: a second acquisition submodule, used to acquire multiple first interface information of the functional module of the target intermediate timing node and multiple second interface information of the functional module of the starting timing node, wherein the first interface information includes the input and output functions of the first interface of the functional module of the target intermediate timing node, and the second interface information includes the input and output functions of the second interface of the functional module of the starting timing node; a third determination submodule, used to merge the first target interface and the second target interface based on the first interface information and the second interface information to determine the target interface, wherein the first target interface has the same input and output functions as the second target interface, and the first target interface is an interface among the multiple first interfaces, and the second target interface is an interface among the multiple second interfaces; a first merging submodule, used to merge the first target system component and the second target system component based on the target interface to determine the functional module of the target timing node, wherein the first target system component is a component in the functional module of the target intermediate timing node, and the second target system component is a component in the functional module of the starting timing node.
[0077] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when running.
[0078] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.
[0079] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.
[0080] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.
[0081] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
[0082] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.
[0083] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.
[0084] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.
[0085] The embodiments of the present application also provide a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.
[0086] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.
[0087] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.
[0088] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.
Claims
1. A method for optimizing a target timing path, characterized in that: Applied to a system on chip, the system on chip includes a plurality of system components, the method comprising: Determine a timing violation path between a first system component and a second system component from a plurality of timing paths between a plurality of the system components, wherein each of the timing paths includes a plurality of timing nodes, one timing node corresponds to a functional module of the system component, a delay of the timing violation path is greater than a preset delay, a starting timing node of the timing violation path is a functional module of the first system component, an ending timing node is a functional module of the second system component, and the first system component and the second system component are both components among the plurality of the system components; Determine a timing node closest to the start timing node among a plurality of intermediate timing nodes included in the timing violation path, and obtain a target intermediate timing node; Determine the functional module of the target timing node based on the merging operation performed on the functional module of the target intermediate timing node and the functional module of the starting timing node; A timing path between the target timing node and the end timing node is determined as a target timing path between the first system component and the second system component.
2. The method according to claim 1, characterized in that After determining the timing path between the target timing node and the end timing node as the target timing path between the first system component and the second system component, the method further includes: Calculating a total path delay of the target timing path based on the time taken for the first preset signal to be transmitted from the target timing node to the end timing node; When the total path delay of the target timing path is greater than the preset delay, the target timing path is determined as a target timing violation path.
3. The method according to claim 2, characterized in that In a case where the total path delay of the target timing path is greater than the preset delay, after determining the target timing path as a target timing violation path, the method further includes: Determine a timing node closest to a target start timing node among a plurality of target intermediate timing nodes included in the target timing violation path, and obtain a first target intermediate timing node; Determine the functional module of the first target timing node based on the merging operation performed on the functional module of the first target intermediate timing node and the functional module of the target starting timing node; A timing path between the first target timing node and the target end timing node is determined as a first target timing path between the first system component and the second system component, wherein a delay of the first target timing path is less than the preset delay.
4. The method according to claim 1, characterized in that Determining a timing violation path between a first system component and a second system component from a plurality of timing paths between a plurality of the system components includes: Based on the transmission direction of the second preset signal, identifying multiple timing paths between the multiple system components, wherein the transmission direction of the second preset signal includes at least one of the following: the first input system component transmits to the first output system component, the first input system component transmits to the first trigger system component, the first trigger system component transmits to the second trigger system component, the first trigger system component transmits to the first output system component, and the first input system component, the first output system component, the first trigger system component and the second trigger system component are all components in the multiple system components; Calculating the total path delay of each of the timing paths based on the time taken for the second preset signal to be transmitted from the starting system component to the ending system component, wherein the starting system component includes the first input system component and the first trigger system component, and the ending system component includes the second trigger system component and the first output system component; The timing path whose total path delay is greater than the preset delay is determined as the timing violation path.
5. The method according to claim 1, characterized in that Before determining a timing node closest to the start timing node among a plurality of intermediate timing nodes included in the timing violation path and obtaining a target intermediate timing node, the method further includes: Traverse the N intermediate timing nodes connected to the starting timing node in the timing violation path, and store the visited N intermediate timing nodes in an access queue, wherein the access queue is used to store the visited intermediate timing nodes, the N intermediate timing nodes are timing nodes stored in the access queue in an access order, and N is a natural number greater than or equal to 1.
6. The method according to claim 1, characterized in that Determining a timing node closest to the start timing node among a plurality of intermediate timing nodes included in the timing violation path to obtain a target intermediate timing node includes: Acquire the coordinates of the starting timing node and the coordinates of the plurality of intermediate timing nodes; The Manhattan distance between each intermediate timing node and the starting timing node is calculated respectively to obtain multiple Manhattan distances, where the Manhattan distance D(i, j)=|x i -x j |+|y i -y j |, the (x i ,y i ) is the coordinate of the starting time sequence node, and the (x j ,y j ) are the coordinates of the intermediate timing nodes; The intermediate timing node that is closest to the start timing node is determined as the target intermediate timing node.
7. The method according to claim 1, characterized in that Determining the functional module of the target timing node based on a merging operation performed on the functional module of the target intermediate timing node and the functional module of the starting timing node includes: Acquire multiple first interface information of the functional module of the target intermediate timing node and multiple second interface information of the functional module of the starting timing node, wherein the first interface information includes the input and output functions of the first interface of the functional module of the target intermediate timing node, and the second interface information includes the input and output functions of the second interface of the functional module of the starting timing node; Based on the first interface information and the second interface information, merging a first target interface and a second target interface to determine a target interface, wherein the first target interface and the second target interface have the same input and output functions, and the first target interface is an interface among a plurality of the first interfaces, and the second target interface is an interface among a plurality of the second interfaces; Based on the target interface, a first target system component and a second target system component are merged to determine a functional module of the target timing node, wherein the first target system component is a component in the functional module of the target intermediate timing node, and the second target system component is a component in the functional module of the starting timing node.
8. A device for optimizing a target timing path, characterized in that: Applied to a system on chip, the system on chip includes multiple system components, and the device includes: A first determining module is used to determine a timing violation path between a first system component and a second system component from a plurality of timing paths between a plurality of the system components, wherein each of the timing paths includes a plurality of timing nodes, one timing node corresponds to a functional module of the system component, a delay of the timing violation path is greater than a preset delay, and a starting timing node of the timing violation path is a functional module of the first system component, an ending timing node is a functional module of the second system component, and the first system component and the second system component are both components among the plurality of the system components; a second determining module is used to determine a timing node closest to the starting timing node among a plurality of intermediate timing nodes included in the timing violation path, and obtain a target intermediate timing node; A third determining module, configured to determine a target timing node based on a merging operation performed on a functional module of the target intermediate timing node and a functional module of the starting timing node; The fourth determining module is used to determine the timing path between the target timing node and the end timing node as the target timing path between the first system component and the second system component.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.
10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.