High-speed image data real-time compression memory and aerospace craft
By using high-speed image data real-time compression memory on spacecraft and using a full-digital disappearance filter chip to replace the DSP chip for compression, the problem of high development cost of spacecraft storage devices is solved, high-speed, real-time compression and storage of data is achieved, and the data is reduced. Development costs and cache occupancy.
Patent Information
- Application Number
- CN202411403663.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-03
AI Technical Summary
The development cost of image storage devices on spacecraft is high, mainly due to the long development cycle of digital signal processing chip (DSP) software, which leads to the high cost of storage devices.
Using high-speed image data real-time compression memory, including processing chips, cache modules, compression modules and storage modules, using a full digital disappearance filter chip (ADV212) to replace the DSP chip for compression, realizing data compression while receiving and through multiple DDR cache modules Improve storage efficiency.
It reduces the memory development cost, improves storage efficiency and stability, reduces the storage space occupied by the cache module, and realizes high-speed and real-time processing of image data.
Smart Images
Figure CN119251042A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of image processing, and in particular relates to a high-speed image data real-time compression memory and a spacecraft. Background Art
[0002] With the development of spacecraft payload remote sensing technology, the code rate of satellite front-end camera payload is getting higher and higher, the amount of data is increasing, and the requirement for efficient storage is getting higher and higher.
[0003] Since the distortion of images after compression is relatively small, in order to reduce the amount of data transmitted when communicating with the ground, the current storage device on the spacecraft first stores the image in a double data rate synchronous dynamic random access memory (Double Data Rate, DDR), and after receiving the instructions sent by the ground, uses a digital signal processing chip (Digital Signal Processing, DSP) to compress the image and transmit it to the ground. However, the long development cycle of DSP software leads to a high cost of the storage device.
[0004] Therefore, the development cost of storage devices on current spacecraft is relatively high. Summary of the invention
[0005] The embodiments of the present invention provide a high-speed image data real-time compression memory and a spacecraft, which can solve the problem of high development cost of storage devices on previous spacecrafts.
[0006] In a first aspect, an embodiment of the present invention provides a high-speed image data real-time compression memory, comprising: a processing chip, a cache module, a compression module and a storage module;
[0007] The cache module is connected to the first input and output terminal of the processing chip, the compression module is connected to the second input and output terminal of the processing chip, and the storage module is connected to the third input and output terminal of the processing chip, wherein the processing chip is provided with a high-speed transceiver interface, and the compression module includes a plurality of all-digital disappearance filter chips;
[0008] The processing chip receives the effective load data through the high-speed transceiver interface, divides the effective load data and temporarily stores it in the cache module, the compression module compresses the divided effective load data, and the storage module saves the compressed effective load data.
[0009] In a possible implementation manner of the first aspect, the processing chip is a FPGA chip.
[0010] In a possible implementation manner of the first aspect, the all-digital disappearance filter chip is an ADV212 chip.
[0011] In a possible implementation manner of the first aspect, the cache module includes multiple DDRs.
[0012] In a possible implementation manner of the first aspect, the number of DDRs in the cache module is greater than the number of all-digital disappearance filter chips in the compression module.
[0013] In a possible implementation manner of the first aspect, the cache module includes 5 DDRs, and the compression module includes 4 all-digital disappearance filter chips.
[0014] In a second aspect, an embodiment of the present invention provides a spacecraft, comprising a photographing device and the high-speed image data real-time compression memory described in the first aspect.
[0015] Compared with the prior art, the embodiment of the present invention has the beneficial effect of reducing the development cost of the memory by using an ADV chip instead of a DSP chip for compression. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic diagram of the structure of a high-speed image data real-time compression memory provided by an embodiment of the present invention;
[0017] Figure 2 A schematic diagram of a scene of sub-block storage provided by an embodiment of the present invention;
[0018] Figure 3 A schematic diagram of a scene of pixel storage in a sub-block provided by an embodiment of the present invention;
[0019] Figure 4 A schematic structural diagram of a spacecraft provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0020] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.
[0021] Example 1
[0022] Figure 1 The structure diagram of a high-speed image data real-time compression memory provided by the present invention is shown. As an example but not a limitation, the high-speed image data real-time compression memory may include a processing chip 1, a cache module 2, a compression module 3 and a storage module 4.
[0023] In some embodiments, see Figure 1 The input and output ends of the cache module 2, the compression module 3 and the storage module 4 are respectively connected to the first input and output end, the second input and output end and the third input and output end of the processing chip 1.
[0024] Exemplarily, the processing chip 1 is provided with a high-speed transceiver interface GTX.
[0025] Specifically, the processing chip 1 can receive the payload data (i.e., the captured image) of the front end through a high-speed transceiver interface, and then divide it into sub-image blocks, and write the sub-image blocks into the cache module 3 for temporary storage in the order of the divided sub-image blocks (i.e., the divided payload data). At the same time, the sub-image blocks in the cache module 3 are read and sent to the compression module 4, and the compression module 4 compresses each sub-image block to obtain compressed payload data. Finally, the compressed payload data is stored in the storage module 4. After receiving the data request from the ground receiving end, the processing chip 1 can send the compressed payload data in the storage module 4 to the ground receiving end through the high-speed transceiver interface. The ground receiving end can decompress it, for example, by decompressing it through JPEG2000 decompression software to restore the original image.
[0026] Exemplarily, the compression module 3 may include a plurality of all-digital vanishing filter (ADV) chips. Compared with DSP chips, the development cycle of ADV chips is shorter, so the development cost of the memory composed of ADV chips is lower.
[0027] At the same time, due to the high performance of the ADV chip, the memory can compress the payload data while receiving it, and finally store all the payload data in the form of compressed data. Compared with the current storage device that directly stores the payload data and then compresses the payload data after receiving the ground compression instruction, the present invention stores and compresses it through the compression module, and only a small amount of data needs to be stored in the cache module 2, which can reduce the area of the storage space occupied by the cache module 2 and improve the utilization rate of the cache module. The ADV chip with a self-check function can also perform a self-check before starting compression to improve the stability of the memory and prevent data loss.
[0028] Optionally, the image auxiliary data sent by the front end can be directly stored in the storage module 4 through the processing chip 1 .
[0029] In a possible implementation, the processing chip 1 may be an FPGA chip. FPGA chips have good compatibility and adaptability and can operate stably in complex and harsh aerospace environments.
[0030] Exemplarily, the processing chip 1 may transfer the compressed effective load data to the storage module 4 through a register.
[0031] In a possible implementation, the cache module 2 may include multiple DDRs.
[0032] In one example, since the front-end acquires and processes data at a high rate, the storage rate of DDR does not match it, and therefore the number of DDR chips can be greater than the number of ADV chips to meet the demand for high-speed, real-time processing of effective load data.
[0033] Optionally, the cache module 2 may include 5 DDRs, and the compression module may include 4 ADV chips.
[0034] Exemplarily, the processing chip 1 can divide the storage space of DDR into multiple address segments, one ADV chip can correspond to multiple addresses, and these addresses form an address segment. The effective load data compressed by each ADV chip is stored in the corresponding address segment in sequence.
[0035] For example, see Figure 2 , address 1-address 75 of a DDR can be divided into an address segment, address 76-150 can be divided into an address segment... The address segment corresponding to ADV chip 1 can be address 1-75, address 126-200; the address segment corresponding to ADV chip 2 can be address 76-150, address 201-275... The sub-block 1 compressed by ADV chip 1 can be stored at address 1-address 75, the sub-block 2 compressed by ADV chip 2 can be stored at address 76-150..., and the sub-block 5 compressed by ADV chip 1 can be stored at address 151-225.
[0036] Exemplarily, the processing chip 2 may store the data of each pixel point into the DDR according to the order of the pixels in the sub-block.
[0037] For example, if the size of a sub-block is 512 pixels * 128 pixels, one pixel occupies 1 byte. Figure 3 , pixel 1 can be stored at address 1 in the first DDR, pixel 2 can be stored at address 2, and so on, until all pixels of the first sub-block are stored in the first DDR.
[0038] As an example, the model of the processing chip 1 may be xc7k480tffg901, and the model of the DDR in the cache module 2 may be MT41K512M16, whose effective rate may reach 51.2 Gbps and may provide data to multiple ADV chips at the same time. The model of the ADV chip may be ADV212. The storage module may be a general SATA or NVME solid-state hard disk.
[0039] Exemplarily, when the model of the ADV chip is ADV212, in the case of 9 / 7 wavelet transform and the effective load data is a color image, the maximum compression capability of ADV212 is 1024 pixels * 2048 pixels. Therefore, the size of a sub-block cannot exceed 1024 pixels * 2048 pixels. In the case of 9 / 7 wavelet transform and the effective load data is a single-channel image, such as a grayscale image, the maximum compression capability of ADV212 is 2048 pixels * 2048 pixels. Therefore, the size of a sub-block cannot exceed 2048 pixels * 2048 pixels. Therefore, when the captured image is large, it needs to be divided into multiple sub-blocks and stored in different DDRs.
[0040] Exemplarily, since the data format recognizable by ADV212 is YUV4:2:2 format, the processing chip 1 also needs to convert the effective load data into YUV4:2:2 format and then input it into ADV212 for compression.
[0041] For example, if the payload data is a color image in the Bayer format, the processing chip 1 may first perform color space conversion on the payload data and then combine it into a YUV4:2:2 format and send it to the ADV212 for compression.
[0042] Specifically, the processing chip 1 can call its internal Xilinx IP core RGB to YCrCb Color-SpaceConvert and Color Filter Array Interpolation to perform format conversion.
[0043] For example, if the effective load data is a grayscale image, the processing chip 1 can directly combine the YUV value of each pixel into a YUV4:2:2 format and send it to ADV212 for compression.
[0044] According to the high-speed image data real-time compression memory provided by the present invention, the development cost of the memory can be reduced by using an ADV chip instead of a DSP chip for compression.
[0045] Figure 4 Shown is a schematic structural diagram of a spacecraft provided by the present invention.
[0046] For example, see Figure 4 The spacecraft may include a photographing device 41 and a high-speed image data real-time compression memory 42 .
[0047] Exemplarily, the camera 41 may acquire the payload data and send it to the high-speed image data real-time compression memory 42, which compresses and stores the data. The high-speed image data real-time compression memory 42 may be the high-speed image data real-time compression memory provided in the above embodiment.
[0048] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0049] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.
[0050] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0051] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.
Claims
1. A high-speed image data real-time compression memory, characterized in that: It includes a processing chip, a cache module, a compression module and a storage module; The cache module is connected to the first input and output terminal of the processing chip, the compression module is connected to the second input and output terminal of the processing chip, and the storage module is connected to the third input and output terminal of the processing chip, wherein the processing chip is provided with a high-speed transceiver interface, and the compression module includes a plurality of all-digital disappearance filter chips; The processing chip receives the effective load data through the high-speed transceiver interface, and divides the effective load data and temporarily stores it in the cache module. The compression module compresses the divided effective load data, and the storage module saves the compressed effective load data.
2. The high-speed image data real-time compression memory according to claim 1, characterized in that: The processing chip is a FPGA chip.
3. The high-speed image data real-time compression memory according to claim 1, characterized in that: The all-digital disappearing filter chip is an ADV212 chip.
4. The high-speed image data real-time compression memory according to claim 1, characterized in that: The cache module includes a plurality of DDRs.
5. The high-speed image data real-time compression memory according to claim 4, characterized in that: The number of DDRs in the cache module is greater than the number of all-digital disappearance filter chips in the compression module.
6. The high-speed image data real-time compression memory according to claim 5, characterized in that: The cache module includes 5 DDRs, and the compression module includes 4 full digital disappearance filter chips.
7. A spacecraft, characterized in that: The spacecraft comprises a photographing device and a high-speed image data real-time compression memory as described in any one of claims 1-6.