Semiconductor device, electronic device, and electronic system

Abstract

A semiconductor device, an electronic device, and an electronic system are provided. The semiconductor device includes: a die stack including at least two semiconductor chips laterally arranged and isolated from each other by a molding material; and an interconnect package disposed above or below the die stack and connecting the semiconductor chips to each other, in which the interconnect package having a smaller lateral width than the die stack completely overlaps the die stack in a vertical direction, a capacitor is disposed inside the interconnect package and connected to at least one of the semiconductor chips and configured to be connected to a voltage source and ground.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims priority from U.S. Provisional Application No. 63 / 524,747 filed in the U.S. Patent and Trademark Office on July 3, 2023 and U.S. Non-provisional Application No. 18 / 625,690 filed in the U.S. Patent and Trademark Office on April 3, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Apparatus and methods relate to semiconductor devices including interconnect packages having capacitors embedded therein. Background Art

[0004] Semiconductor packaging technology has been rapidly developed to address the demand for high device density and performance of integrated circuits. In multi-chip semiconductor packaging, there are technical challenges in designing an interconnect structure connecting semiconductor chips in a semiconductor package, considering impedance and noise that adversely affect the performance of semiconductor devices including the semiconductor chips.

[0005] The information disclosed in this background technology section is known to the inventor or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0006] The present disclosure provides a semiconductor package, which includes at least one interconnect package, at least one capacitor is arranged in the at least one interconnect package and the at least one interconnect package is connected to a semiconductor chip, wherein the interconnect package is stacked above a package substrate and has a redistribution substrate therebetween. The redistribution substrate may include a plurality of wiring tracks that connect the semiconductor chip to another circuit element in the package substrate or outside the package substrate. The interconnect package may be included in the redistribution substrate. The semiconductor package may be a fan-out wafer level package (FOWLP). The capacitor may be a decoupling capacitor configured to reduce the impedance and noise applied to a load (i.e., a semiconductor chip in the semiconductor package).

[0007] Although the decoupling capacitor is generally implemented by a die side capacitor (DSC) or a land side capacitor (LSC) respectively arranged on the top surface or the bottom surface of the package substrate, the semiconductor package according to the embodiment may include at least one capacitor in the interconnect package, and the at least one capacitor is provided to locally connect the semiconductor chips to each other with a small footprint. Therefore, at least one of the DSC and the LSC can be removed from the semiconductor package, because the capacitor in the interconnect package can replace the removed DSC or LSC as a decoupling capacitor. The capacitor included in the interconnect package can be referred to as an integrated stacked capacitor (ISC), which has a thickness of several microns or less and a very high capacitance density.

[0008] The interconnect package may include at least one redistribution layer in which a plurality of dielectric layers and wiring traces are formed, and the capacitor may be formed on at least one of the wiring traces.

[0009] In the interconnect package, a redistribution layer may be formed on an upper portion of the interconnect package, and a capacitor may be formed on an upper portion of the redistribution layer, so that the capacitor may be disposed close to the semiconductor chip to obtain better decoupling performance.

[0010] In the case where the capacitor is embedded in a redistribution layer in an interconnect package, the semiconductor package can achieve power delivery to a semiconductor chip with low impedance and noise and a small footprint in a semiconductor device including the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1A shows a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to an embodiment;

[0013] Figure 1B According to an embodiment, the Figure 1A A schematic cross-sectional view of an interconnect package in a semiconductor package is shown;

[0014] Figure 2A shows a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to another embodiment, Figure 2B According to an embodiment, the Figure 2A A schematic cross-sectional view of an interconnect package in a semiconductor package is shown;

[0015] Figure 3A shows a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to yet another embodiment, Figure 3B According to an embodiment, the Figure 3A A schematic cross-sectional view of an interconnect package in a semiconductor package is shown;

[0016] Figure 4 A flow chart showing a method of manufacturing a semiconductor package including an interconnect package and a decoupling capacitor therein according to an embodiment;

[0017] Figures 5A-5F According to an embodiment, the Figure 4 The intermediate semiconductor package after the corresponding steps of the flowchart shown to manufacture the semiconductor package including the interconnect package and the decoupling capacitor;

[0018] Figure 5A According to the embodiment, Figure 4 The intermediate semiconductor package after step S10 is shown;

[0019] Figure 5B According to the embodiment, Figure 4 The intermediate semiconductor package after step S20 is shown;

[0020] Figure 5C According to the embodiment, Figure 4 The intermediate semiconductor package after step S30 is shown;

[0021] Figure 5D According to the embodiment, Figure 4 The intermediate semiconductor package after step S40 is shown;

[0022] Figure 5E According to the embodiment, Figure 4 The intermediate semiconductor package after step S50 is shown;

[0023] Fig. 5F According to the embodiment, Figure 4 The intermediate semiconductor package after step S60 is shown; and

[0024] Figure 6 is a diagram showing a method including Figure 2A-2B and / or Figure 3A-3B A schematic block diagram of an electronic device having at least one semiconductor package is shown. DETAILED DESCRIPTION

[0025] The embodiments of the present disclosure described here are example embodiments, and therefore, the present disclosure is not limited thereto and can be implemented in various other forms. It is not excluded that each embodiment provided in the following description is associated with one or more features of another embodiment or another example that is also provided herein or not provided herein but consistent with the present disclosure. For example, even if the matters described in a specific example or embodiment are not described in an example or embodiment different therefrom, these matters can also be understood to be related to or combined with the different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural equivalents and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described here can take different types or forms, as long as the present disclosure can be applied thereto.

[0026] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on" another element of the semiconductor device, "above" another element of the semiconductor device, "on" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "under" another element of the semiconductor device, or "connected to" another element of the semiconductor device, it can be directly on, directly above, directly on, directly below, directly below, directly below, directly connected to, or directly connected to the other element, or there may be intervening elements. In contrast, when an element of a semiconductor device is referred to as being “directly on” another element of the semiconductor device, “directly over” another element of the semiconductor device, “directly on” another element of the semiconductor device, “directly below” another element of the semiconductor device, “directly under” another element of the semiconductor device, “directly connected to” another element of the semiconductor device, or “directly coupled to” another element of the semiconductor device, there are no intervening elements. Like reference numerals refer to like elements throughout this disclosure.

[0027] For ease of description, spatial relationship terms such as "above", "above", "on", "below", "below", "below", "under", "under", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used here to describe the relationship of an element to another element as shown in the figure. It will be understood that in addition to the orientations depicted in the figure, the spatial relationship terms are also intended to cover different orientations of the semiconductor device in use or operation. For example, if the semiconductor device in the figure is turned over, the element described as "below" or "below" another element will be oriented to be "above" the other element. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device can be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used here are interpreted accordingly. As another example, when a device or structure including elements referred to as "left" elements and "right" elements is oriented differently, the elements referred to as "left" elements and "right" elements can be "right" elements and "left" elements. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, and necessary descriptions are made to distinguish the two elements.

[0028] It will be understood that although the terms "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0029] As used herein, expressions such as "at least one of," when following a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the term "same" or "equal" is used to compare the size of two or more elements, the term may encompass "substantially the same" or "substantially equal" sizes.

[0030] It will also be understood that when a method of manufacturing a device or structure is described as including multiple steps or operations, a step or operation described as being performed later than another step or operation may be performed before or simultaneously with the other step or operation, unless the other step or operation is described as being performed before the step or operation. In addition, the method may include additional steps or operations not mentioned in the description.

[0031] Many embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments (and intermediate structures). As such, variations relative to the illustrated shapes as a result of, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments should not be construed as limited to the specific shapes of the regions shown herein, but will include shape deviations, for example, caused by manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0032] For the sake of brevity, conventional elements, structures or layers included in semiconductor packages including connection pads, adhesive layers, isolation layers, barrier metal patterns, seed layers, etc. may or may not be described in detail here. For example, when certain connection pads of semiconductor chips connected to solder balls or bumps in semiconductor packages are irrelevant to the novel features of the embodiments, these structural elements may be omitted here. In addition, when the materials forming the well-known structural elements are irrelevant to the novel features of the embodiments, the description of these materials may be omitted. Here, the term "connection" between two structures or elements may refer to the electrical connection between them. For example, the connection between a semiconductor chip, a semiconductor package and / or a semiconductor device may refer to the electrical connection between two or more corresponding elements. The terms "connection" and "connection" may have the same meaning and are used interchangeably here. In addition, the term "isolation" between two structures or elements refers to electrical insulation or separation between them. For example, wiring patterns isolated from each other may mean that wiring patterns are not electrically connected to each other.

[0033] Below, various embodiments of the present disclosure refer to Figure 1A-6 to describe.

[0034] High-performance semiconductor chips such as central processing units (CPUs), graphics processing units (GPUs), artificial intelligence (AI) chips, etc. consume a greater amount of power than other types of semiconductor chips such as memory chips. For example, the power consumption of these high-performance chips can reach a very high level (e.g., about 1000W) for thermal design power (TDP). The greater power consumption poses a challenge to designing a power delivery network (PDN) for high-performance chips, and therefore, when designing and manufacturing semiconductor packages including high-performance chips, there is an increased need to design a PDN with low impedance across multiple frequency ranges.

[0035] The evolution of packaging multiple high performance semiconductor chips has introduced multiple different die-to-die interconnect structures, such as silicon interposers, which have grown in size to 3 or 4 times the size of the reticle, up to 3000mm 2 . The silicon interposer may include a redistribution layer (RDL) in which a plurality of wiring patterns or tracks are formed in one or more dielectric layers to connect semiconductor chips in a semiconductor package to each other. Therefore, the risk of power delivery in a multi-chip package including an interconnect structure has also become a consideration when designing a semiconductor package. In addition, when the interconnect structure includes active devices such as transistors and a metal layer therein, power consumption increases at a specific switching frequency of the active device. Therefore, there is a need to mitigate the risk of power delivery, or to reduce the impedance applied to a multi-chip package in which an interconnect structure connects semiconductor chips to each other.

[0036] A decoupling capacitor is included in a semiconductor package to control impedance and remove noise in a power delivery path to a semiconductor chip in the semiconductor package. As a decoupling capacitor, a semiconductor package of the related art includes one or more capacitors such as a multilayer ceramic capacitor (MLCC), a metal-insulator-metal (MiM) capacitor, a deep trench capacitor (DTC), etc. How to configure one or more decoupling capacitors in a semiconductor package may affect the power delivery performance of a semiconductor device of a semiconductor package including various high power demand semiconductor chips.

[0037] Figure 1A shows a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to an embodiment, Figure 1B According to an embodiment, the Figure 1A A schematic cross-sectional view of an interconnect package in a semiconductor package is shown.

[0038] Reference Figure 1AAccording to an embodiment, a semiconductor package 10 may include a package substrate 100, a redistribution substrate 200, and a die stack 300, wherein the redistribution substrate 200 is disposed above the package substrate 100, and the die stack 300 is disposed above the redistribution substrate 200 with a plurality of connection structures therebetween. The die stack 300 may include a plurality of semiconductor chips 300A-300C that are laterally arranged and isolated from each other, and the redistribution substrate 200 may include an interconnect package 400 therein.

[0039] The semiconductor package 10 may be a fan-out wafer level package (FOWLP), which may be characterized by connecting the semiconductor chip or die to one or more redistribution layers of the package substrate. Compared to other types of semiconductor packages (such as fan-in packages, wire bond packages, etc.), FOWLP allows for smaller package sizes and improved electrical performance. In FOWLP, the lateral edges of the package outline may extend in the D1 direction beyond the lateral edges of the semiconductor chips 300A-300C included therein, such as Figure 1A The lateral width WD1 of each of the die stack 300 and the redistribution substrate 200 may be smaller than the lateral width WD2 of the package substrate 100 . In addition, the lateral width WD1 of each of the die stack 300 and the redistribution substrate 200 may be greater than the lateral width WD3 of the interconnect package 400 .

[0040] Each of the semiconductor chips 300A-300C may be one of a system on chip (SoC), a microprocessor chip (such as a CPU, a GPU, a neural processing unit (NPU), etc.), an AI chip, an application specific integrated circuit (ASIC) chip, an image sensor chip, a power management chip, a memory chip, but is not limited thereto. The SoC may include a CPU, a GPU, an NPU, or an AI module.

[0041] The package substrate 100 may include a substrate core 100C, a lower buildup layer 100L below the substrate core 100C, and an upper buildup layer 100U above the substrate core 100C. The substrate core 100C may provide structural stability for the semiconductor package 10 and may be formed of an insulating material such as epoxy or ceramic, but is not limited thereto. The package substrate 100 may be a motherboard or a printed circuit board (PCB) of an electronic device or system. Alternatively, the package substrate 100 may be a part of a motherboard or a PCB of an electronic device or system.

[0042] The lower buildup layer 100L and the upper buildup layer 100U may be stacked on the bottom surface and the top surface of the substrate core 100C, respectively, to provide additional connection and routing space to the semiconductor package 10. The buildup layers 100L and 100U may each include one or more dielectric layers, and a plurality of wiring patterns 100W are formed in the one or more dielectric layers to connect to each other or to connect to a core via 100V that vertically penetrates the package substrate 100. Each wiring pattern in the dielectric layer may include at least one line portion and at least one via portion that are connected to each other to form a damascene structure. The line portion and the via portion may be respectively connected to the semiconductor package 10, which will be referred to later. Figure 1B The line portion L and the via portion V included in the described interconnect package 400 are the same or similar. The wiring pattern 100W may also be referred to as a wiring trace.

[0043] The wiring pattern 100W and the core via 100V may each be formed of a conductive material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo), but not limited thereto. The dielectric layer may be formed of an organic material such as a photosensitive polymer, for example, photosensitive polyimide, but not limited thereto. Alternatively or additionally, the dielectric layer may be formed of silicon oxide (e.g., SiO or SiO 2 ), silicon nitride (eg, SiN), silicon oxynitride (eg, SiON), and silicon carbon nitride (eg, SiCN), but is not limited thereto. The dielectric layer has an insulating property so that the wiring patterns 100W can be electrically isolated from each other in the dielectric layer.

[0044] In addition, a plurality of external terminals 100T (such as solder balls or bumps) may be formed on the bottom surface of the lower buildup layer 100L, which is also the bottom surface of the package substrate 100. The external terminals 100T may connect the semiconductor chips 300A-300C to external circuit elements through various connection structures included in the package substrate 100 and the redistribution substrate 200, which will be further described later, and formed across the package substrate 100 and the redistribution substrate 200.

[0045] A plurality of stiffeners 600 may be formed on the top surface of the perimeter of the package substrate 100 to prevent the package substrate 100 from warping, which may occur during a packaging process of the semiconductor package 10 or after the semiconductor package 10 is completed. The stiffeners 600 may be made of metal, ceramic, or a combination thereof, but are not limited thereto.

[0046] The redistribution substrate 200 may include a first redistribution layer 200L and a second redistribution layer 200U connected to each other through a plurality of first through vias 200V, and the plurality of first through vias 200V are isolated from each other by a first mold layer 200M formed of epoxy resin. The first redistribution layer 200L may be disposed to face the package substrate 100, and the second redistribution layer 200U may be disposed to face the die stack 300 including the semiconductor chips 300A-300C.

[0047] The redistribution layers 200L and 200U may each include a plurality of wiring traces therein, the plurality of wiring traces being isolated from each other by one or more vertically stacked dielectric layers and being respectively connected to the first through-via 200V. The wiring traces included in the first redistribution layer 200L may be connected to the core via 100V in the package substrate 100 through a plurality of lower connection terminals 200T, the plurality of lower connection terminals 200T being isolated from each other by the first bottom fill layer 200F. The first through-via 200V and the wiring traces in the redistribution layers 200L and 200U may also be formed of metals such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo), but are not limited thereto.

[0048] The wiring traces and dielectric layers in the redistribution layers 200L and 200U may be similar or identical in shape, material, and function or role to the wiring patterns and dielectric layers in the buildup layers 100L and 100U of the package substrate 100. Therefore, repeated descriptions may be omitted here. The first underfill layer 200F may be formed of epoxy resin, but is not limited thereto.

[0049] A die stack 300 including semiconductor chips 300A-300C may be disposed on the second redistribution layer 200U, and the semiconductor chips 300A-300C may each be a high-performance chip such as a system on chip (SoC) or a memory chip. The semiconductor chips 300A-300C may be connected to wiring traces in the second redistribution layer 200U through upper connection terminals 300T, and the upper connection terminals 300T are isolated from each other by a second bottom fill layer 300F, and the second bottom fill layer 300F may be formed of the same or similar material (e.g., epoxy resin) that forms the first bottom fill layer 200F.

[0050] For example, semiconductor chips 300A and 300C may be high bandwidth memories (HBM), and semiconductor chip 300B may be system-on-chip (SoC), but are not limited thereto. A second mold layer 300M, which may include, for example, epoxy resin, may be formed at side surfaces of the chips to laterally isolate each chip from other chips.

[0051] The upper connection terminal 300T and the lower connection terminal 200T may also be solder balls or bumps like the external terminal 100T, and may all be formed of a metal material such as copper (Cu), tin (Sb), lead (Pb), silver (Ag) or a compound thereof, but are not limited thereto.

[0052] The semiconductor package 10 may further include a plurality of interconnection packages 400 under the second redistribution layer 200U in the redistribution substrate 200 to connect or bridge the semiconductor chips 300A- 300C to each other.

[0053] For example, one of the interconnection packages 400 may be embedded in the redistribution substrate 200 below the boundary of the adjacent semiconductor chips 300A and 300B in the second mold layer 300M, and may at least partially overlap with each of the two semiconductor chips to reduce the connection length between the two semiconductor chips. In addition, the lateral width WD3 of the interconnection package 400 may be smaller than the lateral width WD1 of each of the redistribution substrate 200 and the die stack 300. Therefore, in the vertical direction (i.e., the D3 direction intersecting the D1 direction and the D2 direction), the entire lateral width of each of the die stack 300 and the redistribution substrate 200 may not completely overlap vertically with the entire lateral width of the interconnection package 400. That is, the entire lateral width of each of the die stack 300 and the redistribution substrate 200 may not coincide with the entire lateral width of the interconnection package 400.

[0054] Reference Figure 1A and Figure 1B , the interconnect package 400 may include a third redistribution layer 400R and a support layer 400S, and the support layer 400S is attached to the first redistribution layer 200L of the redistribution substrate 200 through a die attach film (DAF) 400F. The third redistribution layer 400R may include a dielectric layer 400D and a plurality of wiring traces 400W formed in the dielectric layer 400D. The wiring traces 400W may locally connect the two semiconductor chips 300A and 300B to each other, and may also be connected to a voltage source to deliver power to the semiconductor chips 300A and 300B through the second redistribution layer 200U and the upper connection terminals 300T connected to the second redistribution layer 200U.

[0055] Reference Figure 1B, the dielectric layer 400D of the interconnect package 400 may include a plurality of dielectric layers D11, D21, D31 and D4 vertically stacked on the support layer 400S. In addition, the wiring trace 400W may include one or more power wiring traces W1 and one or more signal wiring traces W2 embedded in the dielectric layers D11-D4. The power wiring trace W1 may include a power line and a ground line for the purpose of power transmission through the second redistribution layer 200U. The power wiring trace W1 may be configured to connect at least one of the semiconductor chips 300A and 300B to a voltage source. The signal wiring trace W2 may connect the two semiconductor chips 300A and 300B to each other. Each of the wiring traces W1 and W2 may include at least one line portion L and at least one via portion V connected to each other across the plurality of dielectric layers D11-D4 forming the dielectric layer 400D of the interconnect package 400.

[0056] In the present embodiment, the dielectric layer 400D includes four dielectric layers D11-D4. However, the present disclosure is not limited thereto, and according to the embodiment, the dielectric layer 400D may include more or less than four dielectric layers. For example, the dielectric layer 400D may even be a single dielectric layer.

[0057] Similarly, another interconnect package 400 may be disposed below the boundary between the adjacent semiconductor chips 300B and 300C in the second mold layer 300M, and the semiconductor chips 300B and 300C may be connected to each other through wiring traces 400W, wiring traces in the second redistribution layer 200U, and upper connection terminals 300T. Although not shown in the drawings, the semiconductor chips 300A-300C may each include connection pads on their bottom surfaces to connect to the upper connection terminals 300T.

[0058] The wiring traces 400W and the dielectric layer 400D in the third redistribution layer 400R may be formed of the same material as the wiring traces and the dielectric layer included in the first redistribution layer 200L and the second redistribution layer 200U. Therefore, repeated descriptions thereof may be omitted here. The support layer 400S supporting the dielectric layer 400D thereon may include, for example, at least one of silicon, glass, and ceramics, but is not limited thereto.

[0059] In addition, the semiconductor package 10 may further include a plurality of land side capacitors (LSC) 500L and die side capacitors (DSC) 500D respectively disposed on the bottom surface and the top surface of the package substrate 100. Each of the LSC 500L and the DSC 500D may be a decoupling capacitor that controls impedance and noise applied to the semiconductor chips 300A-300C and other active devices (if any) included in the semiconductor package 10. The LSC 500L and the DSC 500D may each be implemented by a multilayer ceramic capacitor (MLCC), a metal-insulator-metal (MiM) capacitor, or a deep trench capacitor (DTC).

[0060] Therefore, through these decoupling capacitors 500L and 500D, stable power delivery to the semiconductor chips 300A- 300C and other active devices can be achieved.

[0061] However, at least one of the semiconductor chips 300A-300C may be a SoC, and the SoC may include high-performance components that consume a larger amount of power, such as a CPU, GPU, NPU, or AI module. Therefore, additional decoupling capacitors may be required in the semiconductor package 10 including the semiconductor chips 300A-300C.

[0062] Figure 2A shows a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to another embodiment, Figure 2B According to an embodiment, the Figure 2A A schematic cross-sectional view of an interconnect package in a semiconductor package is shown.

[0063] Reference Figure 2A , the semiconductor package 20 may include Figure 1A The semiconductor package 10 is shown with the same structural elements in the same structural configuration, except that the interconnection packages 400 may each include a capacitor 700 in the third redistribution layer 400R. Therefore, the differences between the semiconductor package 20 and the semiconductor package 10 may be described below, and a repeated description thereof may be omitted.

[0064] The capacitor 700 may be a capacitor called an integrated stack capacitor (ISC) embedded in the interconnect package 400, but is not limited thereto, and may also be a capacitor as described in reference to Figure 1A The DSC 500D provided on the package substrate 100 is described to function as a decoupling capacitor like the LSC 500L.

[0065] Reference Figure 2B , the vertical thickness TH1 of the capacitor 700 may be less than the vertical thickness of the third redistribution layer 400R, and may even be less than one of the dielectric layers D11-D4 of the dielectric layer 400D (eg, Figure 2B Therefore, the capacitor 700 may be embedded in one of the dielectric layers D11-D4 such that the vertical thickness TH1 of the capacitor 700 is included in or within the vertical thickness TH2 of a single dielectric layer.

[0066] For example, the ISC (which may be capacitor 700) may take the form of a vertical cylindrical array including multiple capacitive paths between two or more connection terminals and have a very low profile, e.g., about 2.0×2.0×2.0 μm, while the DSC500D or LSC 500C (which may be MLCC) has dimensions of hundreds of microns (μm), e.g., about 1.0×0.5×0.35 mm for a 0402 MLCC. While the vertical thickness of the ISC in the D3 direction may be about 2.0 microns, each of the dielectric layers D11-D4 of the dielectric layer 400D may have a vertical thickness in the range of 3.0 microns to 10.0 microns in the D3 direction. In addition, the ISC may have a high capacitance density similar to that of an MLCC. For example, the ISC may have a capacitance of hundreds of nF / mm 2 Capacitance value, for example 1100nF / mm 2 .

[0067] Due to the low profile and high capacitance density described above, the capacitor 700 can be embedded inside the third redistribution layer 400R at a desired location to serve the same functional purpose of the DSC 500D and the LSC 500L.

[0068] For example, the capacitor 700 may be formed in the upper portion of the third redistribution layer 400R disposed close to the semiconductor chips 300A and 300B. When disposed close to the semiconductor chips 300A and 300B, the capacitor 700 may have better performance in controlling the impedance and noise applied to the semiconductor chips 300A and 300B than the DSC 500D and the LSC 500L disposed far from the semiconductor chips 300A and 300B. As another example, the capacitor 700 may be formed in the third redistribution layer 400R on the upper portion of the power wiring trace W1 of the wiring trace 400W and connected thereto, and connected to the wiring trace in the second redistribution layer 200U just below the semiconductor chips 300A and 300B.

[0069] By placing capacitor 700 closer to the load (i.e., semiconductor chips 300A and 300B), the length of the entire wiring trace between capacitor 700 and the load can be reduced to provide a low impedance path for high-frequency current, and parasitic inductance can be minimized. In addition, faster and more efficient power delivery to the load can be achieved.

[0070] While the DSC 500D and the LSC 500L are provided on the package substrate 100 for the same purpose, the capacitor 700 in the interconnect package 400 can provide at least additional impedance and noise control performance to the semiconductor package 20. However, depending on design choice, the semiconductor package 20 can omit at least one of the DSC 500D and the LSC 500L because the capacitor 700 is included in the interconnect package 400 directly below the semiconductor chips 300A and 300B.

[0071] In addition, since the semiconductor package 20 can omit at least one of the DSC 500D and the LSC 500L, the overall size of the semiconductor package 20 can be reduced. For example, when the external terminals 100T (which may be solder balls or bumps) may form a ball grid array (BGA) of the semiconductor package 20, the removal of the external terminals 100T and the LSC 500L may reduce the overall size of the semiconductor package 20. Figure 2A The LSC 500L shown may be formed between the external terminals 100T on the bottom surface of the package substrate 100, which may reduce constraints on package design including a ball design of a BGA for the semiconductor package 20. For example, the external terminals 100T may be formed with smaller-sized solder balls or bumps at smaller pitches and profiles, which helps reduce the overall stack height of the semiconductor package 20.

[0072] The above-described embodiment of embedding capacitor 700 in interconnect package 400 can also be applied to a land grid array (LGA) semiconductor package, i.e., a semiconductor package 20 without external terminals 100T (solder balls or bumps). In this case, eliminating LSC 500L from the bottom surface of package substrate 100 can eliminate the need for a cavity inside an original equipment manufacturer (OEM) socket to improve structural integration with the OEM socket.

[0073] Meanwhile, the interconnect package 400 including the capacitor 700 may not be limited to the above-mentioned and Figure 2A According to an embodiment, the interconnect package 400 may include one or more active devices, such as transistors. For example, Figure 2B It is shown that transistors TR such as field effect transistors can be formed in the support layer 400S and can be connected to the wiring trace 400W. In this case, the capacitor 700 can also be used to reduce the impedance and noise applied to these transistors. In addition, the support layer 400S that structurally supports the third redistribution layer 400R can be configured differently as described below.

[0074] Figure 3A shows a schematic cross-sectional view of a semiconductor package including an interconnect package and a decoupling capacitor according to yet another embodiment, Figure 3B According to an embodiment, the Figure 3AA schematic cross-sectional view of an interconnect package in a semiconductor package is shown.

[0075] Reference Figure 3A and Figure 3B , the semiconductor package 30 may include the same structural elements under the same structural configuration as the semiconductor package 20, except that the interconnect package 400 may have one or more second through vias 400V formed therein. Therefore, the differences between the semiconductor package 30 and the semiconductor package 20 may be described below, and a repeated description thereof may be omitted.

[0076] The second through via 400V may be formed to penetrate the support layer 400S and the die attach film 400F to connect the wiring trace 400W in the third redistribution layer 400R to the wiring trace formed in the first redistribution layer 200L. The second through via 400V may be connected to the capacitor 700 to extend the impedance control function of the capacitor 700 to other circuit elements in the semiconductor package 30, including the above-mentioned Figure 2B The active device (transistor TR) of the embedded interconnect package 400 can be described in the figure. Therefore, the second through-via 400V can connect the capacitor to the active device. The second through-via 400V can be formed of the same or similar metal as the core via 100V and the first through-via 200V.

[0077] In the above-described embodiments, each of the semiconductor packages 20 and 30 is described as including two interconnect packages 400 to connect the three semiconductor chips 300A-300C, and each interconnect package 400 is described as including one capacitor 700 embedded therein, which may be an ISC. However, the present disclosure is not limited thereto. According to embodiments, more or less than three semiconductor chips may be disposed on the redistribution substrate 200 in each of the semiconductor packages 20 and 30, and each interconnect package 400 may include a plurality of capacitors embedded therein for the same or similar purposes described above for the capacitors 700 in the interconnect package 400.

[0078] In the above-described embodiment, one interconnect package, namely, the interconnect package 400, is formed below the boundary of two adjacent semiconductor chips 300A and 300B or 300B and 300C in each of the semiconductor packages 20 and 30. However, one or more additional interconnect packages may be formed below the boundary to provide an additional signal routing path between the two semiconductor chips in the semiconductor package 20 or 30. In addition, according to an embodiment, one or more capacitors such as the capacitor 700 may be formed in the interconnect package 400 to further reduce the impedance and noise applied to the two semiconductor chips.

[0079] In the above-described embodiments, one redistribution substrate, i.e., the redistribution substrate 200 having the interconnection package 400 including the capacitor 700, is formed in each of the semiconductor packages 20 and 30. However, according to embodiments, one or more additional redistribution substrates with or without the interconnection package 400 may be formed above, below, or on the side of the redistribution substrate 200 in the semiconductor package 20 or 30 to provide at least one additional redistribution path to the semiconductor chips 300A-300C. For example, one of the semiconductor chips 300A-300C may be connected to another circuit element or semiconductor chip in another semiconductor package or device through an additional redistribution path provided by the additional redistribution substrate in the semiconductor package 20 or 30. Here, the additional redistribution path may be a power delivery path or a signal routing path from or to the semiconductor package 20 or 30.

[0080] In the above-described embodiments, the interconnection package 400 is formed in the redistribution substrate 200 below the semiconductor chips 300A-300C and above the package substrate 100. However, according to an embodiment, at least one of the interconnection packages 400 may be formed above the semiconductor chips 300A-300C with a corresponding connection structure therebetween, and the capacitor 700 may also be embedded in the at least one interconnection package 400. When the interconnection package 400 is formed above the semiconductor chips 300A-300C, the third redistribution layer 400R may be formed below the support layer 400S, so that the capacitor 700 formed on the wiring trace 400W in the third redistribution layer 400R may be disposed close to the semiconductor chips 300A-300C.

[0081] Below, refer to Figure 4 and Figures 5A-5F A method of manufacturing a semiconductor package including an interconnect package and a decoupling capacitor therein according to an embodiment is described.

[0082] Figure 4 A flow chart of a method of manufacturing a semiconductor package including an interconnect package and a decoupling capacitor therein according to an embodiment is shown. Figures 5A-5F According to an embodiment, the Figure 4 The flowchart shown is an intermediate semiconductor package after the corresponding steps of manufacturing a semiconductor package including an interconnect package and a decoupling capacitor therein.

[0083] The semiconductor package manufactured in the following method can be Figure 2A and Figure 2B The semiconductor packages 20 shown are identical or corresponding, and therefore, repeated descriptions may be omitted, and the same reference numerals are used below to refer to structural elements of the semiconductor package 20 .

[0084] In step S10, a first redistribution layer 200L may be disposed on the carrier substrate 101, and an interconnection package 400 and a first through-via 200V may be formed on the first redistribution layer 200L, as shown in FIG. Figure 5A shown.

[0085] The first redistribution layer 200L, which may include one or more dielectric layers and a plurality of wiring traces embedded therein, may be bonded to the carrier substrate 101 by adhesive bonding using, for example, an epoxy-based adhesive, but is not limited thereto. When the first redistribution layer 200L is formed of a plurality of dielectric layers, the dielectric layers may be vertically stacked one after another, and wiring traces having line portions and via portions may be formed across the dielectric layers and isolated from each other.

[0086] The first through vias 200V may be formed by, for example, a first photolithography / masking / etching / deposition operation including electroplating and connected to wiring traces in the first redistribution layer 200L, and the interconnection packages 400 may be disposed laterally between the first through vias 200V over the first redistribution layer 200L. Each interconnection package 400 may be disposed laterally between the first through vias 200V at a position over which a boundary of two semiconductor chips to be connected to each other through the interconnection package is located.

[0087] Similar to the bonding operation for forming the first redistribution layer 200L on the carrier substrate 101, the interconnection package 400 (each of which may include the support layer 400S and the third redistribution layer 400R on the die attach film 400F) may be bonded to the first redistribution layer 200L by adhesive bonding using, for example, an epoxy-based adhesive. The third redistribution layer 400R may include a dielectric layer 400D and a wiring trace 400W embedded in the dielectric layer 400D. In addition, the third redistribution layer 400R may include a capacitor 700 on an upper portion thereof (e.g., an upper portion of the wiring trace 400W in the third redistribution layer 400R).

[0088] In step 20, the intermediate semiconductor package obtained in the previous step may be overmolded so that the space between the first through via 200V and the interconnection package 400 is filled with epoxy resin, and may be planarized so that the top surfaces of the first mold layer 200M, the first through via 200V, and the interconnection package 400 may be horizontally aligned or coplanar with each other. Figure 5B .

[0089] In step 30, the second redistribution layer 200U may be disposed on the intermediate semiconductor package obtained in the previous step by adhesive bonding, for example, using an epoxy-based adhesive, thereby completing the redistribution substrate 200. Furthermore, upper connection terminals 300T may be formed on the second redistribution layer 200U by a second photolithography / masking / etching / deposition operation, for example, including electroplating, and the upper connection terminals 300T may be overmolded by, for example, epoxy resin to form a second bottom fill layer 300F that isolates the upper connection terminals 300T from each other. The upper connection terminals 300T and the second bottom fill layer 300F may be planarized so that top surfaces of the upper connection terminals 300T and the second bottom fill layer 300F may be horizontally aligned or coplanar with each other. See FIG. Figure 5C .

[0090] Similar to the first redistribution layer 200L, the second redistribution layer 200U may also include one or more dielectric layers and a plurality of wiring traces embedded in the one or more dielectric layers. The second redistribution layer 200U may be formed so that the wiring traces included therein are respectively connected to the first through-via 200V and the wiring traces 400W of each interconnect package 400. In addition, the upper connection terminals 300T may be respectively connected to the wiring traces included in the second redistribution layer 200U.

[0091] In step S40, the semiconductor chips 300A-300C may be respectively placed on and connected to the upper connection terminals 300T, and overmolded using, for example, epoxy resin, so that a second mold layer 300M may be formed between the semiconductor chips 300A-300C for lateral isolation thereof. Figure 5D .

[0092] The semiconductor chips 300A and 300C may be high bandwidth memories (HBM), and the semiconductor chip 300B may be a system on chip (SoC), but are not limited thereto.

[0093] In step S50, the carrier substrate 101 may be removed by, for example, mechanical grinding, and lower connection terminals 200T may be formed on the bottom surface of the first redistribution layer 200L by, for example, welding, so that the wiring traces in the first redistribution layer 200L are respectively connected to the lower connection terminals 200T. Figure 5E .

[0094] In step S60, the intermediate semiconductor package obtained in the previous step may be attached to the package substrate 100 through the lower connection terminals 200T (which may be solder balls or bumps), and the lower connection terminals 200T may be molded by the first bottom filling layer 200F to be isolated from each other. Surface mounting technology (SMT) may be applied to attach the intermediate semiconductor package to the package substrate 100 which may include the substrate core 100C, the lower buildup layer 100L, and the upper buildup layer 100U. See Fig. 5F .

[0095] The lower connection terminal 200T may be located above and connected to the core via 100V included in the package substrate 100 , so that the lower connection terminal 200T may be connected to the external terminal 100T formed on the bottom surface of the package substrate 100 .

[0096] Furthermore, the LSC 500L and the DSC 500D may be integrated into the packaging substrate 100 , and a stiffener 600 may be formed on a top surface of a perimeter of the packaging substrate 100 to prevent warping of the packaging substrate 100 , which may occur at least during a subsequent packaging process.

[0097] Figure 6 The present invention includes Figure 2A-2B and / or Figure 3A-3B A schematic diagram of at least one electronic device in which a semiconductor package is shown.

[0098] Reference Figure 6 The electronic device 1000 may include a printed circuit board (PCB) or motherboard 1010 on which a plurality of semiconductor packages 1011 - 1015 are mounted. The electronic device 1000 may also include a plurality of other components 1020 .

[0099] The semiconductor package 1011 may include multiple chips, such as SoC and memory chips. The SoC may include at least one of a CPU, a GPU, an AI module, a modem, one or more memory units, a power management unit, etc. to control the overall operation of the electronic device 1000. The memory chip included in the semiconductor package 1011 may be one or more of a flash memory, a static random access memory (SRAM), a read-only memory (ROM), etc. Other semiconductor packages 1012, 1013, 1014, and 1015 may include a dynamic random access memory (DRAM) chip, various other processor chips, a communication chip, and an interface chip, respectively. The communication chip included in the semiconductor package 1014 may be configured to also perform wireless or wired communication functions associated with the SoC. At least one of the semiconductor packages 1011-1015 may be composed of Figure 2A The semiconductor package 20 or Figure 3AThe semiconductor package 30 shown is implemented.

[0100] Other components 1020 included in the electronic device 1000 may include a storage device, a camera module, a speaker, a microphone, a display, a battery, etc. The storage device may be configured to store user data. The storage device may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc. The display may be implemented to display data processed by the SoC and / or receive data through a touch screen panel of the display.

[0101] The foregoing is a description of exemplary embodiments and is not to be construed as limiting the present disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the above-described embodiments without substantially departing from the present disclosure.

Claims

1. A semiconductor device, comprising: An interconnect package comprising at least one dielectric layer and at least one first wiring trace formed in the at least one dielectric layer and configured to connect a plurality of semiconductor chips through the at least one first wiring trace, Wherein, the interconnect package further comprises a capacitor on the at least one first wiring trace, the capacitor being connected to the at least one first wiring trace.

2. The semiconductor device according to claim 1, wherein The semiconductor chip is disposed over the interconnect package in a first direction.

3. The semiconductor device according to claim 1, further comprising a redistribution substrate, the interconnect package being included in the redistribution substrate, and in, In a second direction intersecting the first direction, the redistribution substrate has a greater lateral width than the interconnect package.

4. The semiconductor device according to claim 1, further comprising a redistribution substrate, the interconnect package being included in the redistribution substrate, in, The semiconductor chip is arranged above the redistribution substrate in a first direction, wherein the redistribution substrate comprises at least one redistribution layer, at least one second wiring trace is formed in the at least one redistribution layer, and Wherein, the at least one second wiring trace connects the at least one first wiring trace to the semiconductor chip.

5. The semiconductor device according to claim 4, further comprising a packaging substrate disposed below the redistribution substrate, in, The package substrate includes a plurality of connection structures therein and a plurality of connection terminals on a first surface and a second surface thereof, the second surface being opposite to the first surface. Wherein, the connection structures are respectively connected to the connection terminals, and Wherein, at least one of the connection terminals is connected to the at least one first wiring trace through the at least one second wiring trace.

6. The semiconductor device according to claim 5, further comprising at least one additional capacitor, the at least one additional capacitor being on the first surface or the second surface of the package substrate, in, The at least one additional capacitor has a larger size than the capacitor in the interconnect package.

7. The semiconductor device according to claim 1, wherein The semiconductor chip is arranged above the interconnect package in a first direction, The capacitor is disposed in an upper portion of the interconnect package, the upper portion being closer to the semiconductor chip than a lower portion of the interconnect package.

8. The semiconductor device according to claim 1, wherein The at least one dielectric layer comprises a plurality of dielectric layers, and Wherein, in the first direction, the thickness of the capacitor is less than the thickness of one of the plurality of dielectric layers.

9. The semiconductor device according to claim 1, wherein: The at least one first routing trace comprises: a power wiring trace on which the capacitor is disposed, the power wiring trace being configured to connect at least one of the semiconductor chips to a voltage source; and A signal wiring trace is configured to connect the semiconductor chip.

10. The semiconductor device according to claim 1, further comprising: the semiconductor chip; a redistribution substrate, below the semiconductor chip in a first direction, the redistribution substrate including the interconnect package therein; as well as A packaging substrate is below the redistribution substrate in the first direction, and the packaging substrate is connected to the redistribution substrate.

11. The semiconductor device according to claim 10, wherein: The interconnect package further comprises a support layer, the at least one dielectric layer being disposed on the support layer, Wherein, the support layer comprises at least one of silicon, ceramic and glass, and Therein, at least one transistor is included in the supporting layer.

12. The semiconductor device according to claim 11, wherein The interconnect package further includes at least one through via formed in the support layer, and Wherein, the at least one through via connects the capacitor to the at least one transistor.

13. An electronic device comprising: A die stack comprising at least two semiconductor chips; an interconnect package disposed below the die stack in a first direction and connecting the semiconductor chips; as well as a capacitor disposed inside the interconnect package and connected to at least one of the semiconductor chips and configured to be connected to a voltage source, Wherein, in a second direction intersecting the first direction, the interconnect package has a smaller width than the die stack.

14. The electronic device according to claim 13, wherein: The interconnect package comprises: a power wiring trace connected to the capacitor; A signal wiring track connects the semiconductor chip.

15. The electronic device according to claim 13, wherein: The interconnect package is disposed below a boundary of the semiconductor chip in the first direction.

16. The electronic device according to claim 13, wherein: The interconnect package comprises: a dielectric layer in which the capacitor is disposed; and A support layer is provided below the dielectric layer, the support layer including at least one transistor connected to the capacitor.

17. An electronic system comprising: a substrate including a plurality of connection terminals on at least one of a first surface and a second surface thereof, the second surface being opposite to the first surface; as well as at least one semiconductor package including a plurality of semiconductor chips and at least one interconnect package, wherein at least one of the semiconductor chips is connected to at least one of the connection terminals of the substrate, Wherein, the at least one interconnect package comprises: at least one dielectric layer; at least one first wiring trace included in the at least one dielectric layer and connecting the semiconductor chip; and At least one capacitor is connected to the at least one first wiring trace.

18. The electronic system according to claim 17, wherein: The semiconductor chip includes a system on chip and a memory chip.

19. The electronic system according to claim 17, wherein: The at least one first routing trace comprises: a power routing trace connected to the at least one capacitor; and A signal wiring track connects the semiconductor chip.

20. The electronic system according to claim 17, wherein: The at least one capacitor is configured to be connected to a voltage source.

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