Semiconductor packaging structure and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor packaging structure and a forming method thereof. The semiconductor packaging structure comprises a substrate, a first chip and a second chip. The substrate comprises a first groove, a second groove and a substrate through hole. The first groove is formed in the front face of the substrate, the second groove is formed in the back face of the substrate, and the substrate through holes are formed in the outer sides of the first groove and the second groove. The first chip is implanted in the first groove, and the second chip is implanted in the second groove. And the first chip and the second chip are electrically connected to the corresponding substrate through holes respectively and are in communication interconnection through the substrate through holes.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a semiconductor package structure and a method for forming the same. Background Art

[0002] Three-dimensional chip packaging technology is to stack two or more chips vertically in the same packaging structure. It improves many chip performances, such as size, weight, speed, output and energy consumption. However, there are still areas that can be optimized in the three-dimensional chip packaging of related technologies, and it is necessary to further improve product performance and save costs. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a semiconductor packaging structure and a method for forming the same, which can improve product performance and save costs.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides a semiconductor packaging structure, which includes: a substrate, the substrate including a first groove, a second groove and a substrate through hole; the first groove is formed on the front side of the substrate, the second groove is formed on the back side of the substrate, and the substrate through hole is located on the outside of the first groove and the second groove; a first chip is implanted in the first groove; a second chip is implanted in the second groove; the first chip and the second chip are respectively electrically connected to the corresponding substrate through holes, and are communicated and interconnected through the substrate through holes.

[0006] In some embodiments, the semiconductor packaging structure also includes: a first redistribution layer and a second redistribution layer; the first redistribution layer is located on the front side of the substrate; the first chip is electrically connected to the corresponding substrate through-hole through the first redistribution layer; the second redistribution layer is located on the back side of the substrate; the second chip is electrically connected to the corresponding substrate through-hole through the second redistribution layer.

[0007] In some embodiments, the front side of the first chip is oriented in the same direction as the front side of the substrate and is electrically connected to the first redistribution layer through conductive bumps; the front side of the second chip is oriented in the same direction as the back side of the substrate and is electrically connected to the second redistribution layer through conductive bumps.

[0008] In some embodiments, a thickness between a bottom surface of the first groove and a bottom surface of the second groove is greater than one quarter of a thickness of the first chip or the second chip, and less than one third of a thickness of the first chip or the second chip.

[0009] In some embodiments, projections of the first groove and the second groove along the vertical direction overlap with each other; projections of the first chip and the second chip along the vertical direction overlap with each other.

[0010] In some embodiments, the first chip is bonded to the bottom surface of the first groove via an adhesive film; and the second chip is bonded to the bottom surface of the second groove via an adhesive film.

[0011] In some embodiments, an insulating layer is filled between an inner wall of the first groove and a side wall of the first chip, and between an inner wall of the second groove and a side wall of the second chip.

[0012] In some embodiments, there are multiple substrates; the multiple substrates are stacked along the vertical direction; plastic packaging materials are filled between adjacent substrates; and the adjacent chips located in different substrates are bonded to each other and electrically connected.

[0013] In some embodiments, the adhesive film and the molding material both include: resin and filler; wherein the filler is silicon oxide or aluminum oxide.

[0014] In some embodiments, the filler content of the molding material is greater than the filler content of the adhesive film; and the filler volume of the molding material is smaller than the filler volume of the adhesive film.

[0015] The present disclosure also provides a method for forming a semiconductor packaging structure, the method comprising: providing a substrate; etching the front side of the substrate to form a first groove; implanting a first chip into the first groove; forming a substrate through hole in the substrate; the substrate through hole vertically penetrates the substrate and is located outside the first groove; etching the back side of the substrate to form a second groove; implanting a second chip into the second groove; electrically connecting the first chip and the second chip to the corresponding substrate through holes, respectively; the first chip and the second chip are communicatively interconnected through the substrate through holes.

[0016] In some embodiments, the first chip and the second chip are electrically connected to the corresponding substrate through-holes, respectively, including: forming a first redistribution layer on the front side of the substrate to electrically connect the first chip to one end of the corresponding substrate through-hole; thinning the back side of the substrate to expose the other end of the substrate through-hole; forming a second redistribution layer on the back side of the substrate to electrically connect the second chip to the other end of the corresponding substrate through-hole.

[0017] In some embodiments, implanting the first chip into the first groove includes: bonding the first chip to the bottom surface of the first groove through an adhesive film; filling an insulating layer between the inner wall of the first groove and the side wall of the first chip;

[0018] In some embodiments, implanting the second chip into the second groove includes: bonding the second chip to the bottom surface of the second groove through an adhesive film; and filling an insulating layer between the inner wall of the second groove and the side wall of the second chip.

[0019] In some embodiments, after the first chip and the second chip are electrically connected to the corresponding substrate through holes, respectively, the formation method further includes: performing a slicing process on the substrate; hot-pressing bonding the substrate to the base plate; wherein the position of the hot-pressing bonding is in accordance with the position of the substrate through holes; and forming a plastic encapsulation material surrounding the substrate through an injection molding process.

[0020] In some embodiments, there are multiple substrates; thermally pressing and bonding the substrates to the baseplate includes: thermally pressing and bonding the first substrate to the baseplate; stacking the remaining chips on the first substrate in sequence, and thermally pressing and bonding adjacent substrates.

[0021] It can be seen that the embodiment of the present disclosure provides a semiconductor packaging structure and a method for forming the same, wherein the semiconductor packaging structure includes: a substrate, a first chip and a second chip. The substrate includes a first groove, a second groove and a substrate through hole. The first groove is formed on the front side of the substrate, the second groove is formed on the back side of the substrate, and the substrate through hole is located outside the first groove and the second groove. The first chip is implanted in the first groove, and the second chip is implanted in the second groove. The first chip and the second chip are electrically connected to the corresponding substrate through holes, respectively, and are interconnected through the substrate through holes. In this way, the first chip and the second chip realize vertical communication interconnection (i.e., three-dimensional packaging interconnection) through the substrate through holes, that is, communication interconnection between chips is realized without forming through holes through the chips. Therefore, on the one hand, there is no need to reserve area for the through holes and the KOZ (exclusion zone) near the through holes in the chip, which can reduce the size of the chip and increase the DPW (number of grains that can be cut on a wafer); on the other hand, the process can be simplified and costs can be saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 1 ;

[0023] Figure 2 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 2 ;

[0024] Figure 3 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 3 ;

[0025] Figure 4 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 4 ;

[0026] Figure 5 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 5 ;

[0027] Figure 6 The process of forming a semiconductor packaging structure provided by the embodiment of the present disclosure Figure 1 ;

[0028] Figure 7 The process of forming a semiconductor packaging structure provided by the embodiment of the present disclosure Figure 2 ;

[0029] Figure 8 The process of forming a semiconductor packaging structure provided by the embodiment of the present disclosure Figure 3 ;

[0030] Fig. 9 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 1 ;

[0031] Fig.10 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 2 ;

[0032] Fig.11 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 3 ;

[0033] Fig.12 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 4 ;

[0034] Fig.13 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 5 ;

[0035] Fig.14 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 6 ;

[0036] Fig.15 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 7;

[0037] Fig.16 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 8 ;

[0038] Fig.17 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 9 ;

[0039] Fig.18 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 10 . DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0041] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0044] The following are explanations of some terms in the embodiments of the present disclosure:

[0045] RDL (Re-distributed Layer): A wiring pattern formed on the chip surface that rearranges the chip's I / O ports.

[0046] TSV (Through Silicon Via): A structure that uses vertical through holes for electrical connection.

[0047] KOZ (Keep Out Zone): An area close to a semiconductor structure. To avoid interference, no other semiconductor structures can be set in the exclusion zone.

[0048] DPW (Die Per Wafer): refers to the number of die that can be cut from each wafer.

[0049] FO (Fan-out): A packaging method in which the solder joint setting range can exceed the area of ​​the die, providing more I / O solder joints.

[0050] Figure 1 is an optional structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure, Figure 1 is a cross-sectional view. Figure 1 As shown, the semiconductor package structure includes: a substrate 10 , a first chip 201 and a second chip 202 .

[0051] refer to Figure 1 The substrate 10 includes a first groove 101, a second groove 102 and a substrate through hole 11, wherein the first groove 101 is formed on the front side of the substrate 10, the second groove 102 is formed on the back side of the substrate 10, and the substrate through hole 11 is located outside the first groove 101 and the second groove 102. The first chip 201 is implanted in the first groove 101, and the second chip 202 is implanted in the second groove 102. The first chip 201 and the second chip 202 are electrically connected to the corresponding substrate through holes 11, respectively, and are communicated and interconnected through the substrate through holes 11.

[0052] In the embodiments of the present disclosure, reference Figure 1 The substrate 10 may be made of a semiconductor material, such as a silicon substrate. Accordingly, the substrate through hole 11 may be a TSV. The substrate through hole 11 may be filled with a conductive material such as copper, tungsten or polysilicon to interconnect the first chip 201 and the second chip 202.

[0053] In the disclosed embodiment, the semiconductor material used for the substrate 10 can be consistent with the semiconductor material used for the chips (i.e., the first chip 201 and the second chip 202). In this way, the stress caused by the different CTEs (coefficient of thermal expansion) between the structures can be eliminated, thereby avoiding warpage.

[0054] In the present disclosure, continue to refer to Figure 1The first groove 101 and the second groove 102 are etched on the front and back of the substrate 10, respectively. Then, the first chip 201 is implanted in the first groove 101, and the second chip 202 is implanted in the second groove 102. The substrate through hole 11 is located outside the first groove 101 and the second groove 102, that is, the substrate through hole 11 is located outside the first chip 201 and the second chip 202, and no through hole is formed inside the first chip 201 and the second chip 202.

[0055] It should be noted that if a through hole is formed in the chip, especially in the packaging process, the through hole in the chip needs to be exposed from the back of the chip, which will bring higher costs and more complicated processes. At the same time, if a through hole is formed in the chip, then it is necessary to reserve an area for the through hole and the KOZ near the through hole in the chip, which occupies more chip area and is not conducive to reducing the size of the chip.

[0056] It can be understood that in the embodiment of the present disclosure, the first chip 201 and the second chip 202 realize vertical communication interconnection (i.e., three-dimensional packaging interconnection) through the substrate through hole 11. In this way, communication interconnection between chips can be realized without forming through holes through the chips; thus, on the one hand, there is no need to reserve area for the through holes and the KOZ near the through holes in the chip, which can reduce the size of the chip and improve the DPW; on the other hand, it can simplify the process and save costs.

[0057] At the same time, if a TSV structure is manufactured in the first chip 201 and the second chip 202, each chip needs to undergo a TSV exposure process. However, the embodiment of the present disclosure only requires a TSV exposure process on the back side of the substrate, which reduces the TSV exposure process requirement by 50%, simplifies the process, and can improve product yield.

[0058] In some embodiments of the present disclosure, reference Figure 1 The semiconductor package structure further includes: a first redistribution layer 301 and a second redistribution layer 302. The first redistribution layer 301 is located on the front side of the substrate 10; the first chip 201 is electrically connected to the corresponding substrate through hole 11 through the first redistribution layer 301. The second redistribution layer 302 is located on the back side of the substrate 10; the second chip 202 is electrically connected to the corresponding substrate through hole 11 through the second redistribution layer 302.

[0059] Figure 2 is an optional structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure, Figure 2 This is a top view. Figure 2 A wiring pattern of the first redistribution layer 301 is illustrated.

[0060] refer to Figure 2The first redistribution layer 301 electrically connects the port on the first chip 201 to the corresponding substrate through hole 11. The wiring pattern of the second redistribution layer 302 can be referred to Figure 2 The wiring pattern of the first redistribution layer 301 can be understood.

[0061] It should be noted that in Figure 2 In the embodiment, the first redistribution layer 301 connects each port on the first chip 201 to the substrate through hole 11 on the same side. However, the wiring pattern of the first redistribution layer 301 can be adjusted as needed and is not limited to Figure 2 The wiring pattern shown, for example, the first redistribution layer 301 connects each port on the first chip 201 to the substrate through-hole 11 on the opposite side, which is not limited here.

[0062] In the present disclosure, Figure 1 and Figure 3 As shown, the first chip 201 is connected to the substrate through hole 11 through the first redistribution layer 301, and the second chip 202 is connected to the substrate through hole 11 through the second redistribution layer 302, thereby forming a signal interconnection. Since the first redistribution layer 301 connected to the first chip 201 extends to the outside of the first chip 201, and the first redistribution layer 302 connected to the second chip 202 extends to the outside of the second chip 202. In this way, the spacing between the substrate through holes 11 is increased, thereby reducing the impact of signal crosstalk. At the same time, since the substrate through hole 11 is also far away from the first chip 201 and the second chip 202, the heat generated by the substrate through hole 11 has little effect on the chip.

[0063] It can be understood that each chip is electrically connected to the corresponding substrate through-hole in the substrate through the redistribution layer to realize the communication interconnection of each chip. In this way, the communication interconnection between chips can be realized without forming through-holes through the chips; thus, on the one hand, there is no need to reserve area for through-holes and KOZ near through-holes in the chip, which can reduce the size of the chip and improve DPW; on the other hand, there is no need to implement the relevant process of forming through-holes in the chip, thereby simplifying the process and saving costs.

[0064] At the same time, by using the rewiring layer, the ports on the chip can be rearranged, so the ports on the chip can be designed more closely, thereby reducing the size of the chip.

[0065] In some embodiments of the present disclosure, reference Figure 1 The front side of the first chip 201 is aligned with the front side of the substrate 10 and is electrically connected to the first redistribution layer 301 via a conductive bump 401. The front side of the second chip 202 is aligned with the back side of the substrate 10 and is electrically connected to the second redistribution layer 302 via a conductive bump (or pad) 401.

[0066] In the present disclosure, Figure 1 and Figure 3 As shown, the first groove 101 and the second groove 102 are arranged opposite to each other, the first chip 201 is arranged in the first groove 101 with the front side (circuit layer) facing upward, and the second chip 202 is arranged in the second groove 102 with the front side (circuit layer) facing downward. In this way, the circuit layers on the first chip 201 and the second chip 202 are far apart, so that the signal crosstalk between the first chip 201 and the second chip 202 can be reduced.

[0067] In some embodiments of the present disclosure, reference Figure 1 The thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 is greater than one quarter of the thickness of the first chip 201 or the second chip 202 , and less than one third of the thickness of the first chip 201 or the second chip 202 .

[0068] In the embodiment of the present disclosure, the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 is the thickness of the thinnest part of the material in the middle of the substrate 10. This part of the material is adhered to the bottom of the first chip 201 and the bottom of the second chip 202. Therefore, this part of the material cannot be too thin, otherwise there is a risk of collapse; at the same time, this part of the material cannot be too thick, otherwise the size of the substrate 10 in the vertical direction will be unnecessarily increased, thereby causing the size of the entire semiconductor package structure in the vertical direction to be increased.

[0069] It is understandable that in the embodiment of the present disclosure, the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 is set to be between one quarter and one third of the thickness of the first chip 201 or the second chip 202. In this way, the risk of collapse is avoided and the size of the semiconductor package structure in the vertical direction is kept small.

[0070] In some embodiments of the present disclosure, reference Figure 1 The projections of the first groove 101 and the second groove 102 along the vertical direction overlap each other. The projections of the first chip 201 and the second chip 202 along the vertical direction overlap each other. In this way, the area occupied by the first groove 101 and the second groove 102 on the substrate 10 can be minimized, thereby reducing the size of the substrate 10 and further reducing the size of the entire semiconductor package structure.

[0071] In some embodiments of the present disclosure, reference Figure 3 The first chip 201 is bonded to the bottom surface of the first groove through the adhesive film 501. The second chip 202 is bonded to the bottom surface of the second groove through the adhesive film 501.

[0072] In the embodiment of the present disclosure, the adhesive film 501 includes resin and filler, wherein the filler may be silicon oxide (SiO) or aluminum oxide (AlO). The adhesive film 501 has a heat insulation effect, so that the heat generated by the first chip 201 and the second chip 202 will not affect each other, thereby ensuring that the operating conditions of the first chip 201 and the second chip 202 are stable.

[0073] In some embodiments of the present disclosure, reference Figure 3 The space between the inner wall of the first groove and the side wall of the first chip 201, and the space between the inner wall of the second groove and the side wall of the second chip 202 are filled with an insulating layer 502. The insulating layer 502 may be made of polyimide (PI).

[0074] It is understandable that filling the insulating layer 502 outside the side walls of the first chip 201 and the second chip 202 can, on the one hand, avoid short circuits; on the other hand, can protect the first chip 201 and the second chip 202 from being affected by the stress of the substrate 10 .

[0075] like Figures 2 to 4 As shown, the first redistribution layer 301 is located on the insulating layer 502, that is, the first redistribution layer 301 extends on the insulating layer 502, and the two ends are respectively connected to the first chip 201 and the substrate through hole 11, so as to realize signal transmission. Figure 2 It can be seen that the first redistribution layer 301 has a large surface area, so the first redistribution layer 301 will also generate a lot of heat. Since the thermal conductivity of the insulating layer 502 is poor, the thermal conductivity of the molding material 503 is good (greater than the thermal conductivity of the insulating layer 502), and the first redistribution layer 301 is in direct contact with the molding material 503, the heat generated by the first redistribution layer 301 will be dissipated from the molding material 503, thereby reducing the impact of heat on the chip.

[0076] like Figure 4 As shown, in some embodiments, the material of the insulating layer 502 is, for example, polyimide, and the material of the molding material 503 is, for example, a molding material. Polyimide is formed by combining a resin material and a small amount of filler, and the molding material is formed by combining a resin material and a large amount of filler. The resin material has good fluidity, but poor thermal conductivity, so the molding material 503 has more fillers (silicon oxide) relative to the insulating layer 502, so that the molding material 503 has greater thermal conductivity. At the same time, since the gap between the first chip 201 and the side wall of the first groove 101 is small, only a few microns to more than ten microns, therefore, in order to better fix the first chip 201, a smaller filler can be added to the resin material, that is, the filler volume in the insulating layer 502 is smaller than the filler volume in the molding material 503, thereby increasing the fluidity of the insulating layer 502 and having better filling ability.

[0077] In some embodiments, reference Figure 3 , the first chip 201 and the second chip 202 can be chips of the same type, for example, both are dynamic random access memory chips (DRAM) and static random access memory chips (SRAM). In other embodiments, the first chip 201 and the second chip 202 can also be chips of different types, for example, the first chip 201 is a memory chip and the second chip 202 is a control chip. When the first chip 201 and the second chip 202 are chips of different types, the substrate through hole 11 can provide the same power signal to the two.

[0078] In some embodiments of the present disclosure, reference Figure 4 or Figure 5 In the semiconductor packaging structure, there are multiple substrates 10. Multiple substrates 10 are stacked along the vertical direction Z. Between adjacent substrates 10, a plastic encapsulation material 503 is filled. The adjacent chips located in different substrates 10 are bonded to each other and electrically connected.

[0079] It should be noted that Figure 4 and Figure 5 In the example, the number of substrates 10 is two. On this basis, more substrates 10 can be stacked. That is, the number of substrates 10 is not limited to two. The structure and connection relationship can refer to Figure 4 and Figure 5 .

[0080] In the embodiments of the present disclosure, reference Figure 4 , the chip 202 and the chip 203 are respectively located in two different substrates, and the chip 202 and the chip 203 are bonded to each other and electrically connected, wherein the bonding position is located at the position of the substrate through hole 11. At the same time, the chip 201 and the chip 202 are electrically connected through the corresponding substrate through hole 11, and the chip 203 and the chip 204 are also electrically connected through the corresponding substrate through hole 11. In this way, the chips 201, 202, 203 and 204 can all achieve communication interconnection.

[0081] In the embodiments of the present disclosure, reference Figure 5 , chip 202 and chip 203 are respectively located in two different substrates, and chip 202 and chip 203 are bonded to each other and electrically connected, wherein the bonding position is located at the position of conductive bump 401. At the same time, chip 201 and chip 202 are electrically connected through the corresponding substrate through hole 11, and chip 203 and chip 204 are also electrically connected through the corresponding substrate through hole 11. In this way, communication interconnection can be achieved between chips 201, 202, 203 and 204. Since chips 202 and 203 are relatively close to the conductive bump 401, the use of Figure 5The structure shown in the example can shorten the interconnection path, reduce loop resistance, and improve operating efficiency.

[0082] It can be understood that multiple substrates 10 are stacked and the chips in different substrates 10 are electrically connected to each other through bonding; at the same time, in each substrate 10, different chips are electrically connected through corresponding substrate through holes 11. In this way, three-dimensional packaging of multiple chips is achieved, and higher performance is obtained with a smaller packaging size.

[0083] At the same time, the bonding position can be located at the position of the substrate through hole 11, and the substrate through hole 11 is located on the outside of the chip (any one of the chips 201 to 204), that is, an FO type package is adopted, so that the setting range of the bonding solder joints is larger, and more solder joints can be set, which is more beneficial for chip design.

[0084] In some embodiments of the present disclosure, reference Figure 4 or Figure 5 The adhesive film 501 and the molding material 503 both include resin and filler, wherein the filler may be silicon oxide or aluminum oxide.

[0085] It should be noted that, in the adhesive film 501 and the molding material 503 , the resin is the basic material, and the filler is added into the basic material in a certain proportion.

[0086] In some embodiments of the present disclosure, the filler content of the molding material 503 is greater than the filler content of the adhesive film 501. The larger the filler content of the molding material 503, the smaller the resin content. Since the heat dissipation capacity of the resin is relatively poor, the heat dissipation capacity of the molding material 503 is relatively good. In this way, the semiconductor packaging structure can better dissipate heat.

[0087] In some embodiments of the present disclosure, the filling volume of the molding material 503 is smaller than the filling volume of the adhesive film 501. The smaller the filling volume, the better the fluidity of the material, and therefore, the molding material 503 has better fluidity. In this way, the molding material 503 can be better filled, and gaps due to inadequate filling can be avoided.

[0088] Figure 6 An optional flow chart of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 6 As shown, the method for forming a semiconductor package structure includes S101 to S107, which will be described in conjunction with each step.

[0089] It should be noted that Figures 9 to 18 The structure of a semiconductor package structure during the formation process is shown, which is used to describe and clearly illustrate the steps of a method for forming a semiconductor package structure.

[0090] S101. Provide a substrate.

[0091] In the embodiments of the present disclosure, reference Fig. 9 The substrate 10 may be made of a semiconductor material, such as a silicon substrate. The semiconductor material used in the substrate 10 may be consistent with the semiconductor material used in the subsequently implanted chip, so that the stress caused by the different CTEs between the structures can be eliminated, thereby avoiding warpage.

[0092] S102, etching the front surface of the substrate to form a first groove.

[0093] In the embodiments of the present disclosure, reference Fig. 9 and Fig.10 , etching can be performed on the front side of the substrate 10 to form a first groove 101. The position where the first groove 101 is formed can be the middle part of the front side of the substrate 10.

[0094] S103, implanting the first chip into the first groove.

[0095] In the embodiments of the present disclosure, reference Fig.10 and Fig.11 After the first groove 101 is formed, the first chip 201 may be implanted into the first groove 101. A gap may exist between the first chip 201 and the sidewall of the first groove 101.

[0096] S104, forming a substrate through hole in the substrate; the substrate through hole penetrates the substrate in a vertical direction and is located outside the first groove.

[0097] In the embodiments of the present disclosure, reference Fig.12 and Fig.13 After the first chip 201 is implanted, a substrate through hole 11 can be formed in the substrate 10. An opening 12 can be formed at the pad of the first chip 201 and at the corresponding position of the substrate through hole 11, and then the substrate through hole 11 can be formed. The substrate through hole 11 can be filled with conductive materials such as copper, tungsten or polysilicon to interconnect the various chips.

[0098] S105 , etching the back side of the substrate to form a second groove.

[0099] In the embodiments of the present disclosure, reference Fig.14 and Fig.15After completing the relevant processes on the front side of the substrate 10, the back side of the substrate 10 can be etched to form the second groove 102. The second groove 102 can be formed at the middle of the back side of the substrate 10, that is, the projections of the first groove 101 and the second groove 102 along the vertical direction Z can overlap with each other. In this way, the area occupied by the first groove 101 and the second groove 102 on the substrate 10 can be minimized, thereby reducing the size of the substrate 10 and further reducing the size of the entire semiconductor package structure.

[0100] In the embodiment of the present disclosure, during the process of etching to form the second groove 102, the etching cut-off position can be controlled, thereby controlling the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102. The thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 can be set to be greater than one quarter of the thickness of the first chip 201 or the second chip 202, and less than one third of the thickness of the first chip 201 or the second chip 202. In this way, the risk of collapse is avoided and the size of the semiconductor package structure in the vertical direction is ensured to be small.

[0101] S106 , implanting a second chip into the second groove.

[0102] In the embodiments of the present disclosure, reference Fig.15 and Fig.16 After the second groove 102 is formed, the second chip 202 may be implanted into the second groove 102. Accordingly, there may be a gap between the second chip 202 and the sidewall of the second groove 102.

[0103] S107 , electrically connecting the first chip and the second chip to corresponding substrate through holes respectively; the first chip and the second chip are interconnected and communicated through the substrate through holes.

[0104] In the embodiments of the present disclosure, reference Fig.16 The first chip 201 and the second chip 202 are electrically connected to the corresponding substrate through-holes 11, and communicate and interconnect through the substrate through-holes 11. In this way, communication and interconnection between chips can be achieved without forming through-holes through the chips; thus, on the one hand, it is not necessary to reserve an area for the through-holes and the KOZ near the through-holes in the chip, which can reduce the size of the chip and improve the DPW; on the other hand, it can simplify the process and save costs.

[0105] It should be noted that the first chip 201 and the second chip 202 are chips after packaging and thinning, and the thickness of the first chip 201 and the second chip 202 can be between 50-80 microns, for example, 60, 65, 70 microns. Therefore, the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 is relatively small, and can be between 15-20 microns, for example, 18 microns.

[0106] In some embodiments of the present disclosure, Figure 7 S201 to S203 shown are implemented Figure 6 S107 shown will be described in conjunction with each step.

[0107] S201 , forming a first redistribution layer on the front side of the substrate, and electrically connecting the first chip to one end of the corresponding substrate through hole.

[0108] In the embodiments of the present disclosure, reference Fig.13 , one end of the substrate through hole 11 is exposed on the front side of the substrate 10. Then, a first redistribution layer 301 can be formed on the front side of the substrate 10 to electrically connect the first chip 201 to one end of the corresponding substrate through hole 11. The first redistribution layer 301 is electrically connected to the pad of the first chip 201.

[0109] S202, performing a thinning process on the back side of the substrate to expose the other end of the substrate through hole.

[0110] In the embodiments of the present disclosure, reference Fig.13 and Fig.14 The back side of the substrate 10 may be thinned until the other end of the substrate through hole 11 is exposed on the back side of the substrate 10 .

[0111] S203 , forming a second redistribution layer on the back side of the substrate to electrically connect the second chip to the other end of the corresponding substrate through hole.

[0112] In the embodiments of the present disclosure, reference Fig.16 A second redistribution layer 302 may be formed on the back side of the substrate 10 to electrically connect the second chip 202 to the other end of the corresponding substrate through hole 11. The second redistribution layer 302 is electrically connected to the pad of the second chip 202.

[0113] It can be understood that each chip is electrically connected to the corresponding substrate through-hole in the substrate through the redistribution layer to realize the communication interconnection of each chip. In this way, the communication interconnection between chips can be realized without forming through-holes through the chips; thus, on the one hand, there is no need to reserve area for through-holes and KOZ near through-holes in the chip, which can reduce the size of the chip and improve DPW; on the other hand, there is no need to implement the relevant process of forming through-holes in the chip, thereby simplifying the process and saving costs.

[0114] At the same time, by using the rewiring layer, the ports on the chip can be rearranged, so the ports on the chip can be designed more closely, thereby reducing the size of the chip.

[0115] In some embodiments of the present disclosure, S301 to S302 can be used to implement Figure 6 S103 shown will be described in conjunction with each step.

[0116] S301, bonding the first chip to the bottom surface of the first groove through an adhesive film.

[0117] In the embodiments of the present disclosure, reference Fig.11 During the implantation of the first chip 201, the first chip 201 can be bonded to the bottom surface of the first groove 101 through the adhesive film 501. The adhesive film 501 includes resin and filler, wherein the filler can be silicon oxide (SiO) or aluminum oxide (AlO).

[0118] S302 , filling an insulating layer between the inner wall of the first groove and the side wall of the first chip.

[0119] In the embodiments of the present disclosure, reference Fig.11 and Fig.12 During the implantation of the first chip 201, an insulating layer 502 may be filled between the inner wall of the first groove 101 and the side wall of the first chip 201. The insulating layer 502 may be made of PI.

[0120] In some embodiments of the present disclosure, S303 to S304 can be used to implement Figure 6 S106 shown will be described in conjunction with each step.

[0121] S303, bonding the second chip to the bottom surface of the second groove through an adhesive film.

[0122] In the embodiments of the present disclosure, reference Fig.15 and 16 During the implantation of the second chip 202 , the second chip 202 may be bonded to the bottom surface of the second groove 102 by the adhesive film 501 .

[0123] It is understandable that the adhesive film 501 has a heat insulating effect, so that it can be ensured that the heat generated by the first chip 201 and the second chip 202 will not affect each other, thereby ensuring that the operating conditions of the first chip 201 and the second chip 202 are stable.

[0124] S304 , filling an insulating layer between the inner wall of the second groove and the side wall of the second chip.

[0125] In the embodiments of the present disclosure, reference Fig.15 and 16 During the implantation of the second chip 202 , an insulating layer 502 may be filled between the inner wall of the second groove 102 and the side wall of the second chip 202 .

[0126] It is understandable that filling the insulating layer 502 outside the side walls of the first chip 201 and the second chip 202 can, on the one hand, avoid short circuits; on the other hand, can protect the first chip 201 and the second chip 202 from being affected by the stress of the substrate 10 .

[0127] In some embodiments of the present disclosure, Figure 6 After S107 shown, the forming method further includes Figure 8 S108 to S110 shown will be described in conjunction with each step.

[0128] S108, performing a dicing process on the substrate.

[0129] S109, thermally pressing and bonding the substrate to the base; wherein the position of the thermal pressing and bonding is in accordance with the position of the through hole of the substrate.

[0130] S110, forming a plastic packaging material surrounding the substrate through an injection molding process.

[0131] In the embodiments of the present disclosure, reference Fig.17 After the various structures on the substrate 10 are formed, the substrate 10 can be diced to cut out the substrate 10. Then, the substrate 10 is thermally pressed (TCB) bonded to the base plate 60, wherein the position of the thermal compression bonding can be based on the position of the substrate through hole 11. Then, the plastic encapsulation material 503 surrounding the substrate 10 can be formed by injection molding.

[0132] In the present disclosure, continue to refer to Fig.17 The adhesive film 501 and the molding material 503 both include resin and filler, wherein the resin is the base material and the filler is added into the base material in a certain proportion. The filler may be silicon oxide or aluminum oxide.

[0133] In some embodiments of the present disclosure, the filler content of the molding material 503 is greater than the filler content of the adhesive film 501. The larger the filler content of the molding material 503, the smaller the resin content. Since the heat dissipation capacity of the resin is relatively poor, the heat dissipation capacity of the molding material 503 is relatively good. In this way, the semiconductor packaging structure can better dissipate heat.

[0134] In some embodiments of the present disclosure, the filling volume of the molding material 503 is smaller than the filling volume of the adhesive film 501. The smaller the filling volume, the better the fluidity of the material, and therefore, the molding material 503 has better fluidity. In this way, the molding material 503 can be better filled, and gaps due to inadequate filling can be avoided.

[0135] In some embodiments of the present disclosure, the number of substrates is multiple, which can be achieved through S401 to S402. Figure 8 S109 shown will be explained in combination with each step.

[0136] S401, thermally pressing and bonding the first substrate to the base plate.

[0137] S402, stacking the remaining chips on the first substrate in sequence, and thermally pressing and bonding adjacent substrates.

[0138] In the embodiments of the present disclosure, reference Fig.18 , the first substrate 10 (i.e. the substrate 10 at the bottom) can be thermocompressively bonded to the base plate 60. Then, the second substrate 10 can be stacked on the first substrate 10, and the second substrate 10 can be thermocompressively bonded to the first substrate 10, wherein the bonding position can be located at the position of the substrate through hole 11. By analogy, more substrates 10 can be stacked.

[0139] It can be understood that multiple substrates 10 are stacked and the chips in different substrates 10 are electrically connected to each other through bonding; at the same time, in each substrate 10, different chips are electrically connected through corresponding substrate through holes 11. In this way, three-dimensional packaging of multiple chips is achieved, and higher performance is obtained with a smaller packaging size.

[0140] At the same time, the bonding position can be located at the position of the substrate through hole 11, and the substrate through hole 11 is located on the outside of the chip (any one of the chips 201 to 204), that is, an FO type package is adopted, so that the setting range of the bonding solder joints is larger, and more solder joints can be set, which is more beneficial for chip design.

[0141] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0142] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0143] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: The semiconductor packaging structure comprises: A substrate, comprising a first groove, a second groove and a substrate through hole; the first groove is formed on the front side of the substrate, the second groove is formed on the back side of the substrate, and the substrate through hole is located outside the first groove and the second groove; A first chip is implanted in the first groove; The second chip is implanted in the second groove; the first chip and the second chip are electrically connected to the corresponding substrate through holes, respectively, and are interconnected through the substrate through holes.

2. The semiconductor package structure according to claim 1, wherein: The semiconductor package structure further includes: a first redistribution layer and a second redistribution layer; The first redistribution layer is located on the front side of the substrate; the first chip is electrically connected to the corresponding substrate through-hole through the first redistribution layer; The second redistribution layer is located on the back side of the substrate; the second chip is electrically connected to the corresponding substrate through-hole through the second redistribution layer.

3. The semiconductor package structure according to claim 2, characterized in that: The front side of the first chip is aligned with the front side of the substrate and is electrically connected to the first redistribution layer via a conductive bump; The front side of the second chip is aligned with the back side of the substrate and is electrically connected to the second redistribution layer via conductive bumps.

4. The semiconductor package structure according to claim 1, wherein: The thickness between the bottom surface of the first groove and the bottom surface of the second groove is greater than one quarter of the thickness of the first chip or the second chip, and less than one third of the thickness of the first chip or the second chip.

5. The semiconductor package structure according to claim 1, wherein: The projections of the first groove and the second groove in the vertical direction overlap with each other; The projections of the first chip and the second chip along the vertical direction overlap with each other.

6. The semiconductor package structure according to any one of claims 1 to 5, characterized in that: The first chip is bonded to the bottom surface of the first groove through an adhesive film; The second chip is bonded to the bottom surface of the second groove through an adhesive film.

7. The semiconductor package structure according to any one of claims 1 to 5, characterized in that: An insulating layer is filled between the inner wall of the first groove and the side wall of the first chip, and between the inner wall of the second groove and the side wall of the second chip.

8. The semiconductor package structure according to any one of claims 6, characterized in that: The number of the substrates is multiple; A plurality of the substrates are stacked along the vertical direction; and plastic packaging materials are filled between adjacent substrates; The adjacent chips located in different substrates are bonded to each other and electrically connected.

9. The semiconductor package structure according to claim 8, characterized in that: The adhesive film and the molding material both include resin and filler; wherein the filler is silicon oxide or aluminum oxide.

10. The semiconductor package structure according to claim 9, characterized in that: The filler content of the plastic encapsulation material is greater than the filler content of the adhesive film; The filling volume of the plastic encapsulation material is smaller than the filling volume of the adhesive film.

11. A method for forming a semiconductor packaging structure, characterized in that: The method comprises: providing a substrate; Etching the front surface of the substrate to form a first groove; implanting a first chip into the first groove; A substrate through hole is formed in the substrate; the substrate through hole vertically penetrates the substrate and is located outside the first groove; Etching the back side of the substrate to form a second groove; implanting a second chip into the second groove; The first chip and the second chip are electrically connected to the corresponding substrate through holes respectively; the first chip and the second chip are communicatively interconnected through the substrate through holes.

12. The forming method according to claim 11, characterized in that: The first chip and the second chip are electrically connected to the corresponding substrate through holes, respectively, including: On the front side of the substrate, a first redistribution layer is formed to electrically connect the first chip to one end of the corresponding substrate through hole; Performing a thinning process on the back side of the substrate to expose the other end of the substrate through hole; A second redistribution layer is formed on the back side of the substrate to electrically connect the second chip to the other end of the corresponding substrate through hole.

13. The forming method according to claim 11, characterized in that: Implanting the first chip into the first groove includes: Adhere the first chip to the bottom surface of the first groove through an adhesive film; Filling an insulating layer between the inner wall of the first groove and the side wall of the first chip; Implanting the second chip into the second groove includes: Adhere the second chip to the bottom surface of the second groove through an adhesive film; An insulating layer is filled between the inner wall of the second groove and the side wall of the second chip.

14. The forming method according to any one of claims 11 to 13, characterized in that: After electrically connecting the first chip and the second chip to the corresponding substrate through holes, the forming method further includes: Performing a dicing process on the substrate; Thermally press-bonding the base and the substrate; wherein the position of the thermal press-bonding is in accordance with the position of the through hole of the base; A molding material surrounding the substrate is formed by an injection molding process.

15. The forming method according to claim 14, characterized in that: The number of the substrates is multiple; The base and the substrate are thermally pressed and bonded together, comprising: Thermally pressing and bonding the first substrate to the base plate; The remaining chips are stacked on the first substrate in sequence, and the adjacent substrates are bonded by thermal compression.

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