Semiconductor packaging structure and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor packaging structure and a forming method thereof. The semiconductor packaging structure comprises a substrate and a plurality of chips. The substrate comprises a groove and a substrate through hole. The groove and the base through hole penetrate through the base in the vertical direction. The substrate through hole is located outside the groove. The plurality of chips are stacked in the groove in the vertical direction, are electrically connected to the corresponding substrate through holes, and are in communication interconnection through the substrate through holes.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a semiconductor package structure and a method for forming the same. Background Art

[0002] Three-dimensional chip packaging technology is to stack two or more chips vertically in the same packaging structure. It improves many chip performances, such as size, weight, speed, output and energy consumption. However, there are still areas that can be optimized in the three-dimensional chip packaging of related technologies, and it is necessary to further improve product performance and save costs. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a semiconductor packaging structure and a method for forming the same, which can improve product performance and save costs.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides a semiconductor packaging structure, which includes: a substrate, including a groove and a substrate through hole; the groove and the substrate through hole both penetrate the substrate in a vertical direction; the substrate through hole is located on the outside of the groove; a plurality of chips are stacked in the groove along the vertical direction and electrically connected to the corresponding substrate through holes; the plurality of chips are communicatively interconnected through the substrate through holes.

[0006] In some embodiments, the semiconductor packaging structure further includes: two redistribution layers; the two redistribution layers are respectively located on the front and back sides of the substrate; each chip is electrically connected to a corresponding substrate through-hole through a corresponding redistribution layer.

[0007] In some embodiments, the plurality of chips include: a first chip and a second chip; the front side of the first chip is oriented in the same direction as the front side of the substrate, and is electrically connected to the redistribution layer located on the front side of the substrate through conductive bumps; the front side of the second chip is oriented in the same direction as the back side of the substrate, and is electrically connected to the redistribution layer located on the back side of the substrate through conductive bumps.

[0008] In some embodiments, the plurality of chips include: a first chip, a second chip, a third chip and a fourth chip stacked in sequence; the first chip and the second chip are staggered and stacked along a first direction; the third chip and the fourth chip are staggered and stacked along the first direction; the first direction is perpendicular to the vertical direction; the front side of the first chip and the front side of the second chip are oriented in the same direction as the front side of the substrate; the front side of the third chip and the front side of the fourth chip are oriented in the same direction as the back side of the substrate.

[0009] In some embodiments, the front side of the first chip is electrically connected to the redistribution layer located on the front side of the substrate through conductive bumps; the front side of the second chip is electrically connected to the redistribution layer located on the front side of the substrate through conductive pillars; the front side of the third chip is electrically connected to the redistribution layer located on the back side of the substrate through conductive pillars; and the front side of the fourth chip is electrically connected to the redistribution layer located on the back side of the substrate through conductive bumps.

[0010] In some embodiments, adjacent chips are bonded to each other via an adhesive film.

[0011] In some embodiments, an insulating layer is filled between the inner wall of the groove and the side walls of the plurality of chips.

[0012] In some embodiments, there are multiple substrates; the multiple substrates are stacked along the vertical direction; plastic packaging materials are filled between adjacent substrates; and the adjacent chips located in different substrates are bonded to each other and electrically connected.

[0013] In some embodiments, the adhesive film and the molding material both include: resin and filler; wherein the filler is silicon oxide or aluminum oxide; the filler content of the molding material is greater than the filler content of the adhesive film; and the filler volume of the molding material is less than the filler volume of the adhesive film.

[0014] In some embodiments, the thermal expansion coefficient of the molding material is greater than the thermal expansion coefficient of the substrate.

[0015] An embodiment of the present disclosure also provides a method for forming a semiconductor packaging structure, the method comprising: providing a substrate; etching the substrate to form a groove; the groove penetrates the substrate along a vertical direction; stacking a plurality of chips in the groove along the vertical direction; forming a substrate through hole in the substrate; the substrate through hole penetrates the substrate along the vertical direction and is located outside the groove; electrically connecting the plurality of chips to corresponding substrate through holes; the plurality of chips are communicatively interconnected through the substrate through holes.

[0016] In some embodiments, a plurality of the chips are electrically connected to the corresponding substrate through holes, including: forming a first redistribution layer on the front side of the substrate to electrically connect a portion of the chips to the corresponding substrate through holes; wherein the front side of a portion of the chips is oriented in the same direction as the front side of the substrate; thinning the back side of the substrate to expose another portion of the chips; wherein the front side of another portion of the chips is oriented in the same direction as the back side of the substrate; forming a second redistribution layer on the back side of the substrate to electrically connect another portion of the chips to the corresponding substrate through holes.

[0017] In some embodiments, multiple chips are stacked in the groove along the vertical direction, including: implanting the first chip into the groove and bonding the first chip to the bottom surface of the groove with an adhesive film; implanting the remaining chips into the groove in sequence and bonding adjacent chips with an adhesive film; and filling an insulating layer between the inner wall of the groove and the side walls of the multiple chips.

[0018] In some embodiments, after electrically connecting the plurality of chips to the corresponding substrate through holes, the formation method further includes: performing a slicing process on the substrate; thermally pressing and bonding the substrate to a base plate; wherein the position of the thermal pressing and bonding is in accordance with the position of the substrate through holes; and forming a plastic encapsulation material surrounding the substrate through an injection molding process.

[0019] In some embodiments, there are multiple substrates; thermally pressing and bonding the substrates to the baseplate includes: thermally pressing and bonding the first substrate to the baseplate; stacking the remaining chips on the first substrate in sequence, and thermally pressing and bonding adjacent substrates.

[0020] It can be seen that the embodiments of the present disclosure provide a semiconductor packaging structure and a method for forming the same, the semiconductor packaging structure comprising: a substrate and a plurality of chips. The substrate comprises a groove and a substrate through-hole. The groove and the substrate through-hole both penetrate the substrate in a vertical direction. The substrate through-hole is located on the outside of the groove. A plurality of chips are stacked in the groove in a vertical direction, and are electrically connected to the corresponding substrate through-holes, and are communicated and interconnected through the substrate through-holes. In this way, a plurality of chips realize vertical communication interconnection (i.e., three-dimensional packaging interconnection) through the substrate through-holes, that is, communication interconnection between chips is realized without forming through-holes through the chips. Therefore, on the one hand, there is no need to reserve area in the chip for the through-holes and the KOZ (exclusion zone) near the through-holes, which can reduce the size of the chip and increase the DPW (number of grains that can be cut on a wafer); on the other hand, the process can be simplified and costs can be saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 1 ;

[0022] Figure 2 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 2 ;

[0023] Figure 3 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 3 ;

[0024] Figure 4 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 4 ;

[0025] Figure 5 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 5 ;

[0026] Figure 6 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 6 ;

[0027] Figure 7 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 7 ;

[0028] Figure 8 The process of forming a semiconductor packaging structure provided by the embodiment of the present disclosure Figure 1 ;

[0029] Fig. 9 The process of forming a semiconductor packaging structure provided by the embodiment of the present disclosure Figure 2 ;

[0030] Fig.10 The process of forming a semiconductor packaging structure provided by the embodiment of the present disclosure Figure 3 ;

[0031] Fig.11 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 1 ;

[0032] Fig.12 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 2 ;

[0033] Fig.13 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 3 ;

[0034] Fig.14 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 4 ;

[0035] Fig.15 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 5 ;

[0036] Fig.16 A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 6 ;

[0037] Fig.17A structural diagram of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure Figure 7 . DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0039] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0040] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0042] The following are explanations of some terms in the embodiments of the present disclosure:

[0043] RDL (Re-distributed Layer): A wiring pattern formed on the chip surface that rearranges the chip's I / O ports.

[0044] TSV (Through Silicon Via): A structure that uses vertical through holes for electrical connection.

[0045] KOZ (Keep Out Zone): An area close to a semiconductor structure. To avoid interference, no other semiconductor structures can be set in the exclusion zone.

[0046] DPW (Die Per Wafer): refers to the number of die that can be cut from each wafer.

[0047] FO (Fan-out): A packaging method in which the solder joint setting range can exceed the area of ​​the bare die and can provide more I / O solder joints.

[0048] Figure 1 is an optional structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure, Figure 1 is a cross-sectional view. Figure 1 As shown, the semiconductor package structure includes: a substrate 10 and a plurality of chips (ie Figure 1 The first chip 201 and the second chip 202 in the embodiment of the present invention are shown in FIG.

[0049] refer to Figure 1 The substrate 10 includes a groove 101 and a substrate through hole 11, wherein the groove 101 and the substrate through hole 11 both penetrate the substrate 10 along the vertical direction Z, and the substrate through hole 11 is located outside the groove 101. A plurality of chips (i.e., a first chip 201 and a second chip 202) are stacked in the groove 101 along the vertical direction Z and are electrically connected to the corresponding substrate through holes 11; the plurality of chips are interconnected and communicated through the substrate through holes 11.

[0050] In the embodiments of the present disclosure, reference Figure 1 The substrate 10 may be made of a semiconductor material, such as a silicon substrate. Accordingly, the substrate through hole 11 may be a TSV. The substrate through hole 11 may be filled with a conductive material such as copper, tungsten or polysilicon to interconnect multiple chips (i.e., the first chip 201 and the second chip 202).

[0051] In the disclosed embodiment, the semiconductor material used for the substrate 10 can be consistent with the semiconductor material used for multiple chips (i.e., the first chip 201 and the second chip 202). In this way, the stress caused by the different CTE (coefficient of thermal expansion) between the structures can be eliminated, thereby avoiding warpage.

[0052] In the present disclosure, continue to refer to Figure 1 The groove 101 penetrates the substrate 10 along the vertical direction Z, and then the first chip 201 and the second chip 202 are implanted in the groove 101. The substrate through hole 11 is located outside the groove 101, that is, the substrate through hole 11 is located outside the first chip 201 and the second chip 202, and no through hole is formed inside the first chip 201 and the second chip 202.

[0053] It should be noted that if a through hole is formed in the chip, especially in the packaging process, the through hole in the chip needs to be exposed from the back of the chip, which will bring higher costs and more complicated processes. At the same time, if a through hole is formed in the chip, then it is necessary to reserve an area for the through hole and the KOZ near the through hole in the chip, which occupies more chip area and is not conducive to reducing the size of the chip.

[0054] It is understandable that in the disclosed embodiment, multiple chips realize vertical communication interconnection (i.e., three-dimensional packaging interconnection) through substrate through holes. In this way, communication interconnection between chips can be realized without forming through holes through the chips. Therefore, on the one hand, it is not necessary to reserve area for through holes and KOZ near through holes in the chip, which can reduce the size of the chip and improve DPW; on the other hand, it can simplify the process and save costs.

[0055] At the same time, this embodiment sets the TSV in the silicon substrate, and there is no need to consider the impact of TSV on the internal components of the chip. Manufacturing TSV with a larger diameter in the silicon substrate reduces the aspect ratio of TSV and reduces the process difficulty. At the same time, the TSV with a larger diameter has a smaller resistance in the entire loop, which is conducive to reducing the power consumption of the device. At the same time, TSV is not in the chip, which can also improve the impact of TSV heat generation on the chip.

[0056] At the same time, if a TSV structure is manufactured in each chip, each chip needs to undergo a TSV exposure process. A single chip is relatively thin, and due to stress, some risks of warping and fragmentation are prone to occur during the TSV exposure process. However, the disclosed embodiment only requires one TSV exposure process on the back side of the substrate, stacking multiple chips (such as two or four chips) together to increase the overall thickness, and then performing the TSV back exposure process, which reduces the risk of chip fragmentation and improves the chip warping problem. At the same time, it also reduces the demand for the TSV exposure process by 50%, simplifies the process, and can improve the product yield.

[0057] In some embodiments of the present disclosure, reference Figure 1 The semiconductor package structure further includes two redistribution layers 301 and 302. The two redistribution layers 301 and 302 are located on the front and back sides of the substrate 10, respectively, wherein the redistribution layer 301 is located on the front side of the substrate 10, and the redistribution layer 302 is located on the back side of the substrate 10.

[0058] In the present disclosure, continue to refer to Figure 1 , the first chip 201 is electrically connected to the corresponding substrate through hole 11 through the redistribution layer 301, and the second chip 202 is electrically connected to the corresponding substrate through hole 11 through the redistribution layer 302. In other words, each chip is electrically connected to the corresponding substrate through hole 11 through a corresponding redistribution layer.

[0059] Figure 2 is an optional structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure, Figure 2 This is a top view. Figure 2 A wiring pattern of the redistribution layer 301 is illustrated.

[0060] refer to Figure 2 The redistribution layer 301 electrically connects the ports on the first chip 201 to the corresponding substrate through holes 11. The wiring pattern of the redistribution layer 302 can be referred to Figure 2 The wiring pattern of the middle heavy wiring layer 301 can be understood.

[0061] It should be noted that in Figure 2 In the embodiment, the redistribution layer 301 connects each port on the first chip 201 to the substrate through hole 11 on the same side. However, the wiring pattern of the redistribution layer 301 can be adjusted as needed and is not limited to Figure 2 The wiring pattern shown, for example, the redistribution layer 301 connects each port on the first chip 201 to the substrate through-hole 11 on the opposite side, which is not limited here.

[0062] It can be understood that each chip is electrically connected to the corresponding substrate through-hole in the substrate through the redistribution layer to realize the communication interconnection of each chip. In this way, the communication interconnection between chips can be realized without forming through-holes through the chips; thus, on the one hand, there is no need to reserve area for through-holes and KOZ near through-holes in the chip, which can reduce the size of the chip and improve DPW; on the other hand, there is no need to implement the relevant process of forming through-holes in the chip, thereby simplifying the process and saving costs.

[0063] At the same time, by using the rewiring layer, the ports on the chip can be rearranged, so the ports on the chip can be designed more closely, thereby reducing the size of the chip.

[0064] In the embodiments of the present disclosure, reference Figure 1 The front side of the first chip 201 is aligned with the front side of the substrate 10 and is electrically connected to the redistribution layer 301 on the front side of the substrate 10 through a conductive bump 401. The front side of the second chip 202 is aligned with the back side of the substrate 10 and is electrically connected to the redistribution layer 302 on the back side of the substrate 10 through a conductive bump (or pad) 401.

[0065] Figure 4 and Figure 5 are two other optional structural schematic diagrams of the semiconductor packaging structure provided by the embodiments of the present disclosure, Figure 4 and Figure 5 All are cross-sectional views.

[0066] like Figure 4 or Figure 5As shown, the plurality of chips include: a first chip 201, a second chip 202, a third chip 203, and a fourth chip 204 stacked in sequence. The first chip 201 and the second chip 202 are stacked in a staggered manner along a first direction X. The third chip 203 and the fourth chip 204 are stacked in a staggered manner along the first direction X. The first direction X is perpendicular to the vertical direction Z. The front side of the first chip 201 and the front side of the second chip 202 are aligned with the front side of the substrate 10. The front side of the third chip 203 and the front side of the fourth chip 204 are aligned with the back side of the substrate 10.

[0067] In the present disclosure, continue to refer to Figure 4 or Figure 5 The front side of the first chip 201 is electrically connected to the redistribution layer 301 located on the front side of the substrate 10 through the conductive bump 401. The front side of the second chip 202 is electrically connected to the redistribution layer 301 located on the front side of the substrate 10 through the conductive pillar 402. The front side of the third chip 203 is electrically connected to the redistribution layer 302 located on the back side of the substrate 10 through the conductive pillar 402. The front side of the fourth chip 204 is electrically connected to the redistribution layer 302 located on the back side of the substrate 10 through the conductive bump 401.

[0068] It should be noted that Figure 4 In the semiconductor package structure shown, the projections of the second chip 202 and the third chip 203 along the vertical direction Z overlap; that is, the second chip 202 and the third chip 203 are not stacked in a staggered manner along the first direction X. Figure 5 In the semiconductor package structure shown, the second chip 202 and the third chip 203 are also stacked in a staggered manner along the first direction X; that is, any two adjacent chips among the plurality of chips 201 - 204 are stacked in a staggered manner along the first direction X.

[0069] Figure 5 In the semiconductor package structure shown, the length of the transmission path between the first chip 201 and the third chip 203 is consistent with the length of the transmission path between the second chip 202 and the fourth chip 204. In other words, the above two groups of transmission paths both include the conductive bump 401 and the conductive column 402, thereby ensuring that the lengths of the two groups of transmission paths are consistent.

[0070] It can be understood that multiple chips are stacked in the grooves in the substrate, and adjacent chips are stacked in a staggered manner; at the same time, multiple chips are electrically connected to the redistribution layer through conductive bumps or conductive pillars, and further electrically connected to the corresponding substrate through holes to achieve communication interconnection. In this way, three-dimensional packaging of multiple chips is achieved, the integration level is improved, and the product performance is improved.

[0071] In some embodiments of the present disclosure, reference Figures 3 to 5In any of the figures, adjacent chips are bonded to each other by adhesive film 501. Adhesive film 501 includes resin and filler; wherein the filler may be silicon oxide (SiO) or aluminum oxide (AlO). Adhesive film 501 has a heat insulation effect, so that the heat generated by each chip will not affect each other, thereby ensuring the stable operation conditions of each chip.

[0072] In some embodiments of the present disclosure, reference Figures 3 to 5 In any of the figures in FIG. 1 , an insulating layer 502 is filled between the inner wall of the groove and the side walls of the plurality of chips. The insulating layer 502 may be made of polyimide (PI). The insulating layer 502 needs to have a better filling performance, that is, the filler volume of the insulating layer 502 is smaller than the filler volume of the adhesive film 501, and the filler content of the insulating layer 502 is also smaller than the filler content of the adhesive film 501.

[0073] It is understandable that filling the insulating layer 502 outside the sidewall of the chip can, on the one hand, avoid short circuits; on the other hand, protect each chip from being affected by the stress of the substrate 10 .

[0074] In the embodiment of the present disclosure, the front side (circuit layer) of a part of the chips is aligned with the front side of the substrate, and the front side (circuit layer) of another part of the chips is aligned with the back side of the substrate, that is, the front side of a part of the chips is upwardly arranged, and the front side of another part of the chips is downwardly arranged. Figure 1 and Figure 3 In the embodiment, the first chip 201 is arranged with its front side facing upward, and the second chip 202 is arranged with its front side facing downward; Figure 4 and Figure 5 In the embodiment, the first chip 201 and the second chip 202 are arranged with their front faces facing upward, and the third chip 203 and the fourth chip 204 are arranged with their front faces facing downward. In this way, the circuit layers on different chips are far apart, thereby reducing signal crosstalk between different chips.

[0075] In the disclosed embodiment, each chip is electrically connected to the substrate through-hole through the redistribution layer to form signal interconnection, and at the same time, the redistribution layer extends to the outside of the chip. Figure 1 and Figure 3 In the embodiment, the first chip 201 is electrically connected to the substrate through hole 11 through the redistribution layer 301, and the redistribution layer 301 extends to the outside of the first chip 201; Figure 4 and Figure 5In the embodiment, the fourth chip 204 is electrically connected to the substrate through hole 11 through the redistribution layer 302, and the redistribution layer 302 extends to the outside of the fourth chip 204. In this way, the spacing between the substrate through holes 11 is increased, so that the signal crosstalk effect is reduced. At the same time, since the substrate through hole 11 is also far away from the chip, the heat generated by the substrate through hole 11 has little effect on the chip.

[0076] Combination Figure 3 and Figure 6 , the redistribution layer 301 is located on the surface of the insulating layer 502, that is, the redistribution layer 301 extends on the insulating layer 502, and the two ends are respectively connected to the corresponding chip and the substrate through hole 11, so as to realize signal transmission. At the same time, the redistribution layer 301 has a large surface area, so the redistribution layer 301 will also generate a large amount of heat. Since the thermal conductivity of the insulating layer 502 is poor, the thermal conductivity of the molding material 503 is good (greater than the thermal conductivity of the insulating layer 502), and the redistribution layer 301 is in direct contact with the molding material 503, therefore, the heat generated by the redistribution layer 301 will be dissipated from the molding material 503 to the outside, thereby reducing the influence of heat on the chip.

[0077] like Figure 6 As shown, in some embodiments, the material of the insulating layer 502 is, for example, polyimide, and the material of the molding material 503 is, for example, a molding material. Polyimide is formed by combining a resin material and a small amount of filler, and the molding material is formed by combining a resin material and a large amount of filler. The resin material has good fluidity, but poor thermal conductivity, so the molding material 503 has more fillers (silicon oxide) relative to the insulating layer 502, so that the molding material 503 has greater thermal conductivity. At the same time, since the gap between the first chip 201 and the side wall of the first groove 101 is small, only a few microns to more than ten microns, therefore, in order to better fix the first chip 201, a smaller filler can be added to the resin material, that is, the filler volume in the insulating layer 502 is smaller than the filler volume in the molding material 503, thereby increasing the fluidity of the insulating layer 502 and having better filling ability.

[0078] In some embodiments, reference Figure 3 , the first chip 201 and the second chip 202 can be chips of the same type, for example, both are dynamic random access memory chips (DRAM) and static random access memory chips (SRAM). In other embodiments, the first chip 201 and the second chip 202 can also be chips of different types, for example, the first chip 201 is a memory chip and the second chip 202 is a control chip. When the first chip 201 and the second chip 202 are chips of different types, the substrate through hole 11 can provide the same power signal to the two.

[0079] In some embodiments of the present disclosure, reference Figure 6 or Figure 7 In the semiconductor packaging structure, there are multiple substrates 10. Multiple substrates 10 are stacked along the vertical direction Z. Between adjacent substrates 10, a plastic encapsulation material 503 is filled. The adjacent chips located in different substrates 10 are bonded to each other and electrically connected.

[0080] It should be noted that Figure 6 and Figure 7 In the example, the number of substrates 10 is two. On this basis, more substrates 10 can be stacked. That is, the number of substrates 10 is not limited to two. The structure and connection relationship can refer to Figure 6 and Figure 7 .

[0081] In the embodiments of the present disclosure, reference Figure 6 , the chip 202 and the chip 203 are respectively located in two different substrates, and the chip 202 and the chip 203 are bonded to each other and electrically connected, wherein the bonding position is located at the position of the substrate through hole 11. At the same time, the chip 201 and the chip 202 are electrically connected through the corresponding substrate through hole 11, and the chip 203 and the chip 204 are also electrically connected through the corresponding substrate through hole 11. In this way, the chips 201, 202, 203 and 204 can all achieve communication interconnection.

[0082] In the embodiments of the present disclosure, reference Figure 7 , chip 202 and chip 203 are respectively located in two different substrates, and chip 202 and chip 203 are bonded to each other and electrically connected, wherein the bonding position is located at the position of conductive bump 401. At the same time, chip 201 and chip 202 are electrically connected through the corresponding substrate through hole 11, and chip 203 and chip 204 are also electrically connected through the corresponding substrate through hole 11. In this way, communication interconnection can be achieved between chips 201, 202, 203 and 204. Since chips 202 and 203 are relatively close to the conductive bump 401, the use of Figure 7 The structure shown in the example can shorten the interconnection path, reduce loop resistance, and improve operating efficiency.

[0083] It can be understood that multiple substrates 10 are stacked and the chips in different substrates 10 are electrically connected to each other through bonding; at the same time, in each substrate 10, different chips are electrically connected through corresponding substrate through holes 11. In this way, three-dimensional packaging of multiple chips is achieved, and higher performance is obtained with a smaller packaging size.

[0084] At the same time, the bonding position can be located at the position of the substrate through hole 11, and the substrate through hole 11 is located on the outside of the chip (any one of the chips 201 to 204), that is, an FO type package is adopted, so that the setting range of the bonding solder joints is larger, and more solder joints can be set, which is more beneficial for chip design.

[0085] In some embodiments of the present disclosure, reference Figure 6 or Figure 7 The adhesive film 501 and the molding material 503 both include resin and filler, wherein the filler may be silicon oxide or aluminum oxide.

[0086] It should be noted that, in the adhesive film 501 and the molding material 503 , the resin is the basic material, and the filler is added into the basic material in a certain proportion.

[0087] In some embodiments of the present disclosure, reference Figure 6 or Figure 7 , the filler content of the molding material 503 is greater than the filler content of the adhesive film 501. The larger the filler content of the molding material 503, the smaller the resin content. Since the heat dissipation capacity of the resin is relatively poor, the heat dissipation capacity of the molding material 503 is relatively good. In this way, the semiconductor packaging structure can dissipate heat better.

[0088] In some embodiments of the present disclosure, reference Figure 6 or Figure 7 , the filling volume of the plastic encapsulation material 503 is smaller than the filling volume of the adhesive film 501. The smaller the filling volume, the better the fluidity of the material, so the plastic encapsulation material 503 has better fluidity. In this way, the plastic encapsulation material 503 can be better filled and gaps due to inadequate filling can be avoided.

[0089] In some embodiments of the present disclosure, reference Figure 6 or Figure 7 The thermal expansion coefficient (CTE) of the molding material 503 is greater than the thermal expansion coefficient of the substrate 10. The molding material 503 and the substrate 10 are in contact with each other over a large area, and the thermal expansion coefficient of the molding material 503 is greater, so the substrate 10 can suppress the warping of the molding material 503.

[0090] Figure 8 An optional flow chart of a method for forming a semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 8 As shown, the method for forming a semiconductor package structure includes S101 to S105, which will be described in conjunction with each step.

[0091] It should be noted that Figures 11 to 17The structure of a semiconductor package structure during the formation process is shown, which is used to describe and clearly illustrate the steps of a method for forming a semiconductor package structure.

[0092] S101. Provide a substrate.

[0093] In the embodiments of the present disclosure, reference Fig.11 The substrate 10 may be made of a semiconductor material, such as a silicon substrate. The semiconductor material used in the substrate 10 may be consistent with the semiconductor material used in the subsequently implanted chip, so that the stress caused by the different CTEs between the structures can be eliminated, thereby avoiding warpage.

[0094] S102, etching the substrate to form a groove; the groove penetrates the substrate in a vertical direction.

[0095] In the embodiments of the present disclosure, reference Fig.12 , a groove 101 can be first etched on the front surface of the substrate 10; then, Fig.15 After the back side of the substrate 10 is thinned, the groove 101 can penetrate the substrate 10 along the vertical direction Z.

[0096] S103, stacking a plurality of chips in the groove along a vertical direction.

[0097] In the present disclosure, in combination Fig.12 and Fig.13 After etching the groove 101 , a plurality of chips (ie, the first chip 201 and the second chip 202 ) may be stacked in the groove 101 along the vertical direction Z. In the embodiment of FIG.

[0098] S104, forming a substrate through hole in the substrate; the substrate through hole penetrates the substrate in a vertical direction and is located outside the groove.

[0099] In the present disclosure, in combination Fig.13 and Fig.14 , a substrate through hole 11 may be formed in the substrate 10. The substrate through hole 11 is located outside the groove 101, that is, the substrate through hole 11 is located outside the plurality of chips (ie, the first chip 201 and the second chip 202). Fig.15 After the back side of the substrate 10 is thinned, the substrate through hole 11 may penetrate the substrate 10 along the vertical direction Z.

[0100] In the present disclosure, in combination Fig.13 and Fig.14 , an opening may be formed at the pad of the first chip 201 and at the corresponding position of the substrate through hole 11, and then the substrate through hole 11 may be formed. The substrate through hole 11 may be filled with conductive materials such as copper, tungsten or polysilicon to interconnect the various chips.

[0101] S105 , electrically connecting the plurality of chips to corresponding substrate through-holes; the plurality of chips are interconnected and communicated through the substrate through-holes.

[0102] In the embodiments of the present disclosure, reference Fig.15 , multiple chips (i.e., the first chip 201 and the second chip 202) are electrically connected to the corresponding substrate through-holes 11, and are interconnected through the substrate through-holes 11. In this way, inter-chip communication and interconnection are achieved without the need to form through-holes through the chips; thus, on the one hand, there is no need to reserve an area for the through-holes and the KOZ near the through-holes in the chip, which can reduce the chip size and improve the DPW; on the other hand, the process can be simplified and the cost can be saved.

[0103] In some embodiments of the present disclosure, Fig. 9 S201 to S203 shown are implemented Figure 8 S105 shown will be described in conjunction with each step.

[0104] S201, forming a first redistribution layer on the front side of the substrate to electrically connect a portion of the chips to corresponding substrate through holes; wherein the front side of a portion of the chips is aligned with the front side of the substrate.

[0105] In the embodiments of the present disclosure, reference Fig.14 , one end of the substrate through hole 11 is exposed on the front side of the substrate 10. A first redistribution layer 301 may be formed on the front side of the substrate 10 to electrically connect the first chip 201 to one end of the corresponding substrate through hole 11. The first redistribution layer 301 is electrically connected to the pad of the first chip 201; the front side of the first chip 201 is aligned with the front side of the substrate 10.

[0106] S202, thinning the back side of the substrate to expose another portion of the chips; wherein the front side of the other portion of the chips is aligned with the back side of the substrate.

[0107] In the present disclosure, in combination Fig.14 and Fig.15 The back side of the substrate 10 may be thinned to expose the second chip 202 and the other end of the substrate through hole 11. The front side of the second chip 202 is aligned with the back side of the substrate 10.

[0108] S203 , forming a second redistribution layer on the back side of the substrate to electrically connect another portion of the chips to the corresponding substrate through holes.

[0109] In the embodiments of the present disclosure, reference Fig.15A second redistribution layer 302 may be formed on the back side of the substrate 10 to electrically connect the second chip 202 to the other end of the corresponding substrate through hole 11. The second redistribution layer 302 is electrically connected to the pad of the second chip 202.

[0110] It can be understood that each chip is electrically connected to the corresponding substrate through-hole in the substrate through the redistribution layer to realize the communication interconnection of each chip. In this way, the communication interconnection between chips can be realized without forming through-holes through the chips; thus, on the one hand, there is no need to reserve area for through-holes and KOZ near through-holes in the chip, which can reduce the size of the chip and improve DPW; on the other hand, there is no need to implement the relevant process of forming through-holes in the chip, thereby simplifying the process and saving costs.

[0111] In some embodiments of the present disclosure, S301 to S303 can be used to implement Figure 8 S103 shown will be described in conjunction with each step.

[0112] S301, implanting a first chip into the groove, and bonding the first chip to the bottom surface of the groove with an adhesive film.

[0113] In the present disclosure, in combination Fig.12 and Fig.13 First, the second chip 202 (i.e., the first chip) located at the bottom can be implanted into the groove 101, and the second chip 202 and the bottom surface of the groove 101 can be bonded by the adhesive film 501. The adhesive film 501 includes resin and filler, wherein the filler can be silicon oxide (SiO) or aluminum oxide (AlO).

[0114] S302, implanting the remaining chips into the grooves in sequence, and bonding adjacent chips with adhesive films.

[0115] In the present disclosure embodiment, continue to combine Fig.12 and Fig.13 After the second chip 202 (ie, the first chip) is implanted, the first chip 201 (ie, the remaining chips) located above can be implanted into the groove 101 , and the first chip 201 and the second chip 202 can be bonded to each other using the adhesive film 501 .

[0116] It is understandable that the adhesive film 501 has a heat insulating effect, so that it can be ensured that the heat generated by multiple chips will not affect each other, thereby ensuring that the operating conditions of the multiple chips are stable.

[0117] S303 , filling an insulating layer between the inner wall of the groove and the side walls of the plurality of chips.

[0118] In the present disclosure embodiment, continue to combine Fig.12 and Fig.13After bonding the plurality of chips (ie, the first chip 201 and the second chip 202), an insulating layer 502 may be filled between the inner wall of the groove 101 and the sidewalls of the plurality of chips. The insulating layer 502 may be made of PI.

[0119] It is understandable that filling the insulating layer 502 outside the side walls of the plurality of chips can, on the one hand, avoid short circuits; on the other hand, can protect the plurality of chips from being affected by the stress of the substrate 10 .

[0120] In some embodiments of the present disclosure, Figure 8 After S105 shown, the forming method further includes Fig.10 S106 to S108 shown will be described in conjunction with each step.

[0121] S106, performing a dicing process on the substrate.

[0122] S107, thermally press-bonding the substrate and the base plate; wherein the position of the thermal press-bonding is in accordance with the position of the through hole of the substrate.

[0123] S108, forming a plastic packaging material surrounding the substrate through an injection molding process.

[0124] In the embodiments of the present disclosure, reference Fig.16 After the various structures on the substrate 10 are formed, the substrate 10 can be diced to cut out the substrate 10. Then, the substrate 10 is thermally pressed (TCB) bonded to the base plate 60, wherein the position of the thermal compression bonding can be based on the position of the substrate through hole 11. Then, the plastic encapsulation material 503 surrounding the substrate 10 can be formed by injection molding.

[0125] In the present disclosure, continue to refer to Fig.16 The adhesive film 501 and the molding material 503 both include resin and filler, wherein the resin is the base material and the filler is added into the base material in a certain proportion. The filler may be silicon oxide or aluminum oxide.

[0126] In some embodiments of the present disclosure, the filler content of the molding material 503 is greater than the filler content of the adhesive film 501. The larger the filler content of the molding material 503, the smaller the resin content. Since the heat dissipation capacity of the resin is relatively poor, the heat dissipation capacity of the molding material 503 is relatively good. In this way, the semiconductor packaging structure can better dissipate heat.

[0127] In some embodiments of the present disclosure, the filling volume of the molding material 503 is smaller than the filling volume of the adhesive film 501. The smaller the filling volume, the better the fluidity of the material, and therefore, the molding material 503 has better fluidity. In this way, the molding material 503 can be better filled, and gaps due to inadequate filling can be avoided.

[0128] In some embodiments of the present disclosure, the number of substrates is multiple, which can be achieved through S401 to S402. Fig.10 S107 shown will be described in conjunction with each step.

[0129] S401, thermally pressing and bonding the first substrate to the base plate.

[0130] S402, stacking the remaining chips on the first substrate in sequence, and thermally pressing and bonding adjacent substrates.

[0131] In the embodiments of the present disclosure, reference Fig.17 , the first substrate 10 (i.e. the substrate 10 at the bottom) can be thermocompressively bonded to the base plate 60. Then, the second substrate 10 can be stacked on the first substrate 10, and the second substrate 10 can be thermocompressively bonded to the first substrate 10, wherein the bonding position can be located at the position of the substrate through hole 11. By analogy, more substrates 10 can be stacked.

[0132] It can be understood that multiple substrates 10 are stacked and the chips in different substrates 10 are electrically connected to each other through bonding; at the same time, in each substrate 10, different chips are electrically connected through corresponding substrate through holes 11. In this way, three-dimensional packaging of multiple chips is achieved, and higher performance is obtained with a smaller packaging size.

[0133] At the same time, the bonding position can be located at the position of the substrate through hole 11, and the substrate through hole 11 is located on the outside of the chip (any one of the chips 201 to 204), that is, an FO type package is adopted, so that the setting range of the bonding solder joints is larger, and more solder joints can be set, which is more beneficial for chip design.

[0134] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0135] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0136] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: The semiconductor packaging structure comprises: A substrate, wherein the substrate comprises a groove and a substrate through hole; the groove and the substrate through hole both penetrate the substrate in a vertical direction; and the substrate through hole is located outside the groove; A plurality of chips are stacked in the groove along the vertical direction and electrically connected to the corresponding substrate through holes; the plurality of chips are interconnected and communicated through the substrate through holes.

2. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure further includes: two redistribution layers; The two redistribution layers are respectively located on the front and back sides of the substrate; Each of the chips is electrically connected to a corresponding substrate through-hole through a corresponding layer of the redistribution layer.

3. The semiconductor package structure according to claim 2, characterized in that: The plurality of chips include: a first chip and a second chip; The front side of the first chip is aligned with the front side of the substrate and is electrically connected to the redistribution layer located on the front side of the substrate through conductive bumps; The front side of the second chip is aligned with the back side of the substrate and is electrically connected to the redistribution layer on the back side of the substrate through conductive bumps.

4. The semiconductor package structure according to claim 2, wherein: The plurality of chips include: a first chip, a second chip, a third chip and a fourth chip stacked in sequence; The first chip and the second chip are staggered and stacked along a first direction; the third chip and the fourth chip are staggered and stacked along the first direction; the first direction is perpendicular to the vertical direction; The front side of the first chip and the front side of the second chip are oriented in the same direction as the front side of the substrate; the front side of the third chip and the front side of the fourth chip are oriented in the same direction as the back side of the substrate.

5. The semiconductor package structure according to claim 4, characterized in that: The front side of the first chip is electrically connected to the redistribution layer located on the front side of the substrate through a conductive bump; The front side of the second chip is electrically connected to the redistribution layer located on the front side of the substrate through a conductive column; The front side of the third chip is electrically connected to the redistribution layer located on the back side of the substrate through a conductive column; The front side of the fourth chip is electrically connected to the redistribution layer located on the back side of the substrate through conductive bumps.

6. The semiconductor package structure according to any one of claims 1 to 5, characterized in that: The adjacent chips are bonded to each other via adhesive films.

7. The semiconductor package structure according to any one of claims 1 to 5, characterized in that: An insulating layer is filled between the inner wall of the groove and the side walls of the plurality of chips.

8. The semiconductor package structure according to claim 6, wherein: The number of the substrates is multiple; A plurality of the substrates are stacked along the vertical direction; and plastic packaging materials are filled between adjacent substrates; The adjacent chips located in different substrates are bonded to each other and electrically connected.

9. The semiconductor package structure according to claim 8, characterized in that: The adhesive film and the plastic packaging material both include: resin and filler; wherein the filler is silicon oxide or aluminum oxide; The filler content of the plastic encapsulation material is greater than the filler content of the adhesive film; and the filler volume of the plastic encapsulation material is smaller than the filler volume of the adhesive film.

10. The semiconductor package structure according to claim 8, wherein: The thermal expansion coefficient of the molding material is greater than the thermal expansion coefficient of the substrate.

11. A method for forming a semiconductor packaging structure, characterized in that: The method comprises: providing a substrate; Etching the substrate to form a groove, wherein the groove penetrates the substrate in a vertical direction; stacking a plurality of chips in the groove along the vertical direction; A substrate through hole is formed in the substrate; the substrate through hole penetrates the substrate along the vertical direction and is located outside the groove; The plurality of chips are electrically connected to the corresponding substrate through-holes; the plurality of chips are communicatively interconnected through the substrate through-holes.

12. The forming method according to claim 11, characterized in that: Electrically connecting the plurality of chips to the corresponding substrate through holes comprises: A first redistribution layer is formed on the front surface of the substrate to electrically connect a portion of the chips to the corresponding substrate through holes; wherein the front surface of a portion of the chips is aligned with the front surface of the substrate; The back side of the substrate is thinned to expose another part of the chip; wherein the front side of the other part of the chip is in the same direction as the back side of the substrate; A second redistribution layer is formed on the back side of the substrate to electrically connect another portion of the chip to the corresponding substrate through-holes.

13. The forming method according to claim 11, characterized in that: Stacking a plurality of the chips in the groove along the vertical direction comprises: implanting the first chip into the groove, and bonding the first chip to the bottom surface of the groove with an adhesive film; implanting the remaining chips into the grooves in sequence and bonding the adjacent chips with adhesive films; An insulating layer is filled between the inner wall of the groove and the side walls of the plurality of chips.

14. The forming method according to any one of claims 11 to 13, characterized in that: After electrically connecting the plurality of chips to the corresponding substrate through holes, the forming method further comprises: Performing a dicing process on the substrate; Thermally press-bonding the base and the substrate; wherein the position of the thermal press-bonding is in accordance with the position of the through-hole of the base; A molding material surrounding the substrate is formed by an injection molding process.

15. The forming method according to claim 14, characterized in that: The number of the substrates is multiple; The base and the substrate are thermally pressed and bonded together, comprising: Thermally pressing and bonding the first substrate to the base plate; The remaining chips are stacked on the first substrate in sequence, and the adjacent substrates are thermally pressed and bonded.

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