Power supply soft start circuit and start method thereof
By using power supply soft start circuits with components such as transistors, four-way switches and flip-flops in the power supply module, soft start is achieved using pulse signals and ramp voltages, the problems of large circuit area and high cost in the existing technology are solved, and the circuit is improved Integration degree.
Patent Information
- Application Number
- CN202411434512.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-03
AI Technical Summary
The soft-start circuit of the existing power supply module has a large circuit area and high cost due to the use of capacitor devices and DAC, and cannot rise from 0V to VREF when EN_LDO is enabled from low to high, affecting the circuit integration level.
Using a power supply soft start circuit including first, second and third transistors, four-way switches, flip-flops, logic gates and low dropout linear regulators, the power is achieved by switching the current path and voltage path, and the pulse signal and ramp voltage are used to achieve softness. Start up, reduce circuit area and cost.
The power supply soft start function has been realized to greatly reduce the circuit area cost and improve the integration of the circuit.
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Figure CN119253999A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of power modules, and more specifically, to a power soft-start circuit and its starting method. Background Art
[0002] In order to avoid overcharge current spikes in the output of the power module during power-on, the power module usually has a soft-start circuit to make the output slowly rise from 0V to the power output value. The conventional soft-start circuit is to add a terminal for the soft-start voltage VSS starting from 0V together with the input terminal of the error amplifier of the power supply and the reference power supply VREF. In this way, when VSS < VREF, the output of VOUT will follow the rising time of VSS; when VSS >= VREF, the output of VOUT will follow the value of VREF.
[0003] As Figure 1 shown, a circuit of a power module in the prior art, where EN_LDO is the enable signal of the LDO, 0 represents the LDO is off, and 1 represents the LDO is on
[0004] VREF is the reference voltage for the LDO output value
[0005] VSS is the soft-start voltage
[0006] VOUT is the output voltage of the LDO
[0007] COUT is the load capacitance of the output voltage of the LDO
[0008] ROUT is the output resistance load of the LDO
[0009] R1 and C1 are the RC filter for the reference voltage to avoid the influence of the interference of VREF on the LDO reference voltage.
[0010] As Figure 2 shown, in this traditional method, M6:M7:M8 = 1:1:1 in the input pair of the error amplifier of the LDO.
[0011] There are two common schemes for generating VSS in the prior art.
[0012] Figure 3 is a circuit schematic diagram for generating VSS in the prior art. As Figure 3 shown, the capacitor C2 is charged with the bias current I5 to obtain a ramp voltage VSS.
[0013] Figure 4 is a circuit schematic diagram for generating VSS in the prior art. As Figure 4As shown in the figure, a clock is used to generate n bits, and a step-like VSS rising voltage is generated by DAC. Because the step height cannot cause output overcharge, the number n must ensure that the step height is less than a few mV.
[0014] The disadvantages of the existing technology include:
[0015] (1) The area of capacitor devices is much larger than that of other MOS devices, which is very important for cost-saving chips.
[0016] (2) Because the number n is relatively high, the LSB requirement of the DAC is very low and the area of the entire circuit is very large.
[0017] Because VREF is the reference voltage of the chip, it is not controlled by EN_LDO and cannot rise from 0V to VREF when EN_LDO enables LDO from low to high. This is why the common solution uses a VSS voltage in addition to VREF.
[0018] In view of this, the present invention provides a power soft start circuit and a start method thereof. Summary of the invention
[0019] In view of the problems in the prior art, the power soft start circuit and the starting method thereof of the present invention overcome the difficulties of the prior art, can realize the function of power soft start, greatly reduce the circuit area cost, and improve the circuit integration.
[0020] An embodiment of the present invention provides a power soft start circuit, comprising:
[0021] a first transistor, configured to switch a current path between the fourth node and the first node in response to the reference voltage signal terminal;
[0022] a second transistor for switching a current path between a third node and a ground terminal in response to a voltage at the second node;
[0023] a third transistor, configured to switch a current path between the working power supply terminal and the fifth node in response to the voltage of the fourth node;
[0024] a first four-way switch, wherein a first end of the first four-way switch is connected in series with a first resistor and then connected to a reference voltage signal end, a second end is connected to a first node, a third end is connected to a seventh node, a fourth end is connected to an output end of a first trigger, and an input end of the first trigger is connected to the seventh node;
[0025] a second four-way switch, wherein a first end of the second four-way switch is connected to the first node, a second end is connected to the third node, a third end is connected to the sixth node, and a fourth end is connected to the second node;
[0026] a second trigger connected between the sixth node and the second node;
[0027] a logic gate, wherein an output terminal of the logic gate is connected to the seventh node, an input terminal of the logic gate is connected to the sixth node, and another input terminal is connected in series with a Schmitt trigger and then connected to the fifth node; and
[0028] A low voltage dropout linear regulator, wherein the enable signal access terminal of the low voltage dropout linear regulator is connected to the sixth node, the reference signal access terminal is connected to the third node, and the output terminal is connected to a voltage output terminal.
[0029] Preferably, the first transistor and the second transistor are both NMOS transistors.
[0030] Preferably, the third transistors are all PMOS transistors.
[0031] Preferably, an input terminal of the second trigger is connected to the sixth node, and an output terminal is connected to the second node.
[0032] Preferably, it further comprises: a first bias current detection unit connected in series between the fourth node and the working power supply terminal.
[0033] Preferably, it further comprises: a second bias current detection unit connected in series between the fifth node and the ground terminal.
[0034] Preferably, the enable signal emitted by the enable signal access terminal is a pulse signal, the reference voltage emitted by the reference signal access terminal is a ramp voltage signal, the first timing corresponding to the ramp region of the reference voltage is included in the second timing of the high level of the pulse signal, and the trigger time of the rising edge of the pulse signal is synchronized with the initial rising trigger time of the ramp voltage signal.
[0035] Preferably, it also includes: a second capacitor and a second resistor are respectively connected to the voltage output end.
[0036] Preferably, the device further comprises: a first capacitor connected between the third node and the ground terminal.
[0037] An embodiment of the present invention further provides a power soft start method, which uses the above-mentioned power soft start circuit and is characterized by comprising:
[0038] S110, when the enable signal is low, the low voltage dropout linear regulator is turned off, the first four-way switch and the second four-way switch are both turned off, the second transistor is turned on and the reference signal access terminal is grounded; and
[0039] S120. When the enable signal starts to rise, the first four-way switch is disconnected, the second four-way switch is turned on, the second transistor is turned off, and the first bias current charges the first capacitor through the first transistor. As the voltage at the reference signal access terminal increases, the threshold voltage of the first transistor decreases until the first transistor is turned off. When the current capacity of the threshold voltage of the first transistor is less than the first bias voltage, the first transistor changes from disconnection to conduction, so that the first four-way switch is turned on, and the reference voltage charges the first capacitor through the first resistor until the voltage at the reference signal access terminal is equal to the reference voltage.
[0040] The power soft start circuit of the present invention can realize the function of power soft start, greatly reduce the circuit area cost, and improve the circuit integration. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0042] Figure 1 A circuit of a power module in the prior art
[0043] Figure 2 FIG. 1 is a schematic diagram of an input pair of an error amplifier of an LDO in the prior art.
[0044] Figure 3 The present invention is a circuit schematic diagram of generating VSS in the prior art.
[0045] Figure 4 The present invention is a circuit schematic diagram of generating VSS in the prior art.
[0046] Figure 5 It is a circuit diagram of a power soft start circuit of the present invention.
[0047] Figure 6 It is a schematic diagram of the timing of each signal in the multi-bond wire testing method of the present invention.
[0048] Reference numerals
[0049] 1 Enable signal terminal
[0050] 2 Logic Gates
[0051] 3 Schmitt trigger
[0052] 4 Third transistor
[0053] 5. First bias current detection unit
[0054] 6. Second bias current detection unit
[0055] 7. The First Transistor
[0056] 8 Reference voltage signal terminal
[0057] 9 First resistor
[0058] 10 First four-way switch
[0059] 11 First Trigger
[0060] 12 Second four-way switch
[0061] 13 Second trigger
[0062] 14 Second transistor
[0063] 15 Low Dropout Linear Regulator
[0064] 16 First capacitor
[0065] 17 Voltage output terminal
[0066] 18 Second capacitor
[0067] 19 Second resistor DETAILED DESCRIPTION
[0068] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the present application. The present application can also be implemented or applied through other different specific implementation methods, and the details in the present application can also be modified or changed in various ways according to different viewpoints and application systems without departing from the spirit of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0069] The following is a detailed description of the embodiments of the present application with reference to the accompanying drawings so that those skilled in the art can easily implement the present application. The present application can be embodied in a variety of different forms and is not limited to the embodiments described herein.
[0070] In the representations of the present application, the representations with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the represented specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples represented in the present application and the features of the different embodiments or examples, unless they contradict each other.
[0071] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0072] In order to clearly describe the present application, components irrelevant to the description are omitted, and the same reference symbols are given to the same or similar components throughout the specification.
[0073] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.
[0074] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.
[0075] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.
[0076] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present application. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.
[0077] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which this application belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the relevant technical literature and the contents of the current disclosure, and unless defined, shall not be overly interpreted as ideal or very formal meanings.
[0078] Figure 5 It is a circuit diagram of a power soft start circuit of the present invention. Figure 6 FIG. 1 is a schematic diagram of the timing of each signal in the multi-bond wire testing method of the present invention. Figure 5 and 6 As shown, a power soft start circuit of the present invention includes: a first transistor 7, a second transistor 14, a third transistor 4, a first four-way switch 10, a second four-way switch 12, a second trigger 13, a logic gate 2 and a low voltage difference linear regulator 15. Among them, the first transistor 7 is used to respond to the reference voltage signal terminal 8 to switch the current path between the fourth node N4 and the first node N1. The second transistor 14 is used to respond to the voltage of the second node N2 to switch the current path between the third node N3 and the ground terminal. The third transistor 4 is used to respond to the voltage of the fourth node N4 to switch the current path between the working power supply terminal VDD and the fifth node N5. The first four-way switch 10 is connected to the reference voltage signal terminal 8 after the first resistor 9 is connected in series, the second end is connected to the first node N1, the third end is connected to the seventh node N7, the fourth end is connected to the output end of a first trigger 11, and the input end of the first trigger 11 is connected to the seventh node N7. Second four-way switch 12 The first end of the second four-way switch 12 is connected to the first node N1, the second end is connected to the third node N3, the third end is connected to the sixth node N6, and the fourth end is connected to the second node N2. The second trigger 13 is connected between the sixth node N6 and the second node N2. Logic gate 2 The output end of the logic gate 2 is connected to the seventh node N7, one input end of the logic gate 2 is connected to the sixth node N6, and the other input end is connected in series with a Schmitt trigger 3 and then connected to the fifth node N5. Low-dropout linear regulator 15 The enable signal access end of the low-dropout linear regulator 15 is connected to the sixth node N6, the reference signal access end is connected to the third node N3, and the output end is connected to a voltage output end 17.
[0079] In a preferred embodiment, the first transistor 7 and the second transistor 14 are both NMOS transistors, but not limited thereto.
[0080] In a preferred embodiment, the third transistors 4 are all PMOS transistors, but not limited thereto.
[0081] In a preferred embodiment, the input terminal of the second flip-flop 13 is connected to the sixth node N6, and the output terminal is connected to the second node N2, but not limited thereto.
[0082] In a preferred embodiment, the present invention further comprises: a first bias current detection unit 5 connected in series between the fourth node N4 and the working power supply terminal VDD, but the present invention is not limited thereto.
[0083] In a preferred embodiment, the present invention further comprises: a second bias current detection unit 6 connected in series between the fifth node N5 and the ground terminal, but not limited thereto.
[0084] In a preferred embodiment, the enable signal emitted by the enable signal access terminal is a pulse signal, the reference voltage emitted by the reference signal access terminal is a ramp voltage signal, the first timing corresponding to the slope region of the reference voltage is included in the second timing of the high level of the pulse signal, and the trigger time of the rising edge of the pulse signal is synchronized with the initial rising trigger time of the ramp voltage signal, but is not limited to this.
[0085] In a preferred embodiment, the second capacitor 18 and the second resistor 19 are connected to the voltage output terminal 17 respectively, but the present invention is not limited thereto.
[0086] In a preferred embodiment, the present invention further includes: a first capacitor 16 connected between the third node N3 and the ground terminal, but not limited thereto.
[0087] The invention realizes a soft start voltage generation mode through two switches and a current comparator. Compared with the prior art, the circuit area of the invention is very small.
[0088] Continue to refer Figure 5 and 6 The present invention also provides a power soft start method, using the above-mentioned power soft start circuit, comprising:
[0089] S110, when the enable signal is low, the low voltage drop linear regulator 15 is turned off, the first four-way switch 10 and the second four-way switch 12 are both turned off, and the second transistor 14 is turned on and the reference signal access terminal is grounded.
[0090] S120, when the enable signal starts to rise, the first four-way switch 10 is disconnected, the second four-way switch 12 is turned on, the second transistor 14 is turned off, and the first bias current is charged to the first capacitor 16 through the first transistor 7. As the voltage at the reference signal access end increases, the threshold voltage of the first transistor 7 decreases until the first transistor 7 is turned off. When the current capacity of the threshold voltage of the first transistor 7 is less than the first bias voltage, the first transistor 7 changes from disconnection to conduction, so that the first four-way switch 10 is turned on, and the reference voltage is charged to the first capacitor 16 through the first resistor 9 until the voltage at the reference signal access end is equal to the reference voltage. Among them, the enable signal sent by the enable signal access end is a pulse signal, and the reference voltage sent by the reference signal access end is a ramp voltage signal. The first timing corresponding to the ramp region of the reference voltage is included in the second timing of the high level of the pulse signal, and the trigger time of the rising edge of the pulse signal is synchronized with the initial rising trigger time of the ramp voltage signal.
[0091] The specific implementation process of the present invention is as follows:
[0092] like Figure 5 and 6As shown, a power soft start circuit of the present invention includes: an enable signal terminal 1, a logic gate 2, a Schmitt trigger 3, a third transistor 4, a first bias current detection unit 5, a second bias current detection unit 6, a first transistor 7, a reference voltage signal terminal 8, a first resistor 9, a first four-way switch 10, a first trigger 11, a second four-way switch 12, a second trigger 13, a second transistor 14, a low voltage difference linear regulator 15, a first capacitor 16, a voltage output terminal 17, a second capacitor 18, and a second resistor 19. Among them, the first transistor 7 is used to switch the current path between the fourth node N4 and the first node N1 in response to the reference voltage signal terminal 8. The second transistor 14 is used to switch the current path between the third node N3 and the ground terminal in response to the voltage of the second node N2. The third transistor 4 is used to switch the current path between the working power supply terminal VDD and the fifth node N5 in response to the voltage of the fourth node N4. First four-way switch 10 The first end of the first four-way switch 10 is connected in series with the first resistor 9 and then connected to the reference voltage signal end 8, the second end is connected to the first node N1, the third end is connected to the seventh node N7, the fourth end is connected to the output end of a first trigger 11, and the input end of the first trigger 11 is connected to the seventh node N7. Second four-way switch 12 The first end of the second four-way switch 12 is connected to the first node N1, the second end is connected to the third node N3, the third end is connected to the sixth node N6, and the fourth end is connected to the second node N2. The second trigger 13 is connected between the sixth node N6 and the second node N2. Logic gate 2 The output end of the logic gate 2 is connected to the seventh node N7, one input end of the logic gate 2 is connected to the sixth node N6, and the other input end is connected in series with a Schmitt trigger 3 and then connected to the fifth node N5. Low-dropout linear regulator 15 The enable signal access end of the low-dropout linear regulator 15 is connected to the sixth node N6, the reference signal access end is connected to the third node N3, and the output end is connected to a voltage output end 17. The first transistor 7 and the second transistor 14 are both NMOS tubes, and the third transistor 4 is both PMOS tubes. The input end of the second trigger 13 is connected to the sixth node N6, and the output end is connected to the second node N2. The first bias current detection unit 5 is connected in series between the fourth node N4 and the working power supply terminal VDD. The second bias current detection unit 6 is connected in series between the fifth node N5 and the ground terminal. The enable signal sent by the enable signal access terminal is a pulse signal, and the reference voltage sent by the reference signal access terminal is a ramp voltage signal. The first timing corresponding to the ramp area of the reference voltage is included by the second timing of the high level of the pulse signal, and the trigger time of the rising edge of the pulse signal is synchronized with the initial rising trigger time of the ramp voltage signal. The second capacitor 18 and the second resistor 19 are respectively connected to the voltage output terminal 17. The first capacitor 16 is connected between the third node N3 and the ground terminal.
[0093] When the present invention is in the startup state, the enable signal is low, the low voltage difference linear regulator 15 is turned off, the first four-way switch 10 and the second four-way switch 12 are both turned off, the second transistor 14 is turned on and the reference signal access terminal is grounded. When the present invention is started, the enable signal starts to rise, the first four-way switch 10 is turned off, the second four-way switch 12 is turned on, the second transistor 14 is turned off, the first bias current charges the first capacitor 16 through the first transistor 7, and as the voltage at the reference signal access terminal increases, the threshold voltage of the first transistor 7 decreases until the first transistor 7 is turned off. When the current capacity of the threshold voltage of the first transistor 7 is less than the first bias voltage, the first transistor 7 changes from being turned off to being turned on, so that the first four-way switch 10 is turned on, and the reference voltage is charged to the first capacitor 16 through the first resistor 9 until the voltage at the reference signal access terminal is equal to the reference voltage.
[0094] In summary, the power soft start circuit of the present invention can realize the function of power soft start, greatly reduce the circuit area cost, and improve the circuit integration.
[0095] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.
Claims
1. A power soft start circuit, characterized in that: include: a first transistor (7) for switching a current path between a fourth node (N4) and a first node (N1) in response to a reference voltage signal terminal (8); a second transistor (14) for switching a current path between a third node (N3) and a ground terminal in response to a voltage at the second node (N2); a third transistor (4) for switching a current path between a working power supply terminal (VDD) and a fifth node (N5) in response to a voltage at the fourth node (N4); a first four-way switch (10), wherein a first end of the first four-way switch (10) is connected in series with a first resistor (9) and then connected to a reference voltage signal end (8), a second end is connected to a first node (N1), a third end is connected to a seventh node (N7), a fourth end is connected to an output end of a first trigger (11), and an input end of the first trigger (11) is connected to the seventh node (N7); a second four-way switch (12), wherein a first end of the second four-way switch (12) is connected to the first node (N1), a second end is connected to the third node (N3), a third end is connected to a sixth node (N6), and a fourth end is connected to the second node (N2); a second flip-flop (13), connected between the sixth node (N6) and the second node (N2); a logic gate (2), wherein the output end of the logic gate (2) is connected to the seventh node (N7), one input end of the logic gate (2) is connected to the sixth node (N6), and the other input end is connected in series with a Schmitt trigger (3) and then connected to the fifth node (N5); as well as A low voltage difference linear regulator (15), wherein the enable signal access terminal of the low voltage difference linear regulator (15) is connected to the sixth node (N6), the reference signal access terminal is connected to the third node (N3), and the output terminal is connected to a voltage output terminal (17).
2. The power soft start circuit according to claim 1, characterized in that: The first transistor (7) and the second transistor (14) are both NMOS transistors.
3. The power soft start circuit according to claim 1, characterized in that: The third transistors (4) are all PMOS transistors.
4. The power soft start circuit according to claim 1, characterized in that: The input terminal of the second flip-flop (13) is connected to the sixth node (N6), and the output terminal is connected to the second node (N2).
5. The power soft start circuit according to claim 1, characterized in that: Also includes: A first bias current detection unit (5) is connected in series between the fourth node (N4) and the working power supply terminal (VDD).
6. The power soft start circuit according to claim 5, characterized in that: Also includes: A second bias current detection unit (6) is connected in series between the fifth node (N5) and the ground terminal.
7. The power soft start circuit according to claim 6, characterized in that: The enable signal emitted by the enable signal access terminal is a pulse signal, the reference voltage emitted by the reference signal access terminal is a ramp voltage signal, the first timing corresponding to the ramp region of the reference voltage is included in the second timing of the high level of the pulse signal, and the trigger time of the rising edge of the pulse signal is synchronized with the initial rising trigger time of the ramp voltage signal.
8. The power soft start circuit according to claim 7, characterized in that: Also includes: The second capacitor (18) and the second resistor (19) are respectively connected to the voltage output terminal (17).
9. The power soft start circuit according to claim 7, characterized in that: Also includes: A first capacitor (16) is connected between the third node (N3) and the ground terminal.
10. A power soft start method, using the power soft start circuit as claimed in claim 9, characterized in that: include: S110, when the enable signal is low, the low voltage difference linear regulator (15) is turned off, the first four-way switch (10) and the second four-way switch (12) are both turned off, and the second transistor (14) is turned on and the reference signal access terminal is grounded; as well as S120, when the enable signal starts to rise, the first four-way switch (10) is disconnected, the second four-way switch (12) is turned on, the second transistor (14) is turned off, and the first bias current is charged to the first capacitor (16) through the first transistor (7). As the voltage at the reference signal access terminal increases, the threshold voltage of the first transistor (7) decreases until the first transistor (7) is turned off. When the current capacity of the threshold voltage of the first transistor (7) is less than the first bias voltage, the first transistor (7) changes from disconnection to conduction, so that the first four-way switch (10) is turned on, and the reference voltage is charged to the first capacitor (16) through the first resistor (9) until the voltage at the reference signal access terminal is equal to the reference voltage.