Oscillator with frequency folding function

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to an oscillator with a frequency folding function, which comprises two operational amplifiers CMP1 to CMP2, a comparator CMP3, a pin RT, three NMOS (N-channel Metal Oxide Semiconductor) tubes MN9-MN11, two PMOS (P-channel Metal Oxide Semiconductor) tubes MP7-MP8, a capacitor CT, a clock generation logic circuit and a ramp voltage generation module, all the devices are sequentially connected to form an oscillator with a frequency folding function; the high-order harmonic energy of the oscillator can be effectively reduced, and the electromagnetic interference of a chip is reduced.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to an oscillator with a frequency folding function. Background Art

[0002] As a key module inside the switching power supply chip, the performance of the oscillator directly affects the stability of the switching power supply output and key indicators such as electromagnetic compatibility (EMC). Therefore, a good oscillator is very important for the switching power supply circuit. The most commonly used control mode in the switching power supply circuit is the pulse width modulation (PWM) mode. The oscillator provides the chip with a stable oscillation frequency and a periodic pulse signal with a duty cycle. As the switching frequency increases, the high-frequency switching waveform generated in this mode contains a large number of high-order harmonic components, which seriously affects the chip's anti-electromagnetic interference ability. The interference noise of the switching power supply is mainly concentrated around the fundamental wave and harmonic signals of the square wave signal generated by the oscillator. The noise amplitude is the key factor in generating EMI. Summary of the invention

[0003] In order to solve the problems existing in the above prior art, the present invention proposes an oscillator with frequency folding function, including: two operational amplifiers CMP1-CMP2, a comparator CMP3, a pin RT, three NMOS tubes MN9-MN11, two PMOS tubes MP7-MP8, a capacitor CT, a clock generation logic circuit and a ramp voltage generation module;

[0004] The positive input terminal of the operational amplifier CMP1 is connected to the voltage Vref1, the reverse input terminal of CMP1 is respectively connected to the source of MN9, the source of MN10, the pin RT and the reverse input terminal of the operational amplifier CMP2, and the output terminal of CMP1 is connected to the gate of MN9; the positive input terminal of CMP2 is connected to the signal, and the output terminal of CM11 is connected to the gate of MN10; the drain of MN9 is respectively connected to the drain of MN10, the gate of MP7, the drain of MP7 and the gate of MP8; the source of MP7 and the source of MP8 are both connected to the power supply voltage; the drain of MP8 is respectively connected to the positive input terminal of the comparator CMP3, the drain of MN11 and the positive electrode of the capacitor CT; the negative electrode of the capacitor CT is grounded; the output terminal of the ramp voltage generating module is connected to the positive input terminal of CMP3; the reverse input terminal of CMP3 is connected to the reference voltage; the output terminal of CMP is connected to the input terminal of the clock generating logic circuit, and the output terminal of the clock generating logic circuit is connected to the gate of MN11; the source of MN11 is grounded.

[0005] Beneficial effects of the present invention:

[0006] The present invention uses a frequency jitter circuit to periodically change the operating frequency of an oscillator square wave signal, thereby reducing the noise amplitude within the signal frequency band, and the effect is more obvious at high frequencies, thereby effectively reducing electromagnetic interference; the present invention can effectively reduce the high-order harmonic energy of the oscillator and reduce the electromagnetic interference of the chip; the present invention has a simple circuit structure, can be integrated inside the chip, and has good engineering practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a structural diagram of an oscillator circuit of the present invention;

[0008] Figure 2 It is a structural diagram of the internal capacitance of the operational amplifier CMP2 of the present invention;

[0009] Figure 3 is a diagram showing the internal circuit structure of the comparator CM3 of the present invention;

[0010] Figure 4 It is a charge-discharge current circuit diagram of the frequency jittering circuit of the present invention;

[0011] Figure 5 This is a circuit diagram for controlling the charging and discharging behavior of the frequency jittering circuit of the present invention;

[0012] Figure 6 It is a simulation waveform diagram of the frequency jittering circuit of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] An oscillator with frequency folding function, such as Figure 1As shown, the device includes two operational amplifiers CMP1-CMP2, a comparator CMP3, a pin RT, three NMOS tubes MN9-MN11, two PMOS tubes MP7-MP8, a capacitor CT, a clock generation logic circuit and a ramp voltage generation module; wherein the positive input terminal of the operational amplifier CMP1 is connected to the voltage Vref1, the reverse input terminal of CMP1 is respectively connected to the source of MN9, the source of MN10, the pin RT and the reverse input terminal of the operational amplifier CMP2, the output terminal of CMP1 is connected to the gate of MN9; the positive input terminal of CMP2 is connected to the signal, and the output terminal of CMP1 is connected to the gate of MN9. The gate of N10; the drain of MN9 is respectively connected to the drain of MN10, the gate of MP7, the drain of MP7 and the gate of MP8; the source of MP7 and the source of MP8 are both connected to the power supply voltage; the drain of MP8 is respectively connected to the positive input of comparator CMP3, the drain of MN11 and the positive electrode of capacitor CT; the negative electrode of capacitor CT is grounded; the output of the ramp voltage generating module is connected to the positive input of CMP3; the reverse input of CMP3 is connected to the reference voltage; the output of CMP is connected to the input of the clock generating logic circuit, and the output of the clock generating logic circuit is connected to the gate of MN11; the source of MN11 is grounded.

[0015] In this embodiment, the positive input terminal of CMP1 is connected to Vref1 with a voltage of 1.2V, the reverse input terminal is connected to the RT pin and the source of NMOS tubes MN9 to MN10, and the inverting input terminal of the operational amplifier CMP2, and the voltage of this node is clamped to about 1.2V; the output terminal of the operational amplifier CMP1 is connected to the gate of the NMOS tube MN9; the operational amplifier CMP2 is a composite input port operational amplifier, the positive input terminal has VRT, VFB, VRC, and its output terminal is connected to the gate of the NMOS tube MN10; the source of the PMOS tubes MP7 and MP8 is connected to the power supply voltage INTVCC; the gates of MP7 and MP8 are connected, and the gate of MP7 is connected to its drain, and the two PMOS tubes form a current mirror structure; the drain of the PMOS tube MP7 is connected to the NMOS The RT pin is connected to the drain of the transistors MN9~MN10; the RT pin is externally connected to a charging resistor, and the charging current IRT flows into the current mirror structure through the NMOS transistor MN9; the drain of the PMOS tube MP8 is connected to the CT capacitor, the positive input terminal of the comparator CMP3, and the drain terminal of the NMOS tube MN11, and the other end of the CT capacitor is grounded; the ramp voltage generating module is connected to the positive input terminal of the comparator CMP3; one reverse input terminal of the comparator CMP3 is connected to the reference voltage Vref2, and the other reverse input terminal is connected to VUP; the output terminal of the comparator CMP3 is connected to the input terminal of the clock generating logic circuit SYNC, and one output terminal of SYNC is connected to the gate of the NMOS tube MN11 to control the opening of MN11 to realize the discharge function of the CT capacitor, and the other output terminal is responsible for outputting the clock signal CLK.

[0016] The principle of the present invention is as follows:

[0017] When the oscillator is in normal working state, the op amp CMP works, its positive terminal is connected to 1.2V, and its negative terminal is connected to the RT pin, so the voltage of the RT pin is about 1.2V. RT is connected to an external charging resistor to generate a constant charging current IRT, and half of the current is copied to the CT capacitor branch through a 2:1 current mirror composed of mirror tubes MP7 and MP8. When the voltage of the CT capacitor is charged to the Vref2 voltage at the negative end of the comparator CMP3, the comparator output flips to a high level. After the comparator output flips, in the subsequent logic circuit, on the one hand, the clock signal CLK is output, and on the other hand, MN11 connected in parallel with the CT capacitor is controlled to turn on to discharge the capacitor CT. The oscillator enters the next cycle. The operating frequency of the oscillator is determined by the following formula:

[0018]

[0019] Among them, V RT is the voltage across the RT resistor, R T The resistor C is used to set the oscillator frequency. T is the capacitance of capacitor CT, V ref2 is the reference voltage.

[0020] like Figure 2 As shown, the operational amplifier CMP2 includes 8 PMOS tubes MP9-MP16, 4 NMOS tubes MN1-MN4, two resistors R1-R2 and two capacitors C1-C2; the sources of MP9 and MP10 are connected to the power supply voltage, the gate of MP9 is connected to the VBIAS signal, and the drain of MP9 is connected to the source of MP11, the source of MP12, the source of MP13 and the drain of MN1 respectively; the gate of MP11 serves as the VRT input terminal, and the drain of MP11 is connected to the source of MP14; the gate of MP12 serves as the VFB input terminal, and the drain of MP12 is connected to the gate of MP15; the gate of MP13 serves as the VRC input terminal, and the drain of MP13 is connected to the source of MP16; The gate of MP14 is connected to the enable terminal EN1, the drain of MP14 is respectively connected to the drain of MP15, the drain of MP16 and the drain of MN2; the gate of MP15 is connected to the enable terminal EN2; the gate of MP16 is connected to the enable terminal EN3; the gate of MN2 is connected to the gate of MN3, and the source of MN2 is grounded; the drain of MN3 is respectively connected to the source of MN1, the gate of MN4, one end of R1, the positive electrode of C2, and the source of MN3 is grounded; the other end of R1 is connected to the positive electrode of C1; the negative electrodes of C1 and C2 are both grounded; the drain of MN4 is connected to the drain of MP10, the source of MN4 is connected to one end of resistor R2 and the gate of MN1, and the other end of resistor R2 is grounded; the gate of MP10 is connected to the VBIAS signal.

[0021] In this embodiment, according to the internal structure of the operational amplifier CMP2, its input end is a check input port, EN1 to EN3 are enable ends for switching of different modes, and VRT, VFB, and VRC signals are connected when EN1 to EN3 are turned on respectively. The inverting input end of CMP2 is connected to the inverting input end of CMP1, so the voltage is also clamped to 1.2V.

[0022] Figure 3 This is the internal structure of the comparator CMP3. CMP3 is located after the CT capacitor and is used to monitor the voltage change on the CT. During normal operation, the VREF2 voltage is 1.2V. When the CT capacitor voltage exceeds 1.2V, the comparator flips.

[0023] Specifically, the circuit structure of the comparator includes: 5 PMOS tubes P1~P5, 4 NMOS tubes M10~M13 and a resistor R3; wherein the source of P1, the source of P2, the source of P3 and the source of P4 are connected to the power supply voltage; the gate of P1 is respectively connected to the gate of P2, the drain of P1, the drain of M10 and the drain of M11; the gate of M10 is connected to the Vref2 signal, and the source of M10 is respectively connected to the source of M11, the source of M12 and the drain of M13; the gate of M11 is connected to the VUP signal; the source of M13 is grounded, and the gate of M13 is connected to the VB signal; the drain of P2 is respectively connected to the gate of P4 and the drain of M12; the gate of M12 is connected to V CT signal; the drain of P4 is respectively connected to the drain of P5 and one end of the resistor R3; the gate of P5 is respectively connected to the source of P5 and the drain of P3; the gate of P3 is connected to the light load signal Light_Load Sig; the other end of the resistor R3 is grounded.

[0024] In order to reduce the EMI of the circuit, the present invention introduces a frequency jitter circuit in the oscillator design. The principle of the frequency jitter circuit is different from the random code frequency jitter of 3415. Instead, it adopts a relatively simple low-frequency triangle wave modulation frequency jitter, that is, a low-frequency 2.5KHz triangle wave reference voltage is input to the VRC terminal of CMP2, and the amplitude is ensured to jitter between 1V and 1.2V, so that the jitter frequency of the final output CLK signal can also be 2.5KHz.

[0025] As attached Figure 4 As shown in the figure, the charging current of the frequency jitter module is determined by the VGS voltage of M7 divided by the R1 resistor. The waveform at the Vs end is a triangular wave. In order to ensure that the rising slope and falling slope of the triangular wave are consistent, the mirror currents set for M8 and M9 are consistent, and the M4 tube to the ground is used as a discharge channel, so that the charging and discharging currents of the triangular wave are finally equal.

[0026] Specifically, the charge-discharge current circuit of the frequency-jittering circuit includes 6 NMOS tubes M1-M6, 3 PMOS tubes M7-M9, a resistor R4 and a capacitor Cs; the drain of M1 is respectively connected to the gate of M1 and the gate of M2 and then connected to the IB signal, and the source of M1 is respectively connected to the source of M2, the source of M5, the source of M6 and the negative electrode of Cs; the drain of M2 is respectively connected to the drain of M7, the gate of M8 and the gate of M9; the source of M7 is connected to one end of the resistor R4 and then connected to the voltage source voltage, and the gate of M7 is respectively connected to the source of M8, the source of M9 and the other end of the resistor R4; the drain of M8 is respectively connected to the drain of M3, the gate of M3 and the gate of M4; the source of M3 is connected to the drain of M5; the gate of M5 is connected to the power supply voltage; the drain of M9 is connected to the positive electrode of Cs and the drain of M4; the source of M4 is connected to the drain of M6, and the gate of M6 is connected to the enable signal EN3.

[0027] Attached Figure 5 In the figure, EN2 is the enable of the frequency jitter module. After it is enabled, the composite comparator starts to work. The voltages of VREF3 and VRC are 1.2V and 1V respectively, which determine the high and low levels of the triangular wave signal. The modulation frequency of the final frequency jitter signal is determined by the high and low levels of the triangular wave signal and the charging current. EN3 is the control logic for charging and discharging. When EN3 is high, it means discharging.

[0028] Specifically, the charge-discharge behavior control circuit of the frequency-jittering circuit is composed of 6 PMOS tubes P6 to P11, 7 NMOS tubes M14 to M20 and a NOT gate; the source of P6, the source of P7 and the source of P8 are all connected to the power supply voltage, the gate of P6 is respectively connected to the gate of P7 and the gate of P8 and then connected to the VB signal, the drain of P6 is respectively connected to the source of P9, the source of P10 and the source of P11; the gate of P9 is connected to the bias voltage Vref3, and the drain of P9 is connected to the drain of M14; the gate of M14 is connected to the enable signal EN3, and the source of M14 is respectively connected to the source of M15, the drain of M17, the gate of M17 and the gate of M18; the gate of P10 is connected to the VRC input terminal, and the drain of P10 is connected to the drain of M15;

[0029] The gate of M15 is connected to the enable signal EN3; the gate of P11 is connected to the drain of M16, and the drain of P11 is respectively connected to the drain of M18, the source of M16 and the gate of M19; the source of M17 is respectively connected to the source of M18, the source of M19 and the source of M20; the gate of M16 is connected to the enable signal EN2; the drain of M7 is respectively connected to the drain of M19 and the gate of M20; the drain of P8 is respectively connected to the input of the NOT gate and the drain of M20; the input of the NOT gate outputs the enable signal EN3.

[0030] In summary, the oscillator of the present invention can provide a periodic pulse signal with a stable oscillation frequency and duty cycle for the chip. Through simple low-frequency triangle wave frequency jitter modulation, a jitter with a frequency of 2.5KHz and an amplitude between 1V and 1.2V is generated on the output signal, which effectively reduces the EMI of the circuit. The simulation waveform of the jitter circuit is shown in FIG. Figure 6 In addition, the oscillator circuit has a simple structure and can be integrated inside the chip, and has good engineering practicability.

[0031] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An oscillator with frequency folding function, characterized in that: It includes: two operational amplifiers CMP1-CMP2, a comparator CMP3, a pin RT, three NMOS tubes MN9-MN11, two PMOS tubes MP7-MP8, a capacitor CT, a clock generation logic circuit and a ramp voltage generation module; The positive input terminal of the operational amplifier CMP1 is connected to the voltage Vref1, the reverse input terminal of CMP1 is respectively connected to the source of MN9, the source of MN10, the pin RT and the reverse input terminal of the operational amplifier CMP2, and the output terminal of CMP1 is connected to the gate of MN9; the positive input terminal of CMP2 is connected to the signal, and the output terminal of CM11 is connected to the gate of MN10; the drain of MN9 is respectively connected to the drain of MN10, the gate of MP7, the drain of MP7 and the gate of MP8; the source of MP7 and the source of MP8 are both connected to the power supply voltage; the drain of MP8 is respectively connected to the positive input terminal of the comparator CMP3, the drain of MN11 and the positive electrode of the capacitor CT; the negative electrode of the capacitor CT is grounded; the output terminal of the ramp voltage generating module is connected to the positive input terminal of CMP3; the reverse input terminal of CMP3 is connected to the reference voltage; the output terminal of CMP is connected to the input terminal of the clock generating logic circuit, and the output terminal of the clock generating logic circuit is connected to the gate of MN11; the source of MN11 is grounded.

2. The oscillator with frequency folding function according to claim 1, characterized in that: The operational amplifier CMP2 is a composite input port operational amplifier, wherein the non-inverting input terminal includes VRT, VFB and VRC.

3. The oscillator with frequency folding function according to claim 2, characterized in that: The operational amplifier CMP2 includes 8 PMOS tubes MP9-MP16, 4 NMOS tubes MN1-MN4, two resistors R1-R2 and two capacitors C1-C2; the sources of MP9 and MP10 are connected to the power supply voltage, the gate of MP9 is connected to the VBIAS signal, and the drain of MP9 is connected to the source of MP11, the source of MP12, the source of MP13 and the drain of MN1 respectively; the gate of MP11 serves as the VRT input terminal, and the drain of MP11 is connected to the source of MP14; the gate of MP12 serves as the VFB input terminal, and the drain of MP12 is connected to the gate of MP15; the gate of MP13 serves as the VRC input terminal, and the drain of MP13 is connected to the source of MP16; The gate of MN4 is connected to the enable terminal EN1, the drain of MP14 is connected to the drain of MP15, the drain of MP16 and the drain of MN2 respectively; the gate of MP15 is connected to the enable terminal EN2; the gate of MP16 is connected to the enable terminal EN3; the gate of MN2 is connected to the gate of MN3, and the source of MN2 is grounded; the drain of MN3 is connected to the source of MN1, the gate of MN4, one end of R1, the positive electrode of C2, and the source of MN3 is grounded; the other end of R1 is connected to the positive electrode of C1; the negative electrodes of C1 and C2 are both grounded; the drain of MN4 is connected to the drain of MP10, the source of MN4 is connected to one end of resistor R2 and the gate of MN1, and the other end of resistor R2 is grounded; the gate of MP10 is connected to the VBIAS signal.

4. The oscillator with frequency folding function according to claim 3, characterized in that: The oscillator also includes a charge-discharge current circuit of the frequency-jittering circuit, the output end of which is connected to the VRC input end of CMP2 to provide a triangular wave reference voltage for the circuit.

5. The oscillator with frequency folding function according to claim 4, characterized in that: The charge-discharge current circuit of the frequency-jittering circuit includes 6 NMOS tubes M1-M6, 3 PMOS tubes M7-M9, a resistor R4 and a capacitor Cs; the drain of M1 is connected to the gate of M1 and the gate of M2 respectively and then connected to the IB signal, the source of M1 is connected to the source of M2, the source of M5, the source of M6 and the negative electrode of Cs respectively; the drain of M2 is connected to the drain of M7, the gate of M8 and the gate of M9 respectively; the source of M7 is connected to one end of the resistor R4 and then connected to the voltage source voltage, the gate of M7 is connected to the source of M8, the source of M9 and the other end of the resistor R4 respectively; the drain of M8 is connected to the drain of M3, the gate of M3 and the gate of M4 respectively; the source of M3 is connected to the drain of M5; the gate of M5 is connected to the power supply voltage; the drain of M9 is connected to the positive electrode of Cs and the drain of M4; the source of M4 is connected to the drain of M6, and the gate of M6 is connected to the enable signal EN3.

6. The oscillator with frequency folding function according to claim 5, characterized in that: The oscillator also includes a charge-discharge behavior control circuit of the frequency jittering circuit, which is connected to the charge-discharge current circuit of the frequency jittering circuit and is used to control the charging and discharging of the charge-discharge current circuit of the frequency jittering circuit.

7. The oscillator with frequency folding function according to claim 6, characterized in that: The charge-discharge behavior control circuit of the frequency-jittering circuit is composed of 6 PMOS tubes P6~P11, 7 NMOS tubes M14~M20 and a NOT gate; the source of P6, the source of P7 and the source of P8 are all connected to the power supply voltage, the gate of P6 is connected to the gate of P7 and the gate of P8 respectively and then connected to the VB signal, the drain of P6 is connected to the source of P9, the source of P10 and the source of P11 respectively; the gate of P9 is connected to the bias voltage Vref3, the drain of P9 is connected to the drain of M14; the gate of M14 is connected to the enable signal EN3, the source of M14 is connected to the source of M15, the drain of M17 and the drain of M17 respectively. The gate of P10 is connected to the VRC input terminal, and the drain of P10 is connected to the drain of M15; the gate of M15 is connected to the enable signal EN3; the gate of P11 is connected to the drain of M16, and the drain of P11 is respectively connected to the drain of M18, the source of M16 and the gate of M19; the source of M17 is respectively connected to the source of M18, the source of M19 and the source of M20; the gate of M16 is connected to the enable signal EN2; the drain of M7 is respectively connected to the drain of M19 and the gate of M20; the drain of P8 is respectively connected to the input of the NOT gate and the drain of M20; the input of the NOT gate outputs the enable signal EN3.

8. The oscillator with frequency folding function according to claim 1, characterized in that: The comparator CMP3 is composed of 5 PMOS tubes P1~P5, 4 NMOS tubes M10~M13 and a resistor R3; the source of P1, the source of P2, the source of P3 and the source of P4 are connected to the power supply voltage; the gate of P1 is connected to the gate of P2, the drain of P1, the drain of M10 and the drain of M11 respectively; the gate of M10 is connected to the Vref2 signal, the source of M10 is connected to the source of M11, the source of M12 and the drain of M13 respectively; the gate of M11 is connected to the VUP signal; the source of M13 is grounded, and the gate of M13 is connected to the VB signal; the drain of P2 is connected to the gate of P4 and the drain of M12 respectively; the gate of M12 is connected to V CT signal; the drain of P4 is respectively connected to the drain of P5 and one end of the resistor R3; the gate of P5 is respectively connected to the source of P5 and the drain of P3; the gate of P3 is connected to the light load signal Light_Load Sig; the other end of the resistor R3 is grounded.

9. The oscillator with frequency folding function according to claim 1, characterized in that: The operating frequency of the oscillator is: Among them, V RT is the voltage across the RT resistor, R T The resistor C is used to set the oscillator frequency. T is the capacitance of capacitor CT, V ref2 is the reference voltage.

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