Data storage, check node data updating and LDPC (Low Density Parity Check) decoding method and system

Abstract

The invention relates to a data storage, check node data updating and LDPC decoding method and system, and belongs to the technical field of wireless communication. The data storage method comprises the following steps: constructing a check matrix H with M rows and N columns, and dividing the check matrix H into a plurality of sub-matrixes with m rows and n columns; storing an element 1 in the check matrix H by using a plurality of dual-port RAMs, wherein the storage rule comprises that the element 1 at the same position in the source sub-matrix and the corresponding sub-matrix needs to be stored in the same dual-port RAM; elements 1 in each row of the check matrix H are grouped in pairs and are respectively stored in different dual-port RAMs; moreover, every two lines of the source sub-matrix and the corresponding sub-matrix form one group, and the element 1 in the source sub-matrix and the corresponding sub-matrix is stored in the same dual-port RAM; and if the line number of the sub-matrix is an odd number, the elements 1 in the remaining lines of the sub-matrix are grouped in pairs and are respectively stored in different dual-port RAMs. According to the invention, the data access speed during information node data updating and check node data updating is improved.

Description

Technical Field

[0001] The present invention belongs to the field of wireless communication technology, and in particular relates to a data storage, check node data update and LDPC decoding method and system. Background Art

[0002] LDPC (Low-Density Parity-Check) code was invented by Robert Gallager in 1963. A block error correction code with a sparse check matrix is ​​proposed in . It is applicable to almost all channels and has become a research hotspot in the coding community in recent years. Its performance is close to the Shannon limit, and its description and implementation are simple, easy to analyze and study theoretically, simple to decode and can be implemented in parallel, and suitable for hardware implementation.

[0003] There are three main types of LDPC decoders: fully parallel decoder, partially parallel decoder, and serial decoder.

[0004] The fully parallel structure can achieve good performance and high data throughput with simple control logic, but when the codeword is long (greater than 1000), this structure will lead to complex implementation and wiring, as well as huge wiring overhead. At the same time, the fully parallel structure will increase area consumption, and the random connection of check nodes and information nodes may also cause routing congestion. If a synchronous circuit is used to ensure signal synchronization, a large number of registers must be added to store data during the iteration process, which further increases resource consumption. Another disadvantage of the parallel structure is that the structure is fixed and can only be used for LDPC codes of a specific check matrix, and the flexibility is not high.

[0005] The shortcoming of the partially parallel structure is that it has certain requirements on the regularity of the check matrix, especially the regularity of the positions of non-zero elements. Many existing partially parallel LDPC decoder designs in the industry are accompanied by corresponding check matrices constructed by special rules. Without the support of this specially constructed check matrix, its application scope is very limited.

[0006] The disadvantages of the serial structure are slow decoding rate and low data throughput, and it cannot be applied to high-speed data interaction systems. Summary of the invention

[0007] The object of the present invention is to provide a data storage, check node data update and LDPC decoding method and system, which partially solves or alleviates the above-mentioned deficiencies in the prior art, and achieves a balance between decoder area, speed, power consumption and performance in the case of a long code length, so as to quickly and effectively realize information exchange between nodes.

[0008] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions:

[0009] A data storage method is applied to update data storage of information nodes and / or check nodes in LDPC decoding, comprising:

[0010] Constructing a check matrix H with M rows and N columns, wherein N is the number of information nodes and M is the number of check nodes; the elements in the check matrix H include 1 and 0, wherein element 1 indicates that the information node and the check node have a connection relationship, and element 0 indicates that the information node and the check node have no connection relationship;

[0011] Divide the check matrix H into several sub-matrices with m rows and n columns, where the sub-matrix in the first row is the source sub-matrix, and the sub-matrices in the remaining rows are obtained by cyclically shifting the corresponding source sub-matrix to the right by n columns row by row; where m is the column weight of the check matrix H, and n is the row weight of the check matrix H;

[0012] Element 1 in the check matrix H is stored using several dual-port RAMs, and the storage rules include:

[0013] The element 1 at the same position in the source submatrix and its corresponding submatrix should be stored in the same dual-port RAM;

[0014] The elements 1 of each row of the check matrix H are grouped into two pairs and stored in different dual-port RAMs respectively;

[0015] Furthermore, the source submatrix and its corresponding submatrix are grouped into groups of two rows each, and the element 1 therein is stored in the same dual-port RAM; if the number of rows of the submatrix is ​​odd, the element 1 in the remaining rows of the submatrix are grouped into groups of two each and stored in different dual-port RAMs.

[0016] The present invention also provides a verification node data updating method, comprising:

[0017] Read n information node data from the information node data storage module;

[0018] Input the data of n information nodes into the CNU computing unit (check node update computing unit) for calculation;

[0019] The result calculated by the CNU computing unit is stored in the verification node data storage module;

[0020] The information node data storage module and / or the check node data storage module adopts the above data storage method to perform data storage.

[0021] As an improvement, the calculation steps of the CNU calculation unit include:

[0022] Perform cumulative multiplication on the highest sign bit of the information node data;

[0023] Obtain the minimum and second minimum values ​​of the remaining bits in the information node data except the highest sign bit.

[0024] As an improvement, the step of obtaining the minimum value and the second minimum value of the remaining bits except the highest sign bit in the information node data includes:

[0025] S321 compares the input information node data in groups of two to obtain the local minimum value between each pair; stores the information node data in the next level register, and indicates the storage location of the local minimum value in the register with a pointer;

[0026] S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the next level register; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the next level register;

[0027] If the local minimum value obtained in the previous level comparison is an odd number, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0028] Using pointers to indicate the storage location of the local minimum in the register;

[0029] Repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

[0030] The present invention also provides an LDPC decoding method, comprising:

[0031] Reading external soft information input values ​​and storing them in the initial soft information memory;

[0032] Reading external soft information from the initial soft information storage device and storing it in the information storage node data storage device;

[0033] Using the above verification node data updating method to update the verification node data;

[0034] Update information node data;

[0035] Repeat the check node data update and the information node data update until the set number of iterations is reached, and store the last information node data update result in the decoding result memory.

[0036] As an improvement, the step of updating the information node data includes:

[0037] Read m check node data from the check node data storage module;

[0038] Input the m check node data into the VNU calculation unit (information node update calculation unit) for calculation;

[0039] The result calculated by the VNU calculation unit is stored in the information node data storage module;

[0040] The information node data storage module and / or the check node data storage module adopts the above data storage method to perform data storage.

[0041] The present invention also provides a verification node data update system, comprising:

[0042] A check node data storage module, used to store check node data using the data storage method according to claim 1;

[0043] The CNU computing unit is used to read n information node data from the information node data storage module and perform verification node data update calculation.

[0044] As an improvement, the CNU computing unit includes:

[0045] A sign accumulation module, used for accumulating the highest sign bit of the information node data;

[0046] The pointer-based minimum and sub-minimum value module is used to obtain the minimum and sub-minimum values ​​of N information node data, specifically including:

[0047] S11 compares the input information node data in groups of two to obtain the local minimum value between each two; stores the information node data in the next level register, and indicates the storage location of the local minimum value in the register with a pointer;

[0048] S12 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the register of the next level;

[0049] If the local minimum value obtained in the previous level comparison is an odd number, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0050] Using pointers to indicate the storage location of the local minimum in the register;

[0051] Repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

[0052] The present invention also provides an LDPC decoding system, comprising:

[0053] An initial soft information memory, used for reading and storing external soft information input values;

[0054] A check node data update system, comprising a check node data storage module for storing check node data using the data storage method of claim 1; and a CNU computing unit for reading n information node data from the information node data storage module and performing check node data update calculations;

[0055] An information node data update system, comprising an information node data storage module for storing information node data using the data storage method of claim 1; and a VNU calculation unit for reading m check node data from the check node data storage module and performing information node data update calculation;

[0056] The decoding result memory is used to store the last information node data update result when the set number of iterations is reached.

[0057] As an improvement, the CNU computing unit includes:

[0058] A sign accumulation module, used for accumulating the highest sign bit of the information node data;

[0059] The pointer-based minimum and sub-minimum value module is used to obtain the minimum and sub-minimum values ​​of N information node data, specifically including:

[0060] S321 compares the input information node data in groups of two to obtain the local minimum value between each pair; stores the information node data in the next level register, and indicates the storage location of the local minimum value in the register with a pointer;

[0061] S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the next level register; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the next level register;

[0062] If the local minimum value obtained in the previous level comparison is an odd number, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0063] Using pointers to indicate the storage location of the local minimum in the register;

[0064] Repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

[0065] The present invention is beneficial in that:

[0066] 1. Data storage method.

[0067] (1) When updating a check node, a clock can read 12 numbers through the dual ports of the RAM, calculate 12 results, and then store the 12 numbers. Reading and writing can be done in address order, and the parallelism of the information node update is 2. The update delay of the check node is shortened by half, and the control logic and address generation logic are very simple.

[0068] (2) During initialization and information node update, since the three source sub-matrices and their respective corresponding sub-matrices are stored in the same RAM in sequence, and due to the principle of relative position invariance, as long as the address that needs to be read and written when the information node corresponding to "1" in the source sub-matrix is ​​updated is known, it can be used as the first address and increased in sequence to complete the update of the information nodes of all corresponding sub-matrices.

[0069] The data storage method provided by the present invention utilizes the highly structured quasi-cyclic structure of the check matrix H, greatly simplifies the control logic and read-write address generation logic at the cost of a small number of registers and data selectors, and reduces the decoding delay, which is beneficial to hardware implementation and brings great convenience to programmers.

[0070] 2. Pointer-based method for finding the minimum and second minimum values.

[0071] In the case of six inputs, the pointer-based algorithm has fewer registers for storing intermediate variables than the classical algorithm, and occupies less resources than the classical algorithm. When the input and output increase, the difference in resource occupancy of the FPGA implementation of the two algorithm results will be even greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0073] Figure 1Schematic diagram of the check matrix H in the present invention;

[0074] Figure 2 Schematic diagram of the segmentation of the neutron matrix of the present invention;

[0075] Figure 3 It is a schematic diagram of the numbering of element 1 in the check matrix H matrix of the existing data storage method;

[0076] Figure 4 A schematic diagram of data storage in an existing data storage method;

[0077] Figure 5 Schematic diagram of the numbering of element 1 in the check matrix H matrix in the present invention;

[0078] Figure 6 This is a schematic diagram of data storage in the present invention;

[0079] Figure 7 It is the "pointer-based" algorithm for finding the minimum value and the second minimum value in the present invention;

[0080] Figure 8 It is a schematic diagram of the structure of CNU in the present invention;

[0081] Fig. 9 It is a schematic diagram of the structure of the LDPC decoding system in the present invention. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0083] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0084] In this document, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0085] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0086] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0087] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0088] Definition of noun:

[0089] LDPC decoding: Low-Density Parity-Check low-density parity check decoding.

[0090] CNU: Check Node Unit, check node update calculation unit.

[0091] VNU: Variable Node Unit, information node update calculation unit.

[0092] Embodiment 1

[0093] Prior art Chinese patent application CN200710118461.9 discloses an efficient LDPC code decoder device and decoding method, which first analyzes the check matrix of the LDPC code to find out the comparison relationship between row weight and column weight; then, based on the above comparison relationship, determines the reuse degree of the check node update unit and the variable node update unit, and groups them to form a unified node update unit, and uses the unified node update unit to process the check node update operation and the variable node update operation.

[0094] In the above-mentioned prior art, there is no change in the data storage method, and when reading data, the effect of full parallel reading cannot be achieved. It focuses on the control of logical computing resources and storage resources, and the operating efficiency is unsatisfactory.

[0095] In order to solve the above technical problems, the present invention provides a data storage method, which is applied to update data storage of information nodes and / or check nodes in LDPC decoding, comprising:

[0096] S101 constructs a check matrix H with M rows and N columns, where N is the number of information nodes and M is the number of check nodes; the elements in the check matrix H include 1 and 0, where element 1 indicates that the information node and the check node are connected, and element 0 indicates that the information node and the check node are not connected.

[0097] The LDPC decoding algorithm is based on the structure of the check matrix H. To simplify the algorithm implementation, the structure of the H matrix must be studied, and a highly structured quasi-cyclic structure can be used. And because the physical parameters such as the number of read and write ports of the memory cannot be changed, the data storage method can be used to achieve the purpose of reading as much valid data as possible with relatively simple logic control.

[0098] The check matrix H is a sparse matrix used to define the parity check rules of the codeword. There are M rows and N columns in the check matrix H, where the M rows correspond to the length of the check code of the LDPC codeword, that is, there are M check nodes. The N rows correspond to the code length of the LDPC codeword, that is, there are N information nodes. There are two types of elements in the check matrix: 1 and 0. When the element is 1, it means that the check node and the information node are connected and need to be calculated. When the element is 0, it means that the check node and the information node are not connected and no calculation is required.

[0099] S102 divides the check matrix H into several sub-matrices of m rows and n columns, where the sub-matrix in the first row is the source sub-matrix, and the sub-matrices in the remaining rows are obtained by cyclically shifting the corresponding source sub-matrix to the right by n columns row by row; where m is the column weight of the check matrix H, and n is the row weight of the check matrix H.

[0100] The so-called row weight refers to the number of elements 1 in each row of the check matrix H. Assuming that the row weight of the check matrix is ​​y, when the check node is updated, each check node is related to y information nodes, and y information node data need to be called to perform y check node update calculations, thereby updating y storage spaces related to the check node.

[0101] The so-called column weight refers to the number of elements 1 in each column of the check matrix H. Assuming that the column weight of the check matrix is ​​x, when the information node is updated, each information node is related to x check nodes, and it is necessary to call x check node data to perform x information node update calculations, thereby updating the x storage spaces related to the information node.

[0102] Based on the above problems, the present invention provides a data storage method, which can have certain regularity in the three steps of LDPC decoding (i.e., initialization, check node update and information node update), so as to simplify the logic, maximize the use of memory resources and reduce delay.

[0103] Specifically, the check matrix H in the present invention is divided into several sub-matrices of m rows and n columns, wherein the sub-matrix located in the first row is the source sub-matrix, and the sub-matrices of the remaining rows are obtained by cyclically shifting the corresponding source sub-matrix to the right by n columns row by row; wherein m is the column weight of the check matrix H, and n is the row weight of the check matrix H.

[0104] like Figure 1 As shown, the check matrix H of 9 rows and 18 columns has a row weight of 6 and a column weight of 3. It is divided into 9 sub-matrices of 3 rows and 3 columns, and each sub-matrix has 3 rows and 6 columns.

[0105] like Figure 2 As shown, H0, H1, and H2 in the first row are source sub-matrices, and the sub-matrices in the remaining rows are obtained by cyclically shifting the source sub-matrices row by row and 6 columns to the right. For example, in the second row, the three sub-matrices are ordered as H2, H0, and H1; in the third row, the three sub-matrices are ordered as H1, H2, and H0, and so on.

[0106] Therefore, the structure of the entire check matrix H can be derived by recording the positions of the "1"s of the source sub-matrices H0, H1, and H2. That is, the "1"s in the last six rows are obtained by cyclically shifting the "1"s in the first three rows by 6 positions to the right. If the "1"s in the first three rows are numbered in the order of appearance, and the "1"s in the last six rows obtained by cyclically shifting the 18 "1"s in the first three rows are numbered the same. It is easy to observe that numbers with the same number have similar reading and writing rules, because their relative positions on the columns of the sub-matrices to which they belong are unchanged.

[0107] Existing storage methods such as Figure 3 , Figure 4 As shown in the figure, the 6 columns of elements 1 after regularization are stored in the order of arrangement by 3 dual-port RAMs. The so-called dual-port RAM refers to a RAM that can read two data at a time. Under the existing storage method, since the 6 1s in the same row are stored in groups of two in 3 dual-port RAMs, the data of 6 information nodes can be read at one time when the check node is updated, and the parallelism is guaranteed. However, when updating the information node, if it is necessary to read S 00 , S 10 , S 20 The elements 1 at the three positions are stored in the same RAM, and the RAM can only read 2 data at a time, so it needs to be read twice to complete, which greatly reduces the running speed.

[0108] It can be seen that in the LDPC decoding process, the process of checking node update (related to row weight) is more regular, the storage space area division is easier, and the control logic is simple. However, this storage method is not conducive to the read and write data and control logic of initialization and information node update (related to column weight), because relative to these two processes, the storage method described above is completely irregular, which will cause the control logic to be very complicated and difficult to implement, and at the same time cause a lot of delay, waste of resources and even timing confusion.

[0109] In order to meet the parallel processing requirements of check node update and information node update, the storage method of the present invention is as follows.

[0110] S103 uses a plurality of dual-port RAMs to store element 1 in the check matrix H. The storage of "element 1" in the present invention actually refers to the storage of information corresponding to the position of element 1 in the check matrix H. For the convenience of description, it is simplified to the storage of "element 1". Please note.

[0111] Specifically, the storage rules include:

[0112] (1) The element 1 at the same position in the source submatrix and its corresponding submatrix must be stored in the same dual-port RAM;

[0113] (2) Grouping elements 1 of each row of the check matrix H into groups of two each, and storing them in different dual-port RAMs;

[0114] (3) Furthermore, the source submatrix and its corresponding submatrix are grouped into groups of two rows each, and the element 1 therein is stored in the same dual-port RAM; if the number of rows of the submatrix is ​​odd, the element 1 in the remaining rows of the submatrix are grouped into groups of two each and stored in different dual-port RAMs.

[0115] Likewise Figure 1~Figure 3 Take the check matrix shown as an example.

[0116] like Figure 5 , Figure 6 As shown in rule (1), the elements 1 at the same position in submatrix H0 need to be stored in the same dual-port RAM, the elements 1 at the same position in submatrix H1 need to be stored in the same dual-port RAM, and the elements 1 at the same position in submatrix H2 need to be stored in the same dual-port RAM. For example, the S in the first row of submatrix H0 00 and S in the second row of the submatrix 32 , their positions in the sub-matrix are the same, so they need to be stored in the same dual-port RAM, namely RAM0.

[0117] The purpose of setting rule (1) is to ensure that the elements 1 in the same column of the check matrix H are not completely in one RAM, because the elements 1 in the source submatrix and its corresponding submatrix are definitely staggered.

[0118] In rule (2), S 00 , S 01 One group is stored in RAM0, S 02 , S 03 One group is stored in RAM1, S 04 , S 05 One group is stored in RAM 2. It is easy to understand that the above storage is for the purpose of reading the data of the required 6 information nodes at one time when the verification node is updated.

[0119] In rule (3), the first row and the second row of the source submatrix H0 of the first row are grouped together, the first row and the second row of the source submatrix H0 of the second row are grouped together, and the first row and the second row of the source submatrix H0 of the third row are grouped together. 00 , S 01 , S 10 , S 11 , S 30 , S 31 , S 40 , S 41 , S 60 , S 61 , S 70 , S 71 All are stored in RAM0.

[0120] Similarly, the first row and the second row of the source submatrix H1 of the first row are grouped together, the first row and the second row of the source submatrix H1 of the second row are grouped together, and the first row and the second row of the source submatrix H1 of the third row are grouped together. 02 , S 03 , S 12 , S 13 , S 32 , S 33 , S 42 , S 43 , S 62 , S 63 , S 72 , S 73 All are stored in RAM1.

[0121] The first row and the second row of the source submatrix H2 of the first row are grouped together, the first row and the second row of the source submatrix H2 of the second row are grouped together, and the first row and the second row of the source submatrix H2 of the third row are grouped together. 04 , S 05 , S 14, S 15 , S 34 , S 35 , S 44 , S 45 , S 64 , S 65 , S 74 , S 75 All are stored in RAM2.

[0122] Since the number of rows in the submatrix is ​​odd, the three submatrices H0, H1, and H2 in each row have a third row left, so there are three rows of elements 1 that are not allocated for storage. The remaining three rows of elements 1 are stored in a RAM in pairs per row, that is, S of the third row of the check matrix 20 , S 21 , S in the sixth row 55 , S 50 , S in the ninth row 84 , S 85 Stored in RAM3; S in the third row 22 , S 23 , S in the sixth row 51 , S 52 , S in the ninth row 80 , S 81 Stored in RAM4; S in the third row 24 , S 25 , S in the sixth row 53 , S 54 , S in the ninth row 82 , S 83 Stored in RAM5.

[0123] After being stored in this way, the three elements 1 in the same column must be stored in two different dual-port RAMs respectively and can be read out at one time, thus avoiding repeated reading.

[0124] It should be noted that Figure 5 It is shown that a large part of the storage space of RAM3, RAM4, and RAM5 is unused because only the information corresponding to the missing "1" in a single row of the submatrix is ​​stored. However, in actual applications, since the check matrix H has 18 rows, it can be divided into 9 groups, each with two rows, and the corresponding information of each group is stored in the same RAM.

[0125] Embodiment 2

[0126] Based on the construction of the check matrix H and the data storage method, the present invention also provides a check node data update method, including:

[0127] S31 reads n information node data from the information node data storage module.

[0128] The row weight of the check matrix H is n, which means that when the check node is updated, it is related to n information node data, so it is necessary to read n information node data from the information node data storage module. According to the data storage method of the first embodiment, n is 6 and is stored in three dual-port RAMs respectively, so the required 6 information node data can be read out in parallel at one time.

[0129] S32 inputs the n information node data into the CNU computing unit for calculation.

[0130] In the iterative calculation process of the LDPC decoding algorithm, the part with the largest amount of calculation and complexity is the information update calculation of the check node. Each check node is related to n information nodes, so the update of the check node requires the calculation of n related values. Specifically, it includes two parts of calculation, namely, the first part accumulates the highest sign bit of the information node data, and the second part obtains the minimum value and the second minimum value of the remaining bits in the information node data except the highest sign bit.

[0131] The first part is to perform cumulative multiplication of the highest sign bit of the information node data, which can be realized by using an XOR gate. The second part is the minimum absolute value of the n-1 information nodes. For the n information nodes related to each check node, it is necessary to find the minimum absolute value of the other n-1 information nodes except the information node. Analyzing its characteristics, a more intuitive explanation is to find the minimum and second minimum absolute values ​​of the information values ​​of these n information nodes. Except for the information node with the smallest absolute value, the result of this step is the second minimum absolute value of the n information nodes, and the results of this step for the other n nodes are the minimum absolute values. How to realize this calculation process with the least resources is one of the key considerations in the present invention.

[0132] Existing algorithms generally use pipeline methods when implemented in FPGA or ASIC. The advantages of this algorithm are that the control and structure are simple and intuitive, which makes it easy to use pipeline structures and achieve high speed. Without taking into account the input register, this structure consumes at least 34 6-bit registers and 12 comparators. Since each level of calculation not only stores all comparison results, but also stores all input values ​​in a pipeline, most of the registers are wasted for the sake of timing consistency of the pipeline structure. When the parallelism of the check node calculation is high or the row weight n of the check matrix is ​​large, the register resource occupancy of this part will be greater.

[0133] In order to solve the above problem, the present invention provides a method for searching for minimum and second minimum values. Since the process of updating the check node to find the minimum value actually has only two output values: the minimum value and the second minimum value among all input numbers, if the position of the minimum value and the second minimum value of all input numbers are found and indicated by a "pointer", then all output data are determined. Therefore, this solution is called a "pointer-based" algorithm for finding the minimum and second minimum values.

[0134] Specific as Figure 7 The example is shown in the figure. In the figure, the minimum and second minimum values ​​of the six inputs are compared and searched through three steps (it can be understood that the more inputs, the more search steps there are) (in the actual application of the LDPC decoder, the second minimum value is used as the output value corresponding to the minimum input, and the minimum value is used as the output value corresponding to other inputs). The specific steps are as follows:

[0135] S321 compares the input information node data in groups of two to obtain the local minimum value between each two; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum value in the register.

[0136] like Figure 7 As shown, the input values ​​are data1 to data6. For the convenience of description, in this example, data1 to data6 are assigned values ​​1 to 6 to search for the minimum value and the second minimum value.

[0137] In this step, 1 and 2 are a group, 3 and 4 are a group, and 5 and 6 are a group. It is easy to understand that after the three groups of comparison D1_1~D1~3, 1, 3, and 5 in the register are local minimum values, which are marked by pointers. In this step, all data are retained, that is, data1~data6 are stored in the register as data1_1~data1_6.

[0138] In this round of comparison, it can be completed through 3 comparison selectors.

[0139] S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, where the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the next level register; the information node data of the four information nodes that are compared with the local minimum value in the same group at the previous level are compared with the failure value again, where the smaller one is the local second minimum value, and the local second minimum value is stored in the next level register; if the local minimum value obtained in the previous level comparison is odd, the single local minimum value and the information node data in the same group are directly stored in the next level register; the pointer is used to indicate the storage location of the local minimum value in the register; repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

[0140] Continuing with the previous example, the two local minimum values ​​1 and 3 are compared D2_1, and 1 once again enters the next-level register as the local minimum and is indicated by a pointer (since 1 and 3 are both "winners" of the previous-level comparison, 1 is actually the local minimum among the four values), while 3 is a failure value and is compared again with 1's previous-level comparator, that is, 2, D2_2. It is easy to understand that 2 enters the next-level register as the local second minimum of the four values.

[0141] This round of comparison can be completed through two comparators and two gates.

[0142] Since there is no comparison object for 5 in this comparison, it enters the next level register together with the previous level comparison object 6.

[0143] This level of registers includes data2_1~data2_4, namely 1, 2, 5, and 6.

[0144] Repeat this step and compare the two local minimum values ​​1 and 5 D3_3, 1 is the minimum value. Then compare 5 and 2, 2 is the second minimum value, and the whole search process ends. The minimum value (Min) is 1 and the second minimum value (2nd_Min) is 2.

[0145] Similarly, in this round of comparison, it can be completed through two comparators and two gates.

[0146] That is to say, ignoring the input register, the implementation of the above algorithm for finding the minimum value uses 18 6-bit registers to store data, 6 3-bit registers to store pointers, 3 comparison selectors, 4 2-way selectors and 4 comparators.

[0147] Table 1 Comparison of the structure and resource usage of the existing algorithm and the "pointer-based" algorithm of the present invention Traditional algorithm + traditional storage structure "Pointer-based" algorithm + storage structure of the present invention Number of inputs and outputs 6 6 Comparator 12 7 Data Register 34 18 Address Register 0 6 Multiplexer (2 to 1) 0 7 Resource Occupancy Slices 170 166

[0148] The results of the source program compilation of the existing algorithm and the "pointer-based" algorithm described in VHDL language are synthesized using Xilinx FPGA devices. The results are shown in Table 1. For the same six inputs, the number of registers for storing intermediate variables in the "pointer-based" algorithm is less than the registers required by the classic algorithm, and the resource occupation is less than that of the classic algorithm. When the input and output increase, the difference in resource occupation of the FPGA implementation of the two algorithm results will be greater.

[0149] S33 stores the result calculated by the CNU calculation unit in the check node data storage module.

[0150] After the calculation is completed, the calculation result can be stored in the verification node data storage module.

[0151] The information node data storage module and / or the check node data storage module perform data storage using the data storage method described in Embodiment 1. The specific steps of data storage are shown in Embodiment 1 of the present invention and will not be described in detail here.

[0152] Embodiment 3

[0153] Based on the data storage method provided in the first embodiment and the check node data update method provided in the second embodiment, the present invention further provides an LDPC decoding method, including:

[0154] S1 reads the external soft information input value and stores it in the initial soft information memory.

[0155] The external soft information input value is stored in the initial soft information memory MEM for Yn1 or MEM for Yn1 according to the ping-pong rule.

[0156] S2 reads the external soft information from the initial soft information storage and stores it in the information storage node data storage.

[0157] Start the LDPC decoding initialization process. Read the initial soft information from the initial soft information memory and store it in the corresponding information node data memory. The specific data storage method is shown in Example 1 and will not be described here.

[0158] S3 updates the verification node data.

[0159] For the specific updating steps, please refer to Example 2, which will not be repeated here.

[0160] S4 updates the information node data. The specific steps include:

[0161] S41 reads m check node data from the check node data storage module.

[0162] The column weight of the check matrix H is m, which means that when the information node is updated, it is related to m check node data, so it is necessary to read m check node data from the check node data storage module. According to the data storage method of the first embodiment, m is 3 and is stored in two dual-port RAMs respectively, so the required 3 check node data can be read out in parallel at one time.

[0163] S42 inputs the m check node data into the VNU computing unit for calculation.

[0164] The calculation of information node update itself is not technically difficult, but the difficulty lies in the call of data. The data storage method in the first embodiment solves this problem, so the update calculation module of the information node is composed of a large number of multiplexers and 4-input adders (for binary numbers, XOR gates can be used to implement it).

[0165] S43 stores the result calculated by the VNU calculation unit in the information node data storage module; wherein the information node data storage module and / or the check node data storage module adopts the data storage method of the first embodiment to perform data storage.

[0166] S5 repeats the check node data update and the information node data update until the set number of iterations is reached, and stores the last information node data update result in the decoding result memory.

[0167] Embodiment 4

[0168] The present invention also provides a verification node data update system, comprising:

[0169] A check node data storage module, used to store check node data using the data storage method according to claim 1;

[0170] The CNU computing unit is used to read n information node data from the information node data storage module and perform verification node data update calculation; Figure 8 As shown, it specifically includes:

[0171] A sign accumulation module, used for accumulating the highest sign bit of the information node data;

[0172] The pointer-based minimum and sub-minimum value module is used to obtain the minimum and sub-minimum values ​​of N information node data, specifically including:

[0173] S11 compares the input information node data in groups of two to obtain the local minimum value between each two; stores the information node data in the next level register, and indicates the storage location of the local minimum value in the register with a pointer;

[0174] S12 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the register of the next level;

[0175] If the local minimum value obtained in the previous level comparison is an odd number, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0176] Using pointers to indicate the storage location of the local minimum in the register;

[0177] Repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

[0178] Figure 8 In the CNU computing unit shown, the input control signals include an enable signal "EN", a reset signal "RESET" and a clock signal "CLK". Six 7-bit inputs S1 (6 downto 0) ~ S6 (6 downto 0), the highest sign bit of each input, namely SIGN_S1 ~ SIGN_S6, is input into the sign accumulation module, and the last 6 bits, namely S1 (5 downto 0) ~ S6 (5 downto 0), are input into the pointer-based minimum sub-minimum value finding module. The outputs SIGN_S1_OUT ~ SIGN_S6_OUT of the sign accumulation module and the outputs S1_OUT ~ S6 ~ OUT of the pointer-based minimum sub-minimum value finding module are then combined into the six 7-bit outputs S1_OUT (6 downto 0) ~ S6_OUT (6 downto 0) of the entire CHU computing unit.

[0179] Embodiment 5

[0180] like Fig. 9 As shown, the present invention also provides an LDPC decoding system, comprising:

[0181] The initial soft information memory is used to read and store external soft information input values. In this embodiment, there are two parallel initial soft information memories, namely, MEM for Yn1 or MEM for Yn2.

[0182] The check node data update system comprises a check node data storage module for storing check node data using the data storage method of claim 1; and a CNU computing unit for reading n information node data from the information node data storage module and performing check node data update calculation.

[0183] The specific structure of the CNU computing unit is as follows Figure 8 As shown, specifically including:

[0184] A sign accumulation module, used for accumulating the highest sign bit of the information node data;

[0185] The pointer-based minimum and sub-minimum value module is used to obtain the minimum and sub-minimum values ​​of N information node data, specifically including:

[0186] S321 compares the input information node data in groups of two to obtain the local minimum value between each pair; stores the information node data in the next level register, and indicates the storage location of the local minimum value in the register with a pointer;

[0187] S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the next level register; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the next level register;

[0188] If the local minimum value obtained in the previous level comparison is an odd number, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0189] Using pointers to indicate the storage location of the local minimum in the register;

[0190] Repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

[0191] An information node data update system comprises an information node data storage module for storing information node data using the data storage method of claim 1; and a VNU calculation unit for reading m check node data from the check node data storage module and performing information node data update calculation.

[0192] The decoding result memory is used to store the last information node data update result when the set number of iterations is reached, and finally output the LDPC decoding result Decode Data output.

[0193] The control module is used to send instructions to the above modules, including an enable signal "EN", a reset signal "RESET", a clock signal "CLK", a ready signal "READY", and an addressing signal "addr".

[0194] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0195] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a computer terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0196] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A data storage method, applied to update data of information nodes and / or check nodes in LDPC decoding, characterized in that include: Constructing a check matrix H with M rows and N columns, wherein N is the number of information nodes and M is the number of check nodes; the elements in the check matrix H include 1 and 0, wherein element 1 indicates that the information node and the check node have a connection relationship, and element 0 indicates that the information node and the check node have no connection relationship; Divide the check matrix H into several sub-matrices with m rows and n columns, where the sub-matrix in the first row is the source sub-matrix, and the sub-matrices in the remaining rows are obtained by cyclically shifting the corresponding source sub-matrix to the right by n columns row by row; where m is the column weight of the check matrix H, and n is the row weight of the check matrix H; Element 1 in the check matrix H is stored using several dual-port RAMs, and the storage rules include: The element 1 at the same position in the source submatrix and its corresponding submatrix should be stored in the same dual-port RAM; The elements 1 of each row of the check matrix H are grouped into two pairs and stored in different dual-port RAMs respectively; Furthermore, the source submatrix and its corresponding submatrix are grouped into groups of two rows each, and the element 1 therein is stored in the same dual-port RAM; if the number of rows of the submatrix is ​​odd, the element 1 in the remaining rows of the submatrix are grouped into groups of two each and stored in different dual-port RAMs.

2. A verification node data updating method, characterized in that include: Read n information node data from the information node data storage module; Input the data of n information nodes into the CNU computing unit for calculation; The result calculated by the CNU computing unit is stored in the verification node data storage module; Wherein, the information node data storage module and / or the check node data storage module adopts the data storage method according to claim 1 to perform data storage.

3. A verification node data updating method according to claim 2, characterized in that The calculation steps of the CNU calculation unit include: Perform cumulative multiplication on the highest sign bit of the information node data; Obtain the minimum and second minimum values ​​of the remaining bits in the information node data except the highest sign bit.

4. A method for updating check node data according to claim 3, characterized in that The steps of obtaining the minimum value and the second minimum value of the remaining bits except the highest sign bit in the information node data include: S321 compares the input information node data in groups of two to obtain the local minimum value between each pair; stores the information node data in the next level register, and indicates the storage location of the local minimum value in the register with a pointer; S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the next level register; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the next level register; If the local minimum value obtained in the previous level comparison is an odd number, the single local minimum value and the information node data of the same group are directly stored in the next level register; Using pointers to indicate the storage location of the local minimum in the register; Repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

5. A LDPC decoding method, characterized in that include: Reading external soft information input values ​​and storing them in the initial soft information memory; Reading external soft information from the initial soft information storage device and storing it in the information storage node data storage device; Using the check node data updating method described in any one of claims 2 to 4 to update the check node data; Update information node data; Repeat the check node data update and the information node data update until the set number of iterations is reached, and store the last information node data update result in the decoding result memory.

6. The LDPC decoding method according to claim 5, characterized in that The step of updating the information node data comprises: Read m check node data from the check node data storage module; Input the m check node data into the VNU computing unit for calculation; The result calculated by the VNU calculation unit is stored in the information node data storage module; Wherein, the information node data storage module and / or the check node data storage module adopts the data storage method according to claim 1 to perform data storage.

7. A verification node data update system, characterized in that include: A check node data storage module, used to store check node data using the data storage method according to claim 1; The CNU computing unit is used to read n information node data from the information node data storage module and perform verification node data update calculation.

8. A check node data update system according to claim 7, characterized in that The CNU computing unit comprises: A sign accumulation module, used for accumulating the highest sign bit of the information node data; The pointer-based minimum and sub-minimum value module is used to obtain the minimum and sub-minimum values ​​of N information node data, specifically including: S11 compares the input information node data in groups of two to obtain the local minimum value between each two; stores the information node data in the next level register, and indicates the storage location of the local minimum value in the register with a pointer; S12 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the register of the next level; If the local minimum value obtained in the previous level comparison is an odd number, the single local minimum value and the information node data of the same group are directly stored in the next level register; Using pointers to indicate the storage location of the local minimum in the register; Repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

9. An LDPC decoding system, characterized in that include: An initial soft information memory, used for reading and storing external soft information input values; A check node data update system, comprising a check node data storage module for storing check node data using the data storage method of claim 1; and a CNU computing unit for reading n information node data from the information node data storage module and performing verification node data update calculation; An information node data updating system, comprising an information node data storage module for storing information node data using the data storage method of claim 1; and a VNU calculation unit for reading m check node data from the check node data storage module and performing information node data update calculation; The decoding result memory is used to store the last information node data update result when the set number of iterations is reached.

10. An LDPC decoding system according to claim 9, characterized in that The CNU computing unit comprises: A sign accumulation module, used for accumulating the highest sign bit of the information node data; The pointer-based minimum and sub-minimum value module is used to obtain the minimum and sub-minimum values ​​of N information node data, specifically including: S11 compares the input information node data in groups of two to obtain the local minimum value between each two; stores the information node data in the next level register, and indicates the storage location of the local minimum value in the register with a pointer; S12 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the register of the next level; If the local minimum value obtained in the previous level comparison is an odd number, the single local minimum value and the information node data of the same group are directly stored in the next level register; Using pointers to indicate the storage location of the local minimum in the register; Repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

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