Connection method and interconnection device for silicon optical integrated chip and high-frequency transition substrate

Abstract

The invention relates to a connection method of a silicon optical integrated chip and a high-frequency transition substrate and an interconnection device, and the method comprises the following steps: calculating the geometric dimension of the interconnection device through electromagnetic field simulation analysis software, and enabling the impedance of the interconnection device, the silicon optical integrated chip and the transition transmission substrate to be matched; the interconnection substrate of the interconnection device is sucked in a vacuum mode, so that the salient points on the interconnection substrate are adjusted to be aligned with the bonding pad of the silicon optical integrated chip and the bonding pad mark of the transition transmission substrate; welding the salient points and the bonding pads after mark alignment to realize electrical connection of the interconnection device, the silicon optical integrated chip and the transition transmission substrate; and a control signal is loaded to the silicon optical integrated chip, so that the silicon optical integrated chip is actively coupled and aligned, and finally photoelectric integrated packaging of the silicon optical integrated chip is completed. The coupling alignment of the optical fiber and the optical waveguide structure of the silicon optical integrated chip is realized, meanwhile, the interconnection performance between the silicon optical integrated chip and the transition transmission substrate can be improved, the problem of impedance mismatching is avoided, and the signal transmission rate is improved.

Description

Technical Field

[0001] The present application relates to the field of optoelectronic co-packaging, and in particular to a connection method and interconnection device between a silicon photonic integrated chip and a high-frequency transition substrate. Background Art

[0002] The purpose of packaging silicon photonic integrated chips is to protect the chips, enhance electrical and thermal performance, and achieve effective connection between the chips and external circuits.

[0003] In the related technology, method one, for the packaging of traditional silicon photonic integrated chips, firstly, the chip and the transition transmission substrate (high-frequency circuit board) are mounted on a carrier, and then the gold wire bonding technology is used to realize the signal interconnection between the chip electrode and the transition transmission substrate. Method two, when the silicon photonic integrated chip and the transition transmission substrate are packaged by using the flip-chip process for signal transmission.

[0004] However, in method one, at the interconnection between the silicon photonic integrated chip and the transition transmission substrate, as the frequency increases, the parasitic inductance effect of the gold wire bonding will be significantly aggravated, resulting in impedance mismatch. Therefore, the gold wire interconnection is difficult to support higher signal transmission rates. In method two, when the flip-chip process is used for signal transmission packaging, the subsequent optical fiber coupling alignment cannot be performed in actual operation. Summary of the invention

[0005] The present application provides a connection method and interconnection device for a silicon photonic integrated chip and a high-frequency transition substrate, so that the silicon photonic integrated chip can be mounted on a carrier board, and the coupling alignment of the optical fiber and the optical waveguide structure of the silicon photonic integrated chip can be achieved. At the same time, the interconnection performance between the silicon photonic integrated chip and the transition transmission substrate (high-frequency circuit board) can be improved, and the problem of impedance mismatch can be avoided, thereby improving the signal transmission rate.

[0006] In a first aspect, an embodiment of the present application provides a method for connecting a silicon photonic integrated chip to a high-frequency transition substrate, which comprises the following steps:

[0007] The geometric dimensions of the interconnection device are calculated using electromagnetic field simulation analysis software to match the impedance of the interconnection device, silicon photonic integrated chip, and transition transmission substrate;

[0008] Vacuum suction of the interconnection substrate of the interconnection device to adjust the alignment of the bumps on the interconnection substrate with the pads of the silicon photonic integrated chip and the pad marks of the transition transmission substrate;

[0009] Welding the bumps and pads after mark alignment to achieve electrical connection between the interconnection device, silicon photonic integrated chip and transition transmission substrate;

[0010] Loading control signals to the silicon photonic integrated chip enables active coupling alignment of the silicon photonic integrated chip, and finally completes the optoelectronic integrated packaging of the silicon photonic integrated chip.

[0011] In combination with the first aspect, in one embodiment, the vacuum suction of the interconnection substrate of the interconnection device to adjust the alignment of the bumps on the interconnection substrate with the pads of the silicon photonic integrated chip and the pad marks of the transition transmission substrate includes:

[0012] The interconnection substrate of the interconnection device is vacuum-sucked by the suction nozzle of the flip-chip welding equipment to adjust the alignment between the bumps on the interconnection substrate and the pads of the silicon photonic integrated chip and the pad marks of the transition transmission substrate.

[0013] In combination with the first aspect, in one embodiment, welding the bumps and pads after the mark alignment to achieve electrical connection between the interconnection device, the silicon photonic integrated chip and the transition transmission substrate includes:

[0014] The bumps and pads after mark alignment are reflow soldered to achieve electrical connection between the interconnect device, silicon photonic integrated chip and transition transmission substrate.

[0015] In combination with the first aspect, in one implementation, before the control signal is loaded to the silicon photonic integrated chip to align the active coupling of the silicon photonic integrated chip and finally complete the optoelectronic integrated packaging of the silicon photonic integrated chip, the method includes:

[0016] Place the interconnection device, the silicon photonic integrated chip and the transition transmission substrate on a coupling platform.

[0017] In combination with the first aspect, in one embodiment, before vacuum suctioning the interconnection substrate of the interconnection device to adjust the alignment of the bumps on the interconnection substrate with the pads of the silicon photonic integrated chip and the pad marks of the transition transmission substrate, the method includes:

[0018] Place the silicon photonic integrated chip and the transition transmission substrate upright on the carrier so that the radio frequency electrodes of the silicon photonic integrated chip and the transition transmission substrate are aligned.

[0019] In combination with the first aspect, in one embodiment, after the silicon photonic integrated chip and the transition transmission substrate are placed upright on the carrier to align the radio frequency electrodes of the silicon photonic integrated chip and the transition transmission substrate, the method further includes:

[0020] The silicon photonic integrated chip and the transition transmission substrate are glued and cured on the carrier.

[0021] In combination with the first aspect, in one embodiment, the geometric dimensions include the thickness of the interconnect substrate, the S pole width, the G pole width and the distance between the G pole and the S pole of the electrical transmission line, and the height and diameter of the bump.

[0022] In combination with the first aspect, in one implementation, the pad electrode of the silicon photonic integrated chip is a GSG type electrode, and the pad electrode of the transition transmission substrate is a GSG type electrode.

[0023] In combination with the first aspect, in one implementation, the pad electrode of the silicon photonic integrated chip is a GS-type electrode, and the pad electrode of the transition transmission substrate is a GSG-type electrode.

[0024] In a second aspect, an embodiment of the present application provides an interconnection device, comprising:

[0025] An interconnection substrate, wherein an electric transmission line is arranged on one side of the interconnection substrate, and bumps are fixed at both ends of the electric transmission line. The bumps at both ends of the electric transmission line are used to connect between the electrodes correspondingly connected to the silicon photonic integrated chip and the transition transmission substrate.

[0026] The beneficial effects brought by the technical solution provided in the embodiments of the present application include:

[0027] Compared with the traditional interconnection method through gold wire bonding, the interconnection device between the silicon photonic integrated chip and the transition transmission substrate can significantly improve the impedance mismatch problem, thereby improving the interconnection performance between the silicon photonic integrated chip and the transition transmission substrate and supporting a higher signal transmission rate. The signal interconnection between the silicon photonic integrated chip electrode and the transition transmission substrate can be realized, and the control signal is loaded to the chip under the condition of the silicon photonic integrated chip being mounted upright, and finally the active coupling alignment of the silicon photonic integrated chip is realized, avoiding the problem that the flip-chip silicon photonic integrated chip is difficult to realize the coupling alignment of the optical fiber and the chip optical waveguide structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 Schematic diagram of gold wire bonding interconnection between silicon photonic integrated chip and transition transmission substrate;

[0030] Figure 2 Schematic diagram of flip-chip interconnection between silicon photonic integrated chip and transition transmission substrate;

[0031] Figure 3 A schematic diagram of interconnecting a silicon photonic integrated chip and a transition transmission substrate through an interconnection device;

[0032] Figure 4 A schematic diagram of a silicon photonic integrated chip with a GSG type electrode and a transition transmission substrate with a GSG type electrode being interconnected via an interconnection device;

[0033] Figure 5 Schematic diagram of the interconnection of a silicon photonic integrated chip with GS-type electrodes and a transition transmission substrate with GSG-type electrodes through an interconnection device.

[0034] In the figure: 1. Carrier board; 2. Silicon photonic integrated chip; 3. Solder pad; 4. Transition transmission substrate; 5. Optical fiber; 6. Gold wire; 7. Bump; 8. Interconnection substrate. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] It is important to understand that Figure 1 As shown, for the packaging of the traditional silicon photonic integrated chip 2, the silicon photonic integrated chip 2 and the transition transmission substrate 4 (high-frequency circuit board) are first mounted on a carrier 1, and then the gold wire bonding technology is used to realize the signal interconnection between the electrodes of the silicon photonic integrated chip 2 and the transition transmission substrate 4 (high-frequency circuit board).

[0037] Normally, the impedance of the RF signal in the silicon photonic integrated chip 2 is 50Ω for single-end or 100Ω for differential. However, at the interconnection between the silicon photonic integrated chip 2 and the transition transmission substrate 4 (high-frequency circuit board), as the frequency increases, the parasitic inductance effect of the gold wire bonding will also be significantly aggravated, resulting in impedance mismatch. Therefore, the traditional gold wire 6 interconnection is difficult to support higher signal transmission rates.

[0038] However, if Figure 2 As shown, when the silicon photonic integrated chip 2 and the transition transmission substrate 4 (high-frequency circuit board) are subjected to the flip-chip process for signal transmission and packaging, the subsequent optical fiber coupling alignment cannot be performed in actual operation. Because the interconnection electrodes and the optical waveguide structure of the silicon photonic integrated chip 2 are designed on the same surface, when the electrodes of the silicon photonic integrated chip 2 are flip-chip interconnected with the transition transmission substrate 4 (high-frequency circuit board), the electrodes and the optical waveguide structure of the silicon photonic integrated chip 2 are facing downward at the same time. In this way, the real-time position monitoring system cannot locate the optical waveguide structure, and thus cannot achieve the coupling alignment between the optical fiber 5 and the optical waveguide structure of the silicon photonic integrated chip 2.

[0039] To achieve the above objectives, the embodiments of the present application provide a connection method and an interconnection device between a silicon photonic integrated chip and a high-frequency transition substrate, so that the silicon photonic integrated chip 2 is mounted on the carrier 1, and the coupling alignment of the optical fiber 5 and the optical waveguide structure of the silicon photonic integrated chip 2 is realized. At the same time, the interconnection performance between the silicon photonic integrated chip 2 and the transition transmission substrate 4 (high-frequency circuit board) can be improved, and the impedance mismatch problem can be avoided, thereby improving the signal transmission rate.

[0040] On the one hand, if Figure 3 , Figure 4 and Figure 5 As shown, an embodiment of the present application provides an interconnection device for interconnecting a silicon photonic integrated chip and a transition transmission substrate, which includes: an interconnection substrate 8, the interconnection substrate 8 is above the silicon photonic integrated chip 2 and the transition transmission substrate 4, the interconnection substrate 8 is used to electrically connect with the silicon photonic integrated chip 2 and the transition transmission substrate 4, an electrical transmission line is arranged on the interconnection substrate 8, and a bump 7 is arranged on the electrode of the electrical transmission line, and the bump 7 is electrically connected to the silicon photonic integrated chip 2 and the pad 3 of the transition transmission substrate 4.

[0041] In some embodiments, such as Figure 4 As shown, the pad 3 of the silicon photonic integrated chip 2 is a GSG type electrode (ground signal ground plane waveguide plane RF electrode), and the pad 3 of the transition transmission substrate 4 is a GSG type electrode (ground signal ground plane waveguide plane RF electrode), that is, the interconnection device is a GSG-GSG model, and six bumps 7 are arranged on one side of the interconnection substrate 8, and the bumps 7 are electrically connected to the pads 3 corresponding to the silicon photonic integrated chip 2 and the transition transmission substrate 4. That is, the number of electrical transmission lines on the interconnection substrate 8 is three, and the bumps at both ends of the first electrical transmission line are connected to the first G pole of the silicon photonic integrated chip 2 and the first G pole of the transition transmission substrate 4, the bumps at both ends of the second electrical transmission line are connected to the S pole of the silicon photonic integrated chip 2 and the S pole of the transition transmission substrate 4, and the bumps at both ends of the third electrical transmission line are connected to the second G pole of the silicon photonic integrated chip 2 and the second G pole of the transition transmission substrate 4.

[0042] In some embodiments, such as Figure 5 As shown, the pad 3 of the silicon photonic integrated chip 2 is a GS-type electrode (ground plane waveguide planar RF electrode), and the pad 3 of the transition transmission substrate 4 is a GSG-type electrode (ground signal ground plane waveguide planar RF electrode). That is, the interconnection device is a GS-GSG model, and five bumps 7 are provided on one side of the interconnection substrate 8, and the bumps 7 are electrically connected to the pads 3 corresponding to the silicon photonic integrated chip 2 and the transition transmission substrate 4. Among them, the two Gs in the GSG-type electrode are connected together with the G in the GS-type electrode. That is, the number of electrical transmission lines on the interconnection substrate 8 is two, and the bumps at both ends of the first electrical transmission line are connected to the S pole of the silicon photonic integrated chip 2 and the S pole of the transition transmission substrate 4, and the second electrical transmission line has a branch, and the bumps at both ends of the branch are connected to the two G poles of the transition transmission substrate 4, and the bumps at the trunk end are connected to the G electrode of the silicon photonic integrated chip 2.

[0043] The silicon photonic integrated chip 2 and the transition transmission substrate 4 are fixed on the carrier 1 , and both the silicon photonic integrated chip 2 and the transition transmission substrate 4 are provided with pads 3 .

[0044] like Figure 3As shown, the interconnection substrate 8 is a thin film circuit of a quartz glass substrate or a ceramic substrate. Generally, the middle layer of the interconnection substrate 8 is a quartz glass substrate or a ceramic substrate, and an electric transmission line is arranged on its bottom surface. A bump 7 is arranged on the electric transmission line for electrical connection between the silicon photonic integrated chip 2 and the transition transmission substrate 4, and its top surface is gold-plated as grounding. When in use, the top surface of the interconnection substrate 8 is vacuum-sucked by the suction nozzle of the flip-chip welding device so that its bottom surface faces downward, and the interconnection substrate 8 is adjusted so that the bump 7 is aligned with the mark on the pad 3 of the silicon photonic integrated chip 2 and the transition transmission substrate 4, and reflow soldering is performed after the mark is aligned, so as to achieve electrical connection. The thickness of the quartz glass substrate or ceramic substrate, the S pole width of the electric transmission line, the G pole width and the distance between the G pole and the S pole, and the height and diameter of the bump 7 can be calculated by electromagnetic simulation software, so that the impedance of the silicon photonic integrated chip 2 and the interconnection device and the transition transmission substrate 4 is matched.

[0045] Compared with gold wire bonding, gold wire bonding will have parasitic inductance effect, causing impedance mismatch problems, while the electrical transmission line on the interconnect substrate 8 itself is calculated and designed according to the impedance of the silicon photonic integrated chip 2, so it avoids the impedance mismatch problem and thus improves the signal transmission rate.

[0046] On the other hand, an embodiment of the present application further provides a method for connecting a silicon photonic integrated chip and a transition transmission substrate based on the above interconnection device, comprising the following steps:

[0047] Step 1: Place the silicon photonic integrated chip 2 and the transition transmission substrate 4 upright on the carrier 1, align the radio frequency electrodes of the silicon photonic integrated chip 2 and the transition transmission substrate 4, and glue and cure the silicon photonic integrated chip 2 and the transition transmission substrate 4;

[0048] Step 2: Place the carrier 1 with the silicon photonic integrated chip 2 and the transition transmission substrate 4 on the machine platform of the flip-chip welding equipment, vacuum-absorb the interconnection substrate 8 through the suction nozzle of the flip-chip welding equipment, adjust the interconnection substrate 8 so that its bumps 7 are aligned with the marks on the pads 3 of the silicon photonic integrated chip 2 and the transition transmission substrate 4, and perform reflow welding after the marks are aligned to achieve electrical connection.

[0049] Step three: Then place the whole on a coupling platform and load a control signal to the silicon photonic integrated chip 2, thereby realizing active coupling alignment of the silicon photonic integrated chip 2, and finally realizing optoelectronic integrated packaging of the silicon photonic integrated chip 2.

[0050] Among them, the interconnection device between the silicon photonic integrated chip 2 and the transition transmission substrate 4 can significantly improve the impedance mismatch problem compared to the method of interconnection through gold wire bonding, thereby improving the interconnection performance between the silicon photonic integrated chip 2 and the transition transmission substrate 4 and supporting a higher signal transmission rate. The signal interconnection between the electrodes of the silicon photonic integrated chip 2 and the transition transmission substrate 4 can be realized, and the active coupling alignment of the silicon photonic integrated chip 2 can be finally realized by combining the loading of the control signal to the chip under the condition that the silicon photonic integrated chip 2 is upright. The problem of coupling alignment between the optical fiber 5 and the optical waveguide structure of the silicon photonic integrated chip 2 is avoided when the flip-chip silicon photonic integrated chip 2 is difficult to realize.

[0051] Among them, the impedance matching of the GSG-type electrode and the GS-type electrode of the silicon photonic integrated chip 2 includes two situations: under single-ended signals, the impedance of the GSG-type electrode and the GS-type electrode is 50Ω, and under differential signals, the impedance of the GSG-type electrode and the GS-type electrode is 100Ω. While keeping the impedance of the GSG-type electrode and the GS-type electrode unchanged, the geometric dimensions of the interconnection device are calculated through electromagnetic field simulation analysis software according to the geometric dimensions of the GSG-type electrode and the GS-type electrode, including the thickness of the interconnection device, the S-pole width of the electric transmission line, the G-pole width and the spacing between the G-pole and the S-pole, and the height and diameter of the bump 7, so that the impedance of the silicon photonic integrated chip 2 and the interconnection device and the high-speed transition transmission substrate 4 are matched.

[0052] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0053] It should be noted that, in this application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0054] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A method for connecting a silicon photonic integrated chip to a high-frequency transition substrate, characterized in that: It includes the following steps: The geometric dimensions of the interconnection device are calculated using electromagnetic field simulation analysis software to match the impedance of the interconnection device, silicon photonic integrated chip, and transition transmission substrate; Vacuum suction of the interconnection substrate of the interconnection device to adjust the alignment of the bumps on the interconnection substrate with the pads of the silicon photonic integrated chip and the pad marks of the transition transmission substrate; Welding the bumps and pads after mark alignment to achieve electrical connection between the interconnection device, silicon photonic integrated chip and transition transmission substrate; Loading control signals to the silicon photonic integrated chip enables active coupling alignment of the silicon photonic integrated chip, and finally completes the optoelectronic integrated packaging of the silicon photonic integrated chip.

2. The method for connecting a silicon photonic integrated chip to a high-frequency transition substrate according to claim 1, characterized in that: The vacuum suction interconnection substrate of the interconnection device is used to adjust the alignment of the bumps on the interconnection substrate with the pads of the silicon photonic integrated chip and the pad marks of the transition transmission substrate, including: The interconnection substrate of the interconnection device is vacuum-sucked by the suction nozzle of the flip-chip welding equipment to adjust the alignment between the bumps on the interconnection substrate and the pads of the silicon photonic integrated chip and the pad marks of the transition transmission substrate.

3. The method for connecting a silicon photonic integrated chip to a high-frequency transition substrate according to claim 1, characterized in that: The method of welding the convex points and the pads after the mark alignment to realize the electrical connection between the interconnection device, the silicon photonic integrated chip and the transition transmission substrate includes: The bumps and pads after mark alignment are reflow soldered to achieve electrical connection between the interconnect device, silicon photonic integrated chip and transition transmission substrate.

4. The method for connecting a silicon photonic integrated chip to a high-frequency transition substrate according to claim 1, characterized in that: Before the control signal is loaded to the silicon photonic integrated chip to align the active coupling of the silicon photonic integrated chip and finally complete the optoelectronic integrated packaging of the silicon photonic integrated chip, the method includes: Place the interconnection device, the silicon photonic integrated chip and the transition transmission substrate on a coupling platform.

5. The method for connecting a silicon photonic integrated chip to a high-frequency transition substrate according to claim 1, characterized in that: Before the interconnection substrate of the interconnection device is vacuum-sucked to adjust the alignment of the bumps on the interconnection substrate with the pads of the silicon photonic integrated chip and the pad marks of the transition transmission substrate, the method includes: Place the silicon photonic integrated chip and the transition transmission substrate upright on the carrier so that the radio frequency electrodes of the silicon photonic integrated chip and the transition transmission substrate are aligned.

6. The method for connecting a silicon photonic integrated chip to a high-frequency transition substrate as claimed in claim 5, characterized in that: After the silicon photonic integrated chip and the transition transmission substrate are placed upright on the carrier to align the radio frequency electrodes of the silicon photonic integrated chip and the transition transmission substrate, the method further includes: The silicon photonic integrated chip and the transition transmission substrate are glued and cured on the carrier.

7. The method for connecting a silicon photonic integrated chip to a high-frequency transition substrate according to claim 1, characterized in that: Its geometric dimensions include the thickness of the interconnect substrate, the S-pole width of the electrical transmission line, the G-pole width and the spacing between the G-pole and the S-pole, as well as the height and diameter of the bump.

8. The method for connecting a silicon photonic integrated chip to a high-frequency transition substrate according to claim 1, characterized in that: The pad electrode of the silicon photonic integrated chip is a GSG type electrode, and the pad electrode of the transition transmission substrate is a GSG type electrode.

9. The method for connecting a silicon photonic integrated chip to a high-frequency transition substrate according to claim 1, characterized in that: The pad electrode of the silicon photonic integrated chip is a GS type electrode, and the pad electrode of the transition transmission substrate is a GSG type electrode.

10. An interconnection device, characterized in that: It includes: An interconnection substrate, wherein an electric transmission line is arranged on one side of the interconnection substrate, and bumps are fixed at both ends of the electric transmission line. The bumps at both ends of the electric transmission line are used to connect between the electrodes correspondingly connected to the silicon photonic integrated chip and the transition transmission substrate.

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