A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and is applied to the technical field of semiconductors. In the application, the semiconductor device with height differences in the vertical direction between a plurality of lower electrodes is formed by removing part of the height of at least one of the plurality of lower electrodes on the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor memory device and its fabrication method. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, because it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current in the capacitor structure, it has gradually replaced DRAM cells with only planar gate structures under the current mainstream development trend. Generally, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage component to receive voltage signals from the bit line and word line. However, due to limitations in process technology, existing DRAM cells with recessed gate structures still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related memory components. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor structure to improve the performance and reliability of semiconductor devices.

[0004] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for manufacturing a semiconductor device, which may include at least:

[0005] Provide a base, including a first zone and a second zone;

[0006] A stacked structure layer is formed on the first region and the second region, and the stacked structure layer includes a support stack layer and a first mask layer stacked from bottom to top;

[0007] A through-hole is formed within the first region, and the through-hole penetrates the stacked structure layer;

[0008] The lower electrode is formed on the inner surface of the through hole and extends laterally to cover the first mask layer in the second region;

[0009] A second mask layer is formed on the lower electrode in the first region and the second region;

[0010] Remove the second mask layer, a portion of the lower electrode, and a portion of the first mask layer on the second region so that the top surfaces of the lower electrode on the side walls of at least one of the vias adjacent to the second region are at different horizontal heights.

[0011] Optionally, the step of removing the lower electrode on the second region may include:

[0012] A first photoresist layer with a first opening is formed on the second mask layer, and the first opening exposes a portion of the top surface of the second mask layer on the first region and the top surface of the second mask layer on the second region;

[0013] Using the first photoresist layer as a mask, the second mask layer corresponding to the first opening, the portion of the lower electrode, and the portion of the first mask layer are removed to expose the support stack layer on the second region and the lower electrode on the adjacent via sidewall.

[0014] Optionally, after removing the lower electrode on the second region, the process may further include:

[0015] Remove the first photoresist layer and the second mask layer beneath it from the first region to expose the lower electrode on the first region.

[0016] Optionally, the via adjacent to the support stack layer on the second region has opposing first and second sidewalls, the lower electrode located on the first sidewall is in direct contact with the stack structure layer on the first region, and the lower electrode located on the second sidewall is in direct contact with the support stack layer on the second region.

[0017] Optionally, the top surface of the lower electrode located on the first sidewall is higher than the top surface of the lower electrode located on the second sidewall.

[0018] Optionally, the support stack may include a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer stacked sequentially from bottom to top.

[0019] Optionally, after removing the second mask layer on the first region, the process may further include:

[0020] Remove the lower electrode on the support stack layer between adjacent vias and the first mask layer below it.

[0021] Optionally, in the step of removing the lower electrode on the support stack layer between adjacent vias and the first mask layer below it, a portion of the height of the lower electrode on the second sidewall of the via adjacent to the support stack layer on the second region is also removed simultaneously.

[0022] Optionally, after removing the second mask layer on the first region, the process may further include:

[0023] A third mask layer is formed on the first region and the second region;

[0024] A second photoresist layer with a second opening is formed on the third mask layer located in the first region, the second opening exposing a portion of the top surface of the third mask layer in the first region.

[0025] Optionally, after removing the second mask layer on the first region, the process may further include:

[0026] Using the second photoresist layer as a mask, remove the first support layer and the second support layer from the third mask layer and the support stack layer corresponding to the second opening.

[0027] Optionally, after removing the second mask layer on the first region, the process may further include:

[0028] Remove the second sacrificial layer and the first sacrificial layer from the support stack layers in the first region and the second region.

[0029] Optionally, after removing the second mask layer, the lower electrode, and the first mask layer on the second region, the following may also be included:

[0030] A metal oxide layer is formed on the lower electrode, and an upper electrode is formed on the metal oxide.

[0031] Secondly, based on the same inventive concept, the present invention also provides a semiconductor device, which may include at least:

[0032] The substrate includes the first and second regions;

[0033] The support structure includes a first support structure located in the first region and a second support structure located in the second region, wherein the length of the second support structure is greater than that of the first support structure.

[0034] A plurality of lower electrodes are located on the first region of the substrate, and at least a portion of the top surface of the lower electrode that is in contact with the second support structure on the second region is lower than the top surface of the remaining lower electrodes.

[0035] Optionally, the semiconductor device may further include:

[0036] A metal oxide layer is located on the plurality of lower electrodes;

[0037] The upper electrode is located on the metal oxide layer.

[0038] Optionally, the lower electrode that contacts the second support structure on the second region has opposing first and second sidewalls, the second sidewalls contacting the second support structure, and the top surface of the lower electrode located on the first sidewall is higher than the top surface of the lower electrode located on the second sidewall.

[0039] Optionally, the lower electrode that contacts the second support structure on the second region may be located on the same side as all the other lower electrodes.

[0040] Optionally, the lower electrode may be cylindrical or cylindrical.

[0041] Thirdly, based on the same inventive concept, the present invention also provides a semiconductor device, which may include at least:

[0042] Base;

[0043] Multiple lower electrodes are located on the substrate, wherein at least a portion of the top surface of one of the lower electrodes is lower than all the other lower electrodes and is located on the same side of all the lower electrodes.

[0044] Optionally, the semiconductor device may further include:

[0045] A metal oxide layer is located on the plurality of lower electrodes;

[0046] The upper electrode is located on the metal oxide layer.

[0047] Optionally, the lower electrode has opposing first and second sidewalls, the second sidewall being located on a side away from the remaining lower electrodes, and the top surface of the lower electrode located on the first sidewall being higher than the top surface of the lower electrode located on the second sidewall.

[0048] In this invention, by simultaneously removing a portion of the height of the lower electrode on one sidewall of at least one via adjacent to the second region when removing the second mask layer and the first mask layer stacked in the second region, at least one of the lower electrodes in the formed semiconductor device has a top surface lower than the top surface of the remaining lower electrodes, that is, there is a height difference between the lower electrodes in the formed semiconductor device in the vertical direction, which improves the performance and reliability of the semiconductor device. Attached Figure Description

[0049] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0050] Figure 1 This is a flowchart of a method for fabricating a semiconductor memory according to an embodiment of the present invention;

[0051] Figures 2 to 11 This is a schematic diagram of the fabrication process of the semiconductor device provided in one embodiment of the present invention.

[0052] Figure 12 The utilization provided in one embodiment of the present invention Figure 1The diagram shows the evolution of the structure of a semiconductor device fabricated using the method shown.

[0053] The attached figures are labeled as follows:

[0054] 100 - Substrate, 101 - First region of the substrate, 102 - Second region of the substrate, 251 - Stacked structure layer, 110 / 110' / 110" - Support stacked layer, 110 - Support stacked layer, 111 - First sacrificial layer, 112 - First support layer, 113 - Second sacrificial layer, 114 - Second support layer, 120 - First mask layer, OP - Via, 130 - Lower electrode, 140 - Second mask layer, 150 - First photoresist layer, OP1 - Via adjacent to the support stacked layer on the second region, 160 - Third mask layer, 131 / 131' - Lower electrode on the first sidewall of via OP1, 132 / 132' - Lower electrode on the second sidewall of via OP1, H1 / H2 - Height difference of the lower electrode on the first and second sidewalls, 170 - Second photoresist layer, 180 - Metal oxide layer, 190 - Upper electrode, CAP - Capacitor.

[0055] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0056] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0057] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" means not only "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.

[0058] For ease of understanding, the horizontal and vertical directions are defined below, where the horizontal direction is the direction parallel to the surface of the substrate 100, and the vertical direction is the direction perpendicular to the surface of the substrate 100.

[0059] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the method for fabricating a semiconductor device provided in an embodiment of the present invention. Figure 1 As shown, the method for fabricating a semiconductor device provided in this embodiment includes at least the following steps:

[0060] Step S101: Provide a substrate, including a first region and a second region;

[0061] Step S102: A stacked structure layer is formed on the first region and the second region. The stacked structure layer includes a support stack layer and a first mask layer stacked from bottom to top.

[0062] Step S103: A through-hole is formed within the first region, and the through-hole penetrates the stacked structure layer;

[0063] Step S104: Form a lower electrode located on the inner surface of the through hole and extend laterally to cover the first mask layer in the second region;

[0064] Step S1015: A second mask layer is formed on the lower electrode located in the first region and the second region;

[0065] Step S106: Remove the second mask layer, a portion of the lower electrode, and a portion of the first mask layer on the second region, so that the top surfaces of the lower electrodes on the side walls of at least one of the through holes adjacent to the second region are at different horizontal heights.

[0066] To enable those skilled in the art to easily understand the fabrication method of the semiconductor device in the embodiments of this invention, the fabrication method of the semiconductor device proposed in this invention will be further described below with reference to various structural schematic diagrams during the fabrication process. Among them, Figures 2 to 12 This is a schematic diagram of the structure of the semiconductor device fabrication method provided in the embodiments of the present invention during the preparation process.

[0067] Perform the above step S101: Please refer to Figure 2A substrate 100 is provided, the substrate 100 including a first region 101, for example, a cell region of a semiconductor memory, and a second region 102, for example, a peripheral region of a semiconductor memory. In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate or a substrate made of other suitable materials, but not limited thereto. Bit line structures, sidewall structures, contact structures, and connection pad structures (not shown) may be formed within the substrate 100, but are not limited thereto.

[0068] Perform step S102 above: Please continue to refer to Figure 2 A stacked structure layer 251 is formed on the surface of the substrate 100 using at least one deposition process such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The stacked structure layer 251 comprises, from bottom to top, a support stacked layer 110 and a first mask layer 120 stacked sequentially. In one embodiment, the support stacked layer 110 may further comprise, from bottom to top, a first sacrificial layer 111, a first support layer 112, a second sacrificial layer 113, and a second support layer 114 stacked sequentially, to provide stronger support for the lower electrode by providing multiple support layers, but this is not a limitation. The first sacrificial layer 111 and the second sacrificial layer 113 may each comprise a single or multiple layers of oxide material, such as silicon oxide, borophospho-silicate glass (BPSG), or other sacrificial materials having a desired etch selectivity with the material of the support layer, but this is not a limitation. The first support layer 112 and the second support layer 114 may be silicon carbonitride (SiCN); the material of the first mask layer 120 may include silicon oxide, amorphous silicon, polycrystalline silicon or a combination of the above materials, but is not limited thereto.

[0069] Perform the above step S103: Please continue to refer to... Figure 2 Multiple horizontally spaced vias OP are formed within the stacked structure layer 251 in the first region 101 of the substrate 100 using at least one etching process, such as dry etching or wet etching. These vias OP penetrate the first mask layer 120 and the support stacked layer 110, with their bottoms exposed on the substrate 100, but this is not a limitation. After etching to form the vias OP, the top surface of the portion of the first mask layer 120 located in the first region 101 may be lower than the top surface of the portion located in the second region 102.

[0070] Perform the above step S104: Please refer to Figure 3The conductive material layer of the lower electrode 130 is formed using at least one of the above deposition processes. Specifically, the conductive material layer of the lower electrode 130 is located on the inner surface of the via OP, the top surface of the first mask layer 120 exposed in the first region 101 between adjacent vias OP, and the top surface of the first mask layer 120 in the second region 102. At this time, the conductive material layer of the lower electrode 130 does not fill the via OP located in the first region 101. In one embodiment, the material of the conductive material layer of the lower electrode 130 may include doped silicon, tungsten, copper, titanium nitride, or others, but is not limited thereto.

[0071] Perform the above step S105: Please refer to Figure 4 A second mask layer 140 is formed on the first region 101 and the second region 102 of the substrate 100 using at least one of the deposition processes described above. The second mask layer 140 fills the gaps between adjacent vias OP in the first region 101 and extends laterally in the horizontal direction, covering the top surface of the lower electrode 130 between adjacent vias OP and the top surface of the lower electrode 130 located on the second region 102. That is, the second mask layer 140 buries the film structure on both the first region 101 and the second region 102, and due to the height difference of the stacked structure layers 251 in the first region 101 and the second region 102, it forms a stepped shape at the junction of the first region 101 and the second region 102. In one embodiment, the material of the second mask layer 140 may be the same as that of the first mask layer 120, for example, both being silicon oxide, or it may be different, for example, the material of the first mask layer 120 is silicon oxide, while the material of the second mask layer 140 is polycrystalline silicon, but this is not a limitation.

[0072] Perform the above step S106: Please refer to Figure 5 and Figure 6 First, a first photoresist layer 150 can be formed on the second mask layer 140 in the first region 101. The first photoresist layer 150 has an opening (hereinafter referred to as the first opening for ease of distinction), which exposes a portion of the top surface of the second mask layer 140 on the first region 101 and the entire top surface of the second mask layer 140 on the second region 102. Next, using the first photoresist layer 150 with the first opening as a mask, a portion of the second mask layer 140 and a portion of the lower electrode 130 on the first region 101 corresponding to the first opening, as well as all the second mask layer 140 and all the first mask layer 120 on the second region 102, can be removed vertically to expose the support stack layer 110 on the second region 102 and the lower electrode 130 on the sidewall of a via OP on the first region 101, forming a structure as shown below. Figure 5The structure is shown. Next, the first photoresist layer 150 and the remaining second mask layer 140' beneath it are further removed from the first region 101 to expose the lower electrode 130 on the first region 101, forming a structure as shown. Figure 6 The structure shown.

[0073] Thus, the through-hole OP adjacent to the second region 102 (such as...) Figure 6 As shown, the top surfaces of the lower electrodes on the two side walls of the through hole OP1 (hereinafter referred to as OP1) are at different horizontal heights; specifically, the through hole OP1 adjacent to the support stack layer 251 on the second region 102 has opposing first and second side walls. For example, for ease of distinction, the side wall of the through hole OP1 near the first region 101 can be called the first side wall (i.e., the first side wall is in direct contact with the stack structure layer 251 on the first region 101), and the side wall of the through hole OP1 near the second region 102 can be called the second side wall (i.e., the second side wall is in direct contact with the support stack layer 110 on the second region 102). The lower electrode 130 located on the first side wall of the through hole OP1 is identified by reference numeral 131, and the lower electrode 130 located on the second side wall of the through hole OP1 is identified by reference numeral 132. Figure 6 As shown. Obviously, in the process of removing the second mask layer 140 and the first mask layer 120 on the second region 102 in step S106 of the embodiment of the present invention, a portion of the height of the lower electrode 130 located on the second sidewall of the via OP1 is also removed simultaneously. This results in the top surface of the lower electrode 132 remaining on the second sidewall of the via OP1 after etching being lower than the top surface of the lower electrode 131 on the first sidewall of the via OP1 opposite to the second sidewall. That is, there is a height difference H1 between the two in the vertical direction, which also results in a height difference among the top surfaces of a portion of the multiple lower electrodes included in the finally formed semiconductor device.

[0074] It should be understood that in the embodiments of the present invention, only one via OP located on the first region 101 in the semiconductor device is set as a via OP1 with different top surfaces of the lower electrodes on the two sidewalls in the drawings. In other embodiments of the present invention, multiple via OPs on the first region 101 can also be set as via OP1 with different top surfaces (i.e. at different heights) of the lower electrodes on the sidewalls.

[0075] Continuing with step S106: Please refer to... Figure 7After removing a portion of the lower electrode 130 on the second region 102 to form a structure with a height difference between the lower electrodes on the two side walls within the via OP1, the lower electrode 130 on the support stack 110 between adjacent vias OP on the first region 101 and the first mask layer 120 below it can be further removed vertically downwards to make the top surface of the lower electrode 130 on the two side walls of the via OP on the first region 101 lower than the top surface of the support stack 110 between adjacent vias OP. In one embodiment, in the step of removing the lower electrode 130 on the support stack 110 between adjacent vias OP on the first region 101 and the first mask layer 120 below it, a portion of the height of the lower electrode 131 on the first side wall and the lower electrode 132 on the second side wall of the via OP1 adjacent to the support stack 110 on the second region 102 can also be simultaneously removed to reduce the height difference between the lower electrodes on the two side walls of the via OP1 (in the vertical direction), for example by... Figure 6 The H1 shown is reduced to Figure 7 H2 is shown as H1>H2>0, but is not limited thereto; it should be understood that, for ease of distinction, in this embodiment of the invention, the lower electrode remaining on the first sidewall of the through hole OP1 after performing this step is identified by reference numeral 131', and the lower electrode remaining on the second sidewall of the through hole OP1 is identified by reference numeral 132'.

[0076] Continuing with step S106: Please refer to... Figure 8 A third mask layer 160, which buries the corresponding film structures, and a second photoresist layer 170 located on the top surface of the third mask layer 160 on the first region 101 and the second region 102 of the substrate 100, can be further formed using a deposition process. The second photoresist layer 170 then has at least one second opening, such as... Figure 8 The two second openings shown are for exposing a portion of the top surface of the third mask layer 160 in the first region 101. In one embodiment, a second opening within the second photoresist layer 170 is located between two adjacent vias OP on the first region 101 in preparation for subsequent removal of a portion of the film layer in the support stack layer 110.

[0077] Continuing with step S106: Please refer to... Figure 9 and combined Figure 8Using the second photoresist layer 170 as a mask, an etching process such as wet etching is employed to first remove the second support layer 114 and a portion of the second sacrificial layer 113 from the third mask layer 160 and the support stack layer 110, which correspond to at least one second opening within the second photoresist layer 170. In one embodiment, the second support layer 114 is partially removed in this step, while the second sacrificial layer 113 is completely removed, and the position of the removed second support layer 114 aligns with the second opening within the second photoresist layer 170, but this is not a limitation. It should be understood that, for ease of distinction, the support stack layer obtained after performing this step in this embodiment of the invention is identified by reference numeral 110'.

[0078] Continuing with step S106: Please refer to... Figure 10 and combined Figure 8 and Figure 9 Using the second photoresist layer 170 as a mask, an etching process such as wet etching can be used to further remove part of the first support layer 112 and all of the first sacrificial layer 111 in the support stack layer 110' on the first region 101 and the second region 102, and the support stack layer obtained after this step is marked with reference numeral 110". Subsequently, the second photoresist layer 170 and the remaining third mask layer 160 are removed. It should be understood that since the second photoresist layer 170 in this embodiment of the invention has a second opening, the two etching removal steps performed on the support stack layer 110 will remove the second support layer 114 and the first support layer 112 located in the support stack layer 110 within the second opening, but this is not a limitation.

[0079] Continuing with step S106: Please refer to... Figure 11 or Figure 12Furthermore, at least one of the above deposition processes can be used to form a metal oxide layer 180 on the lower electrode 130 in the via OP of the first region 101, and an upper electrode 190 filling the remaining area of ​​the via OP can be formed on the metal oxide layer 180, thereby forming a capacitor CP composed of the lower electrode 130, the metal oxide layer 180 and the upper electrode 190. In one embodiment, the metal oxide layer 180 may include a high dielectric constant material layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)OO, Sr(Zr,Ti)O, combinations of the above materials, or other suitable dielectric materials, while the material of the upper electrode 190 may include titanium nitride, tantalum nitride, SiGe, combinations of the above materials, or other suitable conductive materials, but is not limited thereto. Furthermore, the upper electrode 190 will also fill the areas corresponding to the first sacrificial layer 111, the second sacrificial layer 113, the first support layer 112 and the second support layer 114 that have been removed in the support stack layer 110”, and extend laterally to the top surface of the support stack layer 110” exposed in the first region 101 and the second region 102.

[0080] It should be noted that, as above, based on Figures 2 to 11 In the semiconductor device fabrication method shown, the lower electrode 130 or lower electrode 131' / 131” and lower electrode 132' / 132” located on the inner surface of the through hole OP or OP1 in the first region 101 are cylindrical throughout the entire process. However, in other embodiments, the lower electrode 130 or lower electrode 131' / 131” and lower electrode 132' / 132” located on the inner surface of the through hole OP or OP1 in the first region 101 may also be columnar, such as... Figure 12 As shown.

[0081] Based on this, for different shapes of the lower electrode 130 included in the capacitor CAP, the embodiments of the present invention provide, respectively, the following... Figure 11 The structure of the semiconductor device shown, and as Figure 12 The structure of the semiconductor device shown, and Figure 11 and Figure 12 The semiconductor devices shown all differ in the shape of the lower electrode 130, but their other corresponding fabrication processes are the same, though not limited thereto.

[0082] In summary, in this invention, by simultaneously removing a portion of the height of the lower electrode on one sidewall adjacent to at least one via in the second region when removing the second mask layer and the first mask layer stacked in the second region, at least one of the lower electrodes in the formed semiconductor device has a top surface lower than the top surface of the remaining lower electrodes. That is, there is a height difference between the lower electrodes in the formed semiconductor device in the vertical direction, which improves the performance and reliability of the semiconductor device.

[0083] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0084] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0085] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide a base, including a first zone and a second zone; A stacked structure layer is formed on the first region and the second region. The stacked structure layer includes a support stack layer and a first mask layer stacked from bottom to top. The support stack layer includes a first sacrificial layer, a first support layer, a second sacrificial layer and a second support layer stacked from bottom to top. A through-hole is formed within the first region, and the through-hole penetrates the stacked structure layer; The lower electrode is formed on the inner surface of the through hole and extends laterally to cover the first mask layer in the second region; A second mask layer is formed on the lower electrode in the first region and the second region; Remove the second mask layer, part of the lower electrode, and part of the first mask layer on the second region, so that the top surfaces of the lower electrodes on the two side walls of at least one of the through holes adjacent to the second region are at different horizontal heights and are in physical contact with the second support layer, and the top surfaces of the lower electrodes on the two side walls of the at least one of the through holes are all higher than the bottom surface of the second support layer and all lower than the top surface of the second support layer.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of removing the lower electrode on the second region includes: A first photoresist layer with a first opening is formed on the second mask layer, and the first opening exposes a portion of the top surface of the second mask layer on the first region and the top surface of the second mask layer on the second region; Using the first photoresist layer as a mask, the second mask layer, part of the lower electrode, and part of the first mask layer corresponding to the first opening are removed to expose the support stack layer on the second region and the lower electrode on the adjacent via sidewall.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, After removing the lower electrode on the second region, the process further includes: Remove the first photoresist layer and the second mask layer beneath it from the first region to expose the lower electrode on the first region.

4. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The via adjacent to the support stack layer on the second region has opposing first and second sidewalls. The lower electrode located on the first sidewall is in direct contact with the stack structure layer on the first region, and the lower electrode located on the second sidewall is in direct contact with the support stack layer on the second region.

5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The top surface of the lower electrode located on the first sidewall is higher than the top surface of the lower electrode located on the second sidewall.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, After removing the second mask layer on the first region, the process further includes: Remove the lower electrode on the support stack layer between adjacent vias and the first mask layer below it.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, In the step of removing the lower electrode on the support stack layer between adjacent vias and the first mask layer below it, a portion of the height of the lower electrode on the second sidewall of the via adjacent to the support stack layer on the second region is also removed simultaneously.

8. The method for fabricating a semiconductor device as described in claim 6, characterized in that, After removing the second mask layer on the first region, the process further includes: A third mask layer is formed on the first region and the second region; A second photoresist layer with a second opening is formed on the third mask layer in the first region, and the second opening exposes a portion of the top surface of the third mask layer in the first region.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After removing the second mask layer on the first region, the process further includes: Using the second photoresist layer as a mask, the first support layer and the second support layer in the third mask layer and the support stack layer corresponding to the second opening are removed.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, After removing the second mask layer on the first region, the process further includes: Remove the second sacrificial layer and the first sacrificial layer from the support stack layers in the first region and the second region.

11. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After removing the second mask layer, the lower electrode, and the first mask layer on the second region, the process further includes: A metal oxide layer is formed on the lower electrode, and an upper electrode is formed on the metal oxide.

12. A semiconductor device, characterized in that, include: The substrate includes the first and second regions; The support structure includes a first support structure located in the first region and a second support structure located in the second region, wherein the length of the second support structure is greater than that of the first support structure. A plurality of lower electrodes are located on the first region of the substrate, and at least a portion of the top surface of the lower electrode that is in contact with the second support structure on the second region is lower than the top surface of the remaining lower electrodes, and is higher than the bottom surface of the second support structure and lower than the top surface of the second support structure.

13. The semiconductor device as claimed in claim 12, characterized in that, Also includes: A metal oxide layer is located on the plurality of lower electrodes; The upper electrode is located on the metal oxide layer.

14. The semiconductor device as claimed in claim 12, characterized in that, The lower electrode that is in contact with the second support structure on the second region has opposing first and second sidewalls, the second sidewalls contacting the second support structure, and the top surface of the lower electrode located on the first sidewall is higher than the top surface of the lower electrode located on the second sidewall.

15. The semiconductor device as claimed in claim 12, characterized in that, The lower electrode that contacts the second support structure on the second region is located on the same side as all the other lower electrodes.

16. The semiconductor device as claimed in claim 12, characterized in that, The lower electrode may be cylindrical or columnar.

17. A semiconductor device, characterized in that, include: Base; A supporting structure is located on the substrate; Multiple lower electrodes are located on the substrate, wherein at least a portion of the top surface of one lower electrode is lower than all the other lower electrodes and is located on the same side of all the other lower electrodes, and the one lower electrode is in physical contact with the support structure, and the top surface of the one lower electrode is also higher than the bottom surface of the support structure and lower than the top surface of the support structure.

18. The semiconductor device as claimed in claim 17, characterized in that, Also includes: A metal oxide layer is located on the plurality of lower electrodes; The upper electrode is located on the metal oxide layer.

19. The semiconductor device as claimed in claim 17, characterized in that, The lower electrode has opposing first and second sidewalls, the second sidewall being located on a side away from all the other lower electrodes, and the top surface of the lower electrode located on the first sidewall being higher than the top surface of the lower electrode located on the second sidewall.

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