Nonvolatile memory device

Abstract

A non-volatile memory device is provided. The nonvolatile memory device includes first and second semiconductor layers and a pass transistor. The first semiconductor layer includes word lines extending in a first direction and bit lines extending in a second direction, and further includes a first substrate and a memory cell array. The memory cell array is on the first substrate and is connected to the word line and the bit line. The second semiconductor layer is arranged in a third direction with respect to the first semiconductor layer, and includes a second substrate and a peripheral circuit. The peripheral circuit is on the second substrate and controls the memory cell array. The pass transistor is connected to the word line and controls an electrical connection between the memory cell array and the peripheral circuit. A first portion of the pass transistor is in the first semiconductor layer, and a second portion of the pass transistor is in the second semiconductor layer.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0085764 filed on July 3, 2023 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Aspects of the present disclosure relate generally to semiconductor integrated circuits, and more particularly, to nonvolatile memory devices and memory packages including the same. Background Art

[0003] A vertical memory device (also referred to as a three-dimensional (3D) memory device) is a memory device that includes a plurality of memory cells repeatedly stacked on the surface of a substrate. These memory devices can have a relatively high storage capacity within a relatively small structure. For example, in a vertical memory device, a channel may protrude or extend vertically from the surface of a substrate, and a gate line and an insulating layer surrounding the vertical channel may be repeatedly stacked.

[0004] However, since the memory device still needs to include a peripheral circuit for driving the memory cell array and a wiring structure for electrically connecting the memory cell array to the peripheral circuit, the reduction in size of the vertical memory device is limited. Therefore, there is a demand for a memory device with high integration and excellent electrical characteristics. Summary of the invention

[0005] Some aspects of the present disclosure provide a nonvolatile memory device having a reduced size and / or reduced manufacturing cost.

[0006] Some aspects of the present disclosure provide a memory package including the nonvolatile memory device.

[0007] According to some example embodiments, a nonvolatile memory device may include a first semiconductor layer, a second semiconductor layer, and a plurality of pass transistors. The first semiconductor layer includes a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction, and further includes a first substrate and a memory cell array. The memory cell array is located on the first substrate and connected to the plurality of word lines and the plurality of bit lines. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a second substrate and a peripheral circuit. The peripheral circuit is located on the second substrate and controls the memory cell array. The plurality of pass transistors are connected to the plurality of word lines and control electrical connections between the memory cell array and the peripheral circuit. A first portion of the plurality of pass transistors is located in the first semiconductor layer, and a second portion of the plurality of pass transistors is located in the second semiconductor layer.

[0008] According to some example embodiments, a nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a plurality of pass transistors. The first semiconductor layer includes a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction, and further includes a first substrate and a memory cell array. The memory cell array is located on the first substrate and connected to the plurality of word lines and the plurality of bit lines. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a second substrate and a first peripheral circuit. The first peripheral circuit is located on the second substrate and controls the memory cell array. The third semiconductor layer is arranged in a third direction relative to the first semiconductor layer, and includes a third substrate and a second peripheral circuit. The second peripheral circuit is located on the third substrate and controls the memory cell array. A plurality of pass transistors are connected to the plurality of word lines and control electrical connections between the memory cell array and the first peripheral circuit and the second peripheral circuit. A first portion of the plurality of pass transistors is located in the second semiconductor layer, and a second portion of the plurality of pass transistors is located in the third semiconductor layer.

[0009] According to an example embodiment, a memory package includes a base substrate and a plurality of memory chips stacked on the base substrate. Each of the plurality of memory chips includes a first semiconductor layer, a second semiconductor layer, and a plurality of pass transistors. The first semiconductor layer includes a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction, and further includes a first substrate and a memory cell array. The memory cell array is located on the first substrate and connected to the plurality of word lines and the plurality of bit lines. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a second substrate and a peripheral circuit. The peripheral circuit is located on the second substrate and controls the memory cell array. A plurality of pass transistors are connected to the plurality of word lines and control the electrical connection between the memory cell array and the peripheral circuit. A first portion of the plurality of pass transistors is located in the first semiconductor layer, and a second portion of the plurality of pass transistors is located in the second semiconductor layer.

[0010] According to some example embodiments, a nonvolatile memory device includes a first semiconductor layer, a second semiconductor, a plurality of pass transistors, and a plurality of drivers. The first semiconductor layer includes a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction, and further includes a first substrate and a memory cell array. The memory cell array is located on the first substrate and connected to the plurality of word lines and the plurality of bit lines. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a second substrate and a peripheral circuit. The peripheral circuit is located on the second substrate and controls the memory cell array. A plurality of pass transistors are connected to the plurality of word lines and control electrical connections between the memory cell array and the peripheral circuit. A plurality of drivers control switching operations of the plurality of pass transistors. The memory cell array includes a core region and an extension region. The core region includes a plurality of memory cells. The extension region is adjacent to a first side of the core region and includes a plurality of word line contacts for electrical connections between the plurality of word lines and the plurality of pass transistors. The plurality of word lines include a first word line and a second word line. The plurality of pass transistors include a first pass transistor connected to the first word line and a second pass transistor connected to the second word line. The plurality of drivers include a first driver that controls a switching operation of a first pass transistor and a second driver that controls a switching operation of a second pass transistor. The plurality of word line contacts include a first word line contact that electrically connects a first word line to a first pass transistor and a second word line contact that electrically connects a second word line to a second pass transistor. The first pass transistor and the first driver are located in a first substrate of the first semiconductor layer, and the second pass transistor and the second driver are located in a second substrate of the second semiconductor layer. The first word line contact and the second word line contact are located in an extension region of the first semiconductor layer.

[0011] In the nonvolatile memory device and the memory package according to example embodiments, a BVNAND structure in which a peripheral circuit and a memory cell array are stacked may be employed, and thus the nonvolatile memory device may have a relatively small size.

[0012] In addition, the through transistors for controlling the electrical connection between the memory cell array and the peripheral circuit can be separated and / or distributed in different semiconductor layers. Therefore, the area in which the through transistors are placed in one semiconductor layer can be reduced, and the wiring complexity for connecting the through transistors to the word lines can be reduced. Therefore, the circuit area can be reduced, the manufacturing cost can be reduced, and the non-volatile memory device can be manufactured efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1is a perspective view of a nonvolatile memory device according to some example embodiments.

[0015] Figure 2 is a cross-sectional view of a nonvolatile memory device according to some example embodiments.

[0016] Figure 3 is a block diagram illustrating a nonvolatile memory device according to some example embodiments.

[0017] Figure 4 is included in Figure 3 A perspective view of an example of a memory block in a memory cell array of a nonvolatile memory device.

[0018] Figure 5 It shows reference Figure 4 A circuit diagram depicting the equivalent circuit of the memory block.

[0019] Figure 6 It is shown that the Figure 3 A block diagram of an example of an address decoder in a non-volatile memory device.

[0020] Fig. 7A , Figure 7B and Figure 7C is a cross-sectional view for describing a channel hole included in a nonvolatile memory device according to some example embodiments.

[0021] Fig. 8A , Figure 8B and Figure 8C is a diagram for describing a core area and an extension area included in a nonvolatile memory device according to some example embodiments.

[0022] Fig. 9 yes Figure 2 A cross-sectional view of an example of a nonvolatile memory device.

[0023] Fig.10 is included in Fig. 9 A cross-sectional view of an example of a word line contact in a nonvolatile memory device.

[0024] Fig.11 and Fig.12 yes Figure 2 A cross-sectional view of an example of a nonvolatile memory device.

[0025] Fig.13A and Fig. 13B is a perspective view of a nonvolatile memory device according to some example embodiments.

[0026] Fig.14A and Fig. 14B yes Figure 2A cross-sectional view of an example of a nonvolatile memory device.

[0027] Fig.15A , Fig. 15B , Fig. 15C , Fig.15D and Fig.15E is a diagram illustrating a nonvolatile memory device according to some example embodiments.

[0028] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D is a diagram illustrating a nonvolatile memory device according to some example embodiments.

[0029] Fig.17A and Fig. 17B is a cross-sectional view of a memory package according to some example embodiments.

[0030] Fig.18 is a block diagram illustrating an electronic system including a nonvolatile memory device according to some example embodiments.

[0031] Fig.19 is a cross-sectional view of a memory device according to some example embodiments.

[0032] Fig. 20 is a diagram illustrating a manufacturing process of a memory device according to some example embodiments. DETAILED DESCRIPTION

[0033] Various examples of the embodiments will be described more fully with reference to the accompanying drawings, in which some examples of the embodiments are shown. However, the present disclosure can be implemented in many different forms and should not be interpreted as being limited in any way to the embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0034] Figure 1 is a perspective view of a nonvolatile memory device according to some example embodiments.

[0035] exist Figure 1In the figure, two directions that are each parallel to or substantially parallel to the first surface (e.g., top surface) of the substrate and intersect each other may be referred to as the first direction D1 (e.g., X-axis direction) and the second direction D2 (e.g., Y-axis direction). In addition, the direction perpendicular to or substantially perpendicular to the first surface of the substrate may be referred to as the third direction D3 (e.g., Z-axis direction). For example, the first direction D1 and the second direction D2 may be perpendicular or substantially perpendicular to each other. In addition, the third direction D3 may be perpendicular or substantially perpendicular to both the first direction D1 and the second direction D2. In addition, the direction indicated by the arrow in the figure and the opposite direction thereof are considered to be the same direction. The definitions of the first direction D1, the second direction D2, and the third direction D3 are the same in the subsequent figures.

[0036] Reference Figure 1 , the nonvolatile memory device 10 includes a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 and the second semiconductor layer L2 may be stacked in a third direction D3. For example, the first semiconductor layer L1 may be located below the second semiconductor layer L2 in the third direction D3 (e.g., directly below the second semiconductor layer L2 or indirectly below the second semiconductor layer L2), and the second semiconductor layer L2 may be stacked on the first semiconductor layer L1 in the third direction D3. However, example embodiments are not limited thereto. For example, the nonvolatile memory device 10 may be flipped during a manufacturing process so that the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in the third direction D3. In some example embodiments, as will be referred to Fig.15A and Fig.16A As described, three or more semiconductor layers may be stacked in the third direction D3.

[0037] The first semiconductor layer L1 may include a plurality of word lines WL, a plurality of bit lines BL, and a memory cell array MCA. Therefore, the first semiconductor layer L1 may be referred to as a memory cell region (MCR).

[0038] For example, if you refer to Figure 2 As described, the first semiconductor layer L1 may include a first substrate, and a plurality of word lines WL, a plurality of bit lines BL, and a memory cell array MCA may be arranged and / or formed on the first substrate. For example, each of the plurality of word lines WL may extend in a first direction D1, the plurality of word lines WL may be arranged along a second direction D2 or spaced apart from each other, and the plurality of word lines WL may be stacked in a third direction D3. For example, each of the plurality of bit lines BL may extend in a second direction D2, and the plurality of bit lines BL may be arranged along a first direction D1 or spaced apart from each other. For example, the memory cell array MCA may be connected to the plurality of word lines WL and the plurality of bit lines BL.

[0039] The second semiconductor layer L2 may include a peripheral circuit PC controlling the memory cell array MCA. Therefore, the second semiconductor layer L2 may be referred to as a peripheral circuit region (PCR).

[0040] For example, if you refer to Figure 2 As described, the second semiconductor layer L2 may include a second substrate, and the peripheral circuit PC may be arranged and / or formed on the second substrate. Figure 3 As described, the peripheral circuit PC may include a control circuit, a page buffer circuit, and the like.

[0041] Although not shown in detail, the first semiconductor layer L1 may include a pattern for electrically connecting the memory cell array MCA (eg, a plurality of word lines WL and a plurality of bit lines BL) with a circuit formed in the second semiconductor layer L2 .

[0042] The nonvolatile memory device 10 may include a plurality of pass transistors PT. The plurality of pass transistors PT may be connected to a plurality of word lines WL, and may control electrical connections between the memory cell array MCA and the peripheral circuit PC. For example, some (e.g., a first portion) of the plurality of pass transistors PT may be arranged and / or formed in the first semiconductor layer L1, and other (e.g., a second portion) of the plurality of pass transistors PT may be arranged and / or formed in the second semiconductor layer L2.

[0043] The nonvolatile memory device 10 according to some example embodiments may have or adopt a structure in which the peripheral circuit PC and the memory cell array MCA are stacked, for example, a bonded vertical NAND (BVNAND) structure in which the peripheral circuit PC and the memory cell array MCA are set or arranged in a third direction D3. Therefore, the nonvolatile memory device 10 may have a relatively small size. For example, the first semiconductor layer L1 may include a first metal pad (pad, or referred to as a "pad" or "pad"), the second semiconductor layer L2 may include a second metal pad, and the first semiconductor layer L1 and the second semiconductor layer L2 may be manufactured on separate wafers. The first metal pad and the second metal pad may be connected by a bonding method, so that the first semiconductor layer L1 and the second semiconductor layer L2 may be electrically connected in the third direction D3. Reference will be made to Fig.19 The BVNAND structure is described in more detail.

[0044] However, example embodiments are not limited thereto, and the nonvolatile memory device 10 may have or employ a cell-on-periphery (COP) structure in which a peripheral circuit PC is formed below and then a memory cell array MCA is stacked on the peripheral circuit PC in a single manufacturing process.

[0045] In addition, in the nonvolatile memory device 10 according to example embodiments, a plurality of pass transistors PT may be separated and / or distributed in the first semiconductor layer L1 and the second semiconductor layer L2. For example, instead of forming all the pass transistors PT in one of the first semiconductor layer L1 and the second semiconductor layer L2, some pass transistors PT may be formed in the first semiconductor layer L1 and other pass transistors PT may be formed in the second semiconductor layer L2. Therefore, the area in which the pass transistors PT are placed within one semiconductor layer may be reduced, and the wiring complexity for connecting the pass transistors PT with the word line WL may be reduced. Therefore, the circuit area may be reduced, the manufacturing cost may be reduced, and the nonvolatile memory device 10 may be manufactured more efficiently.

[0046] Figure 2 is a cross-sectional view of a nonvolatile memory device according to some example embodiments.

[0047] Reference Figure 2 The first semiconductor layer L1 may include a first substrate SUB1, first and second word lines WLa and WLb, a channel (or vertical channel or pillar) CH, a first pass transistor PTa, and a first insulating layer IL1. The second semiconductor layer L2 may include a second substrate SUB2, a second pass transistor PTb, and a second insulating layer IL2.

[0048] The first substrate SUB1 may be a support layer supporting components of the first semiconductor layer L1, and the second substrate SUB2 may be a support layer supporting components of the second semiconductor layer L2. For example, each of the first substrate SUB1 and the second substrate SUB2 may be a silicon substrate and may be referred to as a base substrate. The first insulating layer IL1 may cover components of the first semiconductor layer L1, and the second insulating layer IL2 may cover components of the second semiconductor layer L2.

[0049] The word lines WLa and WLb may be stacked on the first substrate SUB1 in the third direction D3. The channel CH may penetrate the word lines WLa and WLb and may extend in a direction perpendicular to the top surface of the first substrate SUB1 (e.g., the third direction D3). A memory cell array MCA including a plurality of memory cells may be formed in the first semiconductor layer L1 through the word lines WLa and WLb and the channel CH. Figure 4 , Fig. 7A , Figure 7B , Figure 7C , Figure 8B and Figure 8C A more detailed configuration of the word lines WLa and WLb and the channel CH is described.

[0050] The first pass transistor PTa may be formed in or on the first substrate SUB1 and may be connected to the first word line WLa. The second pass transistor PTb may be formed in or on the second substrate SUB2 and may be connected to the second word line WLb.

[0051] The first pass transistor PTa and the second pass transistor PTb may perform substantially the same operation, but may be formed on different substrates SUB1 and SUB2. In some example embodiments, the first pass transistor PTa and the second pass transistor PTb may be manufactured to have different physical properties (e.g., channel length, etc.) in different substrates SUB1 and SUB2. In some example embodiments, at least one of the width and length of the first pass transistor PTa in the first semiconductor layer L1 and the second pass transistor PTb in the second semiconductor layer L2 may be different from each other.

[0052] For ease of explanation, Figure 2 A nonvolatile memory device including only one first word line WLa, one first pass transistor PTa, one second word line WLb, and one second pass transistor PTb is shown. However, example embodiments are not limited thereto, and the nonvolatile memory device may include a plurality of first word lines, a plurality of first pass transistors, a plurality of second word lines, and a plurality of second pass transistors. Fig. 9 , Fig.11 , Fig.12 , Fig.14A , Fig. 14B , Fig. 15C , Fig.15D , Fig.15E , Fig. 16C and Fig.16D A more detailed construction of word lines and pass transistors is described.

[0053] Despite Figure 2 Although not shown in detail, the peripheral circuit PC and various circuits may be formed in the second semiconductor layer L2 by forming semiconductor elements (eg, transistors) and patterns for wiring the semiconductor elements on the second substrate SUB2 of the second semiconductor layer L2.

[0054] Figure 3 is a block diagram illustrating a nonvolatile memory device according to some example embodiments.

[0055] Reference Figure 3 , the nonvolatile memory device 500 may include a memory cell array 510 , an address decoder 520 , a page buffer circuit 530 , a data input / output (I / O) circuit 540 , a voltage generator 550 , and a control circuit 560 .

[0056] The nonvolatile memory device 500 may have the above-described BVNAND structure. In some example embodiments, the memory cell array 510 may be formed in the first semiconductor layer L1, and at least a portion of the address decoder 520, the page buffer circuit 530, the data I / O circuit 540, the voltage generator 550, and the control circuit 560 may be formed in the second semiconductor layer L2.

[0057] The memory cell array 510 may be connected to the address decoder 520 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. The memory cell array 510 may also be connected to the page buffer circuit 530 via a plurality of bit lines BL. The memory cell array 510 may include a plurality of memory cells (e.g., a plurality of nonvolatile memory cells) connected to a plurality of word lines WL and a plurality of bit lines BL. The memory cell array 510 may be divided into a plurality of memory blocks BLK1, BLK2, ..., BLKz (where z is any positive integer), and each of the plurality of memory blocks BLK1, BLK2, ..., BLKz includes a memory cell. In addition, each of the plurality of memory blocks BLK1, BLK2, ..., BLKz may be divided into a plurality of pages.

[0058] In some example embodiments, as will be referred to Figure 4 and Figure 5 Described in more detail, the memory cell array 510 may be a three-dimensional memory cell array that may be formed on a substrate in a three-dimensional structure (or a vertical structure). In this example, the memory cell array 510 may include a plurality of cell strings (e.g., a plurality of vertical NAND strings) oriented vertically, such that at least one memory cell is located above another memory cell.

[0059] The control circuit 560 may receive a command CMD and an address ADDR from outside the nonvolatile memory device 500 (e.g., from a host device and / or a memory controller), and the control circuit 560 may be configured to control an erase operation, a program operation, and a read operation of the nonvolatile memory device 500 based on the command CMD and the address ADDR. The erase operation may include executing an erase cycle sequence, and the program operation may include executing a program cycle sequence. Each program cycle may include a program operation and a program verification operation. Each erase cycle may include an erase operation and an erase verification operation. The read operation may include a normal read operation and a data recovery read operation.

[0060] In some example embodiments, based on the command CMD, the control circuit 560 may generate a control signal CON that may be used to control the voltage generator 550, and the control circuit 560 may generate a control signal PBC that may be used to control the page buffer circuit 530. The control circuit 560 may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 560 may provide the row address R_ADDR to the address decoder 520 and may provide the column address C_ADDR to the data I / O circuit 540.

[0061] The address decoder 520 may be connected to the memory cell array 510 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. In some example embodiments, in a data erase / write / read operation, based on a row address R_ADDR, the address decoder 520 may determine at least one of the plurality of word lines WL as a selected word line, may determine at least one of the plurality of string selection lines SSL as a selected string selection line, and may determine at least one of the plurality of ground selection lines GSL as a selected ground selection line.

[0062] The address decoder 520 may include a plurality of pass transistors (PT) 522 and a plurality of drivers (DRV) 524. Figure 6 A more detailed construction of the plurality of pass transistors 522 and the plurality of drivers 524 is described.

[0063] The voltage generator 550 may generate a voltage VS that may be used for the operation of the nonvolatile memory device 500 based on the power PWR and the control signal CON. The voltage VS may be applied to a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL via the address decoder 520. In addition, the voltage generator 550 may generate an erase voltage VERS for a data erase operation based on the power PWR and the control signal CON.

[0064] The page buffer circuit 530 may be connected to the memory cell array 510 via a plurality of bit lines BL. The page buffer circuit 530 may include a plurality of page buffers. The page buffer circuit 530 may store data DAT to be programmed into the memory cell array 510 or may read data DAT sensed from the memory cell array 510. In other words, the page buffer circuit 530 may operate as a write driver and / or a sense amplifier according to an operation mode of the nonvolatile memory device 500.

[0065] The data I / O circuit 540 may be connected to the page buffer circuit 530 via the data line DL. Based on the column address C_ADDR, the data I / O circuit 540 may provide data DAT from the outside of the nonvolatile memory device 500 to the memory cell array 510 via the page buffer circuit 530, or may provide data DAT from the memory cell array 510 to the outside of the nonvolatile memory device 500.

[0066] Figure 4 is included in Figure 3 FIG. 1 is a perspective view of an example of a memory block BLKi in a memory cell array of a nonvolatile memory device.

[0067] Reference Figure 4 , the memory block BLKi may include a plurality of cell strings (eg, a plurality of vertical NAND strings) that may be formed on a substrate in a three-dimensional structure (or a vertical structure). The memory block BLKi includes a structure extending along a first direction D1, a second direction D2, and a third direction D3.

[0068] A substrate 111 (e.g., an upper substrate of the first semiconductor layer L1) may be provided. In some example embodiments, the substrate 111 may have a well having a first type of charge carrier impurities (e.g., a first conductivity type) therein. In some example embodiments, the substrate 111 may have a p-well formed by implanting a Group 3 (III) element such as boron (B). Specifically, the substrate 111 may have a pocket p-well disposed within an n-well. In some example embodiments, the substrate 111 has a p-type well (or a p-type pocket well). However, the conductivity type of the substrate 111 is not limited to the p-type.

[0069] A plurality of doped regions 311, 312, 313, and 314 arranged along the second direction D2 are disposed in / on the substrate 111. These plurality of doped regions 311 to 314 may have a second type of charge carrier impurities (e.g., a second conductivity type) different from the first type of the substrate 111. In some example embodiments, the first to fourth doped regions 311 to 314 may have an n-type. However, the conductivity types of the first to fourth doped regions 311 to 314 are not limited to the n-type.

[0070] A plurality of insulating materials 112 extending along the first direction D1 are sequentially disposed in a third direction D3 on a region of the substrate 111 between the first doping region 311 and the second doping region 312. In some example embodiments, the plurality of insulating materials 112 are disposed in the third direction D3 and are spaced apart by a specific distance. In some example embodiments, the insulating material 112 may include an insulating material such as an oxide layer.

[0071] In the region of the substrate 111 between the first doping region 311 and the second doping region 312, a plurality of pillars 113 penetrating or extending through the insulating material in the third direction D3 are sequentially disposed and spaced apart along the first direction D1. In some example embodiments, the plurality of pillars 113 may penetrate the insulating material 112 and may contact the substrate 111.

[0072] In some example embodiments, each pillar 113 may include a plurality of materials. In some example embodiments, the channel layer 114 of each pillar 113 may include a silicon material having a first conductivity type. In some example embodiments, the channel layer 114 of each pillar 113 may include a silicon material having the same conductivity type as the substrate 111. In some example embodiments, the channel layer 114 of each pillar 113 includes p-type silicon. However, the channel layer 114 of each pillar 113 is not limited to p-type silicon.

[0073] The inner material 115 of each pillar 113 includes an insulating material. In some example embodiments, the inner material 115 of each pillar 113 may include an insulating material such as silicon oxide. In some examples, the inner material 115 of each pillar 113 may include an air gap. As discussed again, the term "gas" may refer to atmospheric air or other gases that may be present during the manufacturing process.

[0074] On the region between the first doped region 311 and the second doped region 312, the insulating layer 116 may be disposed along the exposed surfaces of the insulating material 112, the pillar 113, and the substrate 111. In some example embodiments, as shown, the insulating layer 116 disposed on the surface of the insulating material 112 may be between the pillar 113 and the plurality of stacked first conductive materials 211, 221, 231, 241, 251, 261, 271, 281, and 291. In some examples, the insulating layer 116 may not be disposed between the pillar 113 and the first conductive material corresponding to the ground selection line GSL (e.g., 211) and the string selection line SSL (e.g., 291) among the first conductive materials 211 to 291, and may not exist between the pillar 113 and the first conductive material corresponding to the ground selection line GSL (e.g., 211) and the string selection line SSL (e.g., 291) among the first conductive materials 211 to 291. In this example, the ground selection line GSL is the lowermost first conductive material in the stack of first conductive materials 211 to 291 , and the string selection line SSL is the uppermost first conductive material in the stack of first conductive materials 211 to 291 .

[0075] In the region between the first doping region 311 and the second doping region 312, a plurality of first conductive materials 211 to 291 may be disposed on the surface of the insulating layer 116. In some example embodiments, the first conductive material 211 extending along the first direction D1 may be disposed between the insulating material 112 adjacent to the substrate 111 and the substrate 111. In more detail, the first conductive material 211 extending along the first direction D1 is disposed between the insulating layer 116 at the bottom of the insulating material 112 adjacent to the substrate 111 and the insulating layer 116 at the top surface of the substrate 111.

[0076] The first conductive material extending along the first direction D1 may be disposed between the insulating layer 116 at the top of a specific insulating material among the insulating materials 112 and the insulating layer 116 at the bottom of a specific insulating material among the insulating materials 112. In some example embodiments, a plurality of first conductive materials 221 to 281 extending along the first direction D1 may be disposed between the insulating materials 112, and it may be understood that the insulating layer 116 is disposed between the insulating material 112 and the first conductive materials 221 to 281. The first conductive materials 211 to 291 may be formed of a conductive metal, but in other embodiments, the first conductive materials 211 to 291 may include a conductive material such as polysilicon.

[0077] The same structure as that on the region between the first doping region 311 and the second doping region 312 may be provided in the region between the second doping region 312 and the third doping region 313. In the region between the second doping region 312 and the third doping region 313, a plurality of insulating materials 112 extending along the first direction D1 are provided. Also, a plurality of pillars 113 sequentially arranged along the first direction D1 and penetrating or extending through the plurality of insulating materials 112 along the third direction D3 may be provided. An insulating layer 116 may be provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, and a plurality of first conductive materials 211 to 291 may extend along the first direction D1. Similarly, the same structure as that on the region between the first doping region 311 and the second doping region 312 may be provided in the region between the third doping region 313 and the fourth doping region 314.

[0078] A plurality of drain regions 320 may be disposed on the plurality of pillars 113, respectively. The drain region 320 may include a silicon material doped with a second type of charge carrier impurity. In some example embodiments, the drain region 320 may include a silicon material doped with an n-type dopant. In some example embodiments, the drain region 320 includes an n-type silicon material. However, the drain region 320 is not limited to an n-type silicon material.

[0079] On the drain region 320, a plurality of second conductive materials 331, 332, and 333 extending along the second direction D2 are provided. The second conductive materials 331 to 333 may be arranged along the first direction D1, spaced apart from each other by a specific distance. The second conductive materials 331 to 333 are connected to the drain region 320 in corresponding regions, respectively. The drain region 320 and the second conductive material 333 extending along the second direction D2 may be connected by each contact plug. In some example embodiments, each contact plug may be a conductive plug formed of a conductive material such as a metal. The second conductive materials 331 to 333 may include a metal material. The second conductive materials 331 to 333 may include a conductive material such as polysilicon.

[0080] exist Figure 4 In the example of the present invention, the first conductive materials 211 to 291 may be used to form word lines WL, string selection lines SSL, and ground selection lines GSL. In some example embodiments, the first conductive materials 221 to 281 may be used to form word lines WL, wherein conductive materials belonging to the same layer may be interconnected. The second conductive materials 331 to 333 may be used to form bit lines BL. The number of layers of the first conductive materials 211 to 291 may be variously changed according to the process and control technology.

[0081] Figure 5 It shows reference Figure 4 A circuit diagram depicting the equivalent circuit of the memory block.

[0082] Figure 5 The memory block BLKi may be formed on a substrate in a three-dimensional structure (or a vertical structure). In some example embodiments, a plurality of NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0083] Reference Figure 5 , the memory block BLKi may include a plurality of NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground selection transistor GST. In some example embodiments, the bit lines BL1 to BL3 may correspond to Figure 4 The second conductive materials 331 to 333 in the common source line CSL can be Figure 4 The first doping region 311 to the fourth doping region 314 are interconnected to form.

[0084] Each string selection transistor SST can be connected to a corresponding string selection line (one of SSL1, SSL2, and SSL3). Multiple memory cells MC1 to MC8 can be connected to corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively. Each ground selection transistor GST can be connected to a corresponding ground selection line (one of GSL1, GSL2, and GSL3). Each string selection transistor SST can be connected to a corresponding bit line (for example, one of BL1 to BL3), and each ground selection transistor GST can be connected to a common source line CSL. Figure 5 In the example, some of the string selection transistors SST are connected to the same bit line (e.g., one of BL1 to BL3) to connect the corresponding NAND strings to the appropriately selected same bit line via selection voltages applied to appropriate string selection lines SSL1 to SSL3 and ground selection lines GSL1 to GSL3.

[0085] Cell strings commonly connected to one bit line may form one column, and cell strings connected to one string selection line may form a row. In some example embodiments, cell strings NS11, NS21, and NS31 connected to the first bit line BL1 may correspond to the first column, and cell strings NS11, NS12, and NS13 connected to the first string selection line SSL1 may form the first row.

[0086] Word lines (e.g., WL1) having the same height may be commonly connected, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated. Memory cells located at the same semiconductor layer share word lines. Cell strings in the same row share string selection lines. Common source lines CSL are commonly connected to all cell strings.

[0087] exist Figure 5 , the memory block BLKi is shown as being connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3, and each of the NAND strings NS11 to NS33 is shown as including eight memory cells MC1 to MC8. However, the present disclosure is not limited thereto. In some example embodiments, each memory block may be connected to any number of word lines and bit lines, and each NAND string may include any number of memory cells.

[0088] The three-dimensional vertical array structure may include vertical NAND strings oriented vertically such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer. The following patent documents, which are incorporated herein by reference in their entirety, describe suitable constructions for memory cell arrays including a 3D vertical array structure, wherein the three-dimensional memory array is constructed into multiple levels and word lines and / or bit lines are shared between levels: U.S. Patent No. 7,679,133; U.S. Patent Nos. 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0089] Although the memory cell array included in the nonvolatile memory device according to some example embodiments is described based on a NAND flash memory device, the nonvolatile memory device according to some example embodiments may be any nonvolatile memory device, such as a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.

[0090] Figure 6 It is shown that the Figure 3 A block diagram of an example of an address decoder in a non-volatile memory device.

[0091] Reference Figure 6 , the address decoder 600 may be connected to the memory cell array 510 through the string selection line SSL, the word lines WL1, . . . , WLn, and the ground selection line GSL, and may include a transfer switch circuit 610 and a driver circuit 620. The address decoder 600 may be referred to as a row decoder, a word line decoder, etc.

[0092] The transmission switch circuit 610 may include a plurality of pass transistors SPT1, PT1, ..., PTn, and GPT1. For example, the plurality of pass transistors SPT1, PT1 to PTn, and GPT1 may include a string pass transistor SPT1 connected to a string selection line SSL, word line pass transistors PT1 to PTn connected to word lines WL1 to WLn, and a ground pass transistor GPT1 connected to a ground selection line GSL.

[0093] The driver circuit 620 may control the switching operation of the plurality of pass transistors SPT1, PT1 to PTn, and GPT1, and may control the operation of supplying voltages VS1, VW1, ..., VWn, and VG1 to the memory cell array 510 through the plurality of pass transistors SPT1, PT1 to PTn, and GPT1. The driver circuit 620 may include a pass transistor driver 630, a string selection line driver 640, a word line driver 650, and a ground selection line driver 660.

[0094] The transistor driver 630 can be based on a voltage generator (e.g., Figure 3 A plurality of switch control signals SCS are generated by using a high voltage VPPH provided by a voltage generator 550 in the memory cell array 510. The plurality of switch control signals SCS may be applied to gate electrodes of the plurality of pass transistors SPT1, PT1 to PTn, and GPT1. Switching operations of the plurality of pass transistors SPT1, PT1 to PTn, and GPT1 may be controlled in response to the plurality of switch control signals SCS. The timing of applying voltages VS1, VW1 to VWn, and VG1 to the memory cell array 510 may be controlled by switching operations of the plurality of pass transistors SPT1, PT1 to PTn, and GPT1.

[0095] The plurality of pass transistors SPT1, PT1 to PTn, and GPT1 may be implemented so that the string selection line SSL, the word lines WL1 to WLn, and the ground selection line GSL are respectively electrically connected to the string selection line driver 640, the word line driver 650, and the ground selection line driver 660 in response to activation of the plurality of switch control signals SCS. For example, the plurality of switch control signals SCS may be generated based on the high voltage VPPH and may have a voltage level corresponding to the high voltage VPPH, and thus the plurality of pass transistors SPT1, PT1 to PTn, and GPT1 may include high voltage transistors capable of withstanding the high voltage.

[0096] The string selection line driver 640 may output one of the on voltage VON and the off voltage VOFF provided from the voltage generator as the string selection voltage VS1. When the string pass transistor SPT1 is turned on, the string selection voltage VS1 may be applied to the memory cell array 510 through the string selection line SSL. When the string pass transistor SPT1 is turned on, the string selection voltage VS1 may be applied to the memory cell array 510 through the string selection line SSL. For example, during a programming operation, the string selection line driver 640 may supply the string selection voltage VS1 to turn on all string selection transistors in a selected memory block.

[0097] According to a non-volatile memory device (e.g., Figure 3In order to operate the nonvolatile memory device 500 of the present invention, the word line driver 650 may output one of the program voltage VPGM, the pass voltage VPASS, the verification voltage VPV, the read voltage VRD, and the negative voltage VNEG provided from the voltage generator to a corresponding word line among the word lines WL1 to WLn. When one of the word line pass transistors PT1 to PTn is turned on, a corresponding word line voltage among the word line voltages VW1 to VWn may be provided to the memory cell array 510 through the corresponding word line among the word lines WL1 to WLn.

[0098] The ground selection line driver 660 may output one of the on voltage VON and the off voltage VOFF provided from the voltage generator as the ground selection voltage GS1. When the ground pass transistor GPT1 is turned on, the ground selection voltage GS1 may be applied to the memory cell array 510 through the ground selection line GSL.

[0099] In some example embodiments, each of the pass transistor driver 630, the string selection line driver 640, the word line driver 650, and the ground selection line driver 660 may include a plurality of sub-drivers controlling a portion or part of the memory cell array 510. In some example embodiments, the address decoder 600 may operate based on a row address R_ADDR.

[0100] In some example embodiments, the pass transistors PT1 to PTn connected to the word lines WL1 to WLn may be Figure 1 and Figure 2 The pass transistors PT, PTa, and PTb of the described example embodiments. For example, the pass transistors PT1 to PTn may be separately provided in the first semiconductor layer L1 and the second semiconductor layer L2. For example, among the pass transistors PT1 to PTn, at least one of the width and length of the pass transistor in the first semiconductor layer L1 and the pass transistor in the second semiconductor layer L2 may be different from each other.

[0101] Fig. 7A , Figure 7B and Figure 7C is a cross-sectional view for describing a channel hole included in a nonvolatile memory device according to example embodiments.

[0102] Reference Fig. 7A , the channel hole CHa can correspond to Figure 2 The channel CH and Figure 4A column 113 in the channel hole CHa. A column including a channel layer 114 and an inner layer (inner material) 115 may be formed in the channel hole CHa. For example, the channel hole CHa may be drilled from top to bottom, and a diameter Da at a position where formation of the channel hole CHa starts (e.g., at the top) may be greater than a diameter Db at a position where formation of the channel hole CHa ends (e.g., at the bottom).

[0103] Reference Figure 7B , the channel hole CHb may include a first sub-channel hole SCH1 and a second sub-channel hole SCH2. Fig. 7A Like the channel hole CHa, a column including the channel layer 114 and the inner layer 115 may be formed in the first sub-channel hole SCH1, and a column including the channel layer 124 and the inner layer 125 may be formed in the second sub-channel hole SCH2. Fig. 7A If the channel holes are formed one at a time as in the example of Figure 7B As in the example of FIG. 2 , a plurality of sub-channel holes are used to form one channel hole. Figure 7B Examples of may be referred to as a multi-stack string structure or a multi-stack structure.

[0104] Figure 7B A double stack structure is shown in which two sub-channel holes SCH1 and SCH2 are sequentially formed or extended along the third direction D3 within one channel hole CHb. For example, the first sub-channel hole SCH1 and the second sub-channel hole SCH2 may be sequentially stacked on the first substrate SUB1. For example, the first sub-channel hole SCH1 as a lower sub-channel hole may be formed first, and then the second sub-channel hole SCH2 as an upper sub-channel hole may be formed later. However, the present disclosure is not limited thereto, and three or more sub-channel holes may be included in one channel hole.

[0105] Reference Figure 7C , the channel hole of each cell string may include a first sub-channel hole 410 and a second sub-channel hole 420. The channel hole may be referred to as a pillar. The first sub-channel hole 410 may include a channel layer 411, an inner material 412, and an insulating layer 413. The second sub-channel hole 420 may include a channel layer 421, an inner material 422, and an insulating layer 423. The channel layer 411 of the first sub-channel hole 410 may be connected to the channel layer 421 of the second sub-channel hole 420 through a p-type silicon pad SIP.

[0106] The sub-channel holes 410 and 420 can be formed using a stop line 435 having an appropriate etching rate. For example, the stop line 435 can be formed of polysilicon, and the other word lines 431, 432, 433, 434, 436, 437, and 438 can be formed of a metal such as tungsten to achieve an appropriate etching rate. For example, although there is a difference depending on the doping concentration of polysilicon, the resistance of the stop line 435 can be significantly greater than the corresponding resistance of the resistance of the remaining word lines 431 to 434 and 436 to 438, for example, the resistance of the stop line 435 can be about six times the corresponding resistance of the resistance of the remaining word lines 431 to 434 and 436 to 438.

[0107] The memory cells connected to the stop line 435 may not be suitable for storing data, so the stop line 435 and the memory cells connected thereto may be respectively referred to as dummy word lines and dummy memory cells. The dummy word lines and the dummy memory cells connected thereto may also be referred to as buffer cells, junction cells, etc.

[0108] The word lines 431 to 434 below the stop line 435 (e.g., word lines 431 to 434 formed to correspond to the first sub-channel hole 410) can be defined as first stacked word lines and / or first word lines. Similarly, the word lines 436 to 438 on the stop line 435 (e.g., word lines 436 to 438 formed to correspond to the second sub-channel hole 420) can be defined as second stacked word lines and / or second word lines.

[0109] In some example embodiments, as will be referred to Fig. 9 As described, when the pass transistors PT are arranged separately according to example embodiments, the pass transistors connected to the word lines in the same stack (eg, word lines formed to correspond to the same sub-channel hole) may be formed in the same substrate. Fig.11 and Fig.12 As described, when the pass transistors PT are individually arranged according to example embodiments, word lines in the same stack may be divided into two or more groups, and pass transistors connected to the word lines of the same group may be formed in the same substrate.

[0110] Fig. 8A , Figure 8B and Figure 8C is a diagram for describing a core area and an extension area included in a nonvolatile memory device according to example embodiments.

[0111] Reference Fig. 8A , showing Figure 1 An example of a layout arrangement of the first semiconductor layer L1 and the second semiconductor layer L2 in the nonvolatile memory device 10 is shown.

[0112] The first semiconductor layer L1 may include a memory cell array MCA, and may also include a core region CR and an extension region (or word line extension region) EXR_L1. The core region CR may include a plurality of memory cells MC. The extension region EXR_L1 may be formed adjacent to a first side of the core region CR, and may include some of a plurality of pass transistors PT. The extension region EXR_L1 may not include the memory cells MC, and a structure for electrically connecting the word line WL to other components / circuits may be formed or included in the extension region EXR_L1. For example, as will be referred to Fig. 9 As described, the extension region EXR_L1 may include a word line contact for electrical connection between the word line WL and the pass transistor PT.

[0113] The second semiconductor layer L2 may include a peripheral circuit PC (not shown), and may also include an extension region EXR_L2 corresponding to the extension region EXR_L1 of the first semiconductor layer L1. For example, when the first semiconductor layer L1 and the second semiconductor layer L2 are stacked and viewed on the same plane, the extension region EXR_L1 and the extension region EXR_L2 may overlap or match. Other pass transistors PT of the plurality of pass transistors PT may be formed in the extension region EXR_L2.

[0114] although Fig. 8A The first semiconductor layer L1 is shown to include only one extension region EXR_L1 adjacent to the first side of the core region CR, but the present disclosure is not limited thereto. For example, the first semiconductor layer L1 may also include a second extension region adjacent to a second side of the core region CR opposite to the first side of the core region CR, and thus the second semiconductor layer L2 may also include two extension regions.

[0115] Reference Figure 8B , showing the inclusion of Fig. 8A FIG. 5 is a plan view of the core region CR and the extension region EXR_L1 in the first semiconductor layer L1.

[0116] A plurality of channels CH for the memory cells MC may be provided in the core region CR. The channels CH may correspond to Figure 4 The pillars 113 in the figure can be used as regions for forming channels of NAND strings.

[0117] A step (or staircase) structure ST in which conductive materials for forming word lines WL are stacked in a step shape may be provided in the extension region EXR_L1. The conductive materials may correspond to Figure 4 In the core region CR, the first conductive material 211 to 291 may be formed as shown in FIG. Figure 4The conductive material is formed as described to form the word line WL. However, in the extension region EXR_L1, the conductive material may be formed into a step structure ST, and the word line WL may be electrically connected to other components / circuits.

[0118] To form word lines WL extending in the first direction D1, word line cutting regions WCUTa, WCUTb, WCUTc, WCUTd, WCUTe, WCUTf, and WCUTg may be formed as shown by bold dashed lines. One word line extending in the first direction D1 may be formed by two adjacent word line cutting regions.

[0119] Reference Figure 8C , showing the inclusion of Fig. 8A FIG. 5 is a cross-sectional view of the core region CR and the extension region EXR_L1 in the first semiconductor layer L1.

[0120] The first semiconductor layer L1 may include a first substrate SUB1 and a vertical structure formed on the first substrate SUB1. The first semiconductor layer L1 may also include a contact and a bit line BL electrically connected to the vertical structure. The first semiconductor layer L1 may also include a first insulating layer IL1 covering the vertical structure and various conductive lines. The vertical structure may include a gate conductive layer disposed on the first substrate SUB1.

[0121] In the core region CR, the vertical structure may include a channel CH that penetrates or passes through the gate conductive layer and extends in the third direction D3 on the top surface of the first substrate SUB1. The gate conductive layer may include word lines WL1 to WL4. Although not shown in detail, the gate conductive layer may also include a ground selection line and a string selection line, and an insulating interlayer may be below or above each of the gate conductive layers. For example, a conductive layer including a conductive material (e.g., word lines WL1 to WL4) and an insulating interlayer including an insulating material may be alternately stacked in the third direction D3.

[0122] In the extension region EXR_L1 , the vertical structure may include a step structure ST The step structure ST may be implemented to have a step shape in a cross-sectional view with respect to (or associated with or related to) the word lines WL1 to WL4 .

[0123] Fig. 9 yes Figure 2 A cross-sectional view of an example of a nonvolatile memory device.

[0124] Reference Fig. 9 , the channel CH can have a reference Figure 7BThe double stack structure of the description. The plurality of word lines WL11, WL12, WL13, WL14, WL21, WL22, WL23 and WL24 may include first word lines WL11 to WL14 and second word lines WL21 to WL24. The plurality of pass transistors PT11, PT12, PT13, PT14, PT21, PT22, PT23 and PT24 may include first pass transistors PT11 to PT14 and second pass transistors PT21 to PT24. For ease of description, in Fig. 9 The ground / string selection line and the ground / string pass transistor are omitted in the following text for the sake of brevity. Figures 2 to 8C The description is repeated or overlapped, and the exemplary embodiments will be described focusing mainly on the configuration in the extended region EXR.

[0125] The first word lines WL11 to WL14 may be stacked on the first substrate SUB1 in the third direction D3, may be formed to correspond to the first sub-channel hole at the bottom of the channel CH, and may be referred to as the first stacked word lines. The second word lines WL21 to WL24 may be stacked on the first word lines WL11 to WL14 in the third direction D3, may be formed to correspond to the second sub-channel hole at the top of the channel CH, and may be referred to as the second stacked word lines. For ease of explanation, Fig. 9 The number of word lines in one stack is shown as four, however, example embodiments are not limited thereto. Figure 7C The dummy word line and / or the buffer unit of the stop line 435 in the embodiment may be formed or arranged between the first word lines WL11 to WL14 and the second word lines WL21 to WL24, but in Fig. 9 Not shown.

[0126] The first pass transistors PT11 to PT14 may be connected to the first word lines WL11 to WL14. The second pass transistors PT21 to PT24 may be connected to the second word lines WL21 to WL24. The first pass transistors PT11 to PT14 and the second pass transistors PT21 to PT24 may be disposed in the extension region EXR. The extension region EXR may correspond to both the extension region EXR_L1 of the first semiconductor layer L1 and the extension region EXR_L2 of the second semiconductor layer L2.

[0127] Fig. 9 An example is shown in which pass transistors connected to word lines in the same stack are formed in the same substrate. For example, first pass transistors PT11 to PT14 may be formed in the first substrate SUB1 of the first semiconductor layer L1, and second pass transistors PT21 to PT24 may be formed in the second substrate SUB2 of the second semiconductor layer L2.

[0128] The extension region EXR may include a plurality of word line contacts WC11a, WC12a, WC13a, WC14a, WC21a, WC22a, WC23a, and WC24a for electrical connection between the plurality of word lines WL11 to WL14 and WL21 to WL24 and the plurality of pass transistors PT11 to PT14 and PT21 to PT24.

[0129] The plurality of word line contacts WC11a to WC14a and WC21a to WC24a may include first word line contacts WC11a to WC14a and second word line contacts WC21a to WC24a. The first word line contacts WC11a to WC14a may electrically connect the first word lines WL11 to WL14 with the first pass transistors PT11 to PT14, and the second word line contacts WC21a to WC24a may electrically connect the second word lines WL21 to WL24 with the second pass transistors PT21 to PT24.

[0130] In some example embodiments, the first word line contacts WC11a to WC14a and the second word line contacts WC21a to WC24a may be aligned with each other along the third direction D3. For example, the first word line contacts WC11a and the second word line contacts WC21a may be aligned along the third direction D3. For example, when viewed in a plan view, the first word line contacts WC11a and the second word line contacts WC21a aligned with each other may completely overlap and may be disposed at the same position in the first direction D1 and the second direction D2. Although Fig. 9 It is shown that all of the first word line contacts WC11a to WC14a are aligned with all of the second word line contacts WC21a to WC24a, respectively, but the present disclosure is not limited thereto. For example, some of the first word line contacts WC11a to WC14a may be aligned with some of the second word line contacts WC21a to WC24a, and other word line contacts of the first word line contacts WC11a to WC14a may not be aligned with other word line contacts of the second word line contacts WC21a to WC24a.

[0131] In some example embodiments, in order to achieve alignment of the first word line contacts WC11a to WC14a and the second word line contacts WC21a to WC24a, each of the first word line contacts WC11a to WC14a and the second word line contacts WC21a to WC24a may extend in the third direction D3 so that each word line contact corresponds to a portion of the first insulating layer IL1. For example, the first word line contacts WC11a to WC14a may extend in the third direction D3 to correspond only to the first sub-channel holes and the first word lines WL11 to WL14. For example, the second word line contacts WC21a to WC24a may extend in the third direction D3 to correspond only to the second sub-channel holes and the second word lines WL21 to WL24. For example, the height of each of the first word line contacts WC11a to WC21a and the second word line contacts WC21a may be approximately half the height of the first insulating layer IL1.

[0132] In some example embodiments, the extension region EXR may include a plurality of step regions SZ1 and SZ2 and at least one flat region FZ. The plurality of step regions SZ1 and SZ2 may have a step shape in a cross-sectional view relative to at least some of the plurality of word lines WL11 to WL14 and WL21 to WL24. For example, the step region SZ1 may have a step shape in a cross-sectional view relative to the word lines WL11, WL12, WL21, and WL22, and the step region SZ2 may have a step shape in a cross-sectional view relative to the word lines WL13, WL14, WL23, and WL24. The flat region FZ may be between two adjacent step regions SZ1 and SZ2, and may have a flat shape in a cross-sectional view relative to all of the plurality of word lines WL11 to WL14 and WL21 to WL24.

[0133] In some example embodiments, a plurality of word line contacts WC11a to WC14a and WC21a to WC24a may be formed in a plurality of step regions SZ1 and SZ2, and may not be formed in the flat region FZ. For example, word line contacts WC11a, WC12a, WC21a, and WC22a may be formed in the step region SZ1, and word line contacts WC13a, WC14a, WC23a, and WC24a may be formed in the step region SZ2. In other words, a plurality of word line contacts WC11a to WC14a and WC21a to WC24a may be formed by avoiding the flat region FZ. Although Fig. 9 It is shown that the pass transistors PT11 to PT14 and PT21 to PT24 are also formed in the step regions SZ1 and SZ2 similarly to the word line contacts WC11a to WC14a and WC21a to WC24a, but example embodiments are not limited thereto. For example, some of the pass transistors PT11 to PT14 and PT21 to PT24 may be formed in the flat region FZ.

[0134] In some example embodiments, since the first word line contacts WC11a to WC14a and the second word line contacts WC21a to WC24a may be aligned with each other, the step region and the flat region for the first word lines (or first stacked word lines) WL11 to WL14 and the step region and the flat region for the second word lines (or second stacked word lines) WL21 to WL24 may be aligned with each other. In other words, the step region SZ1 may be a step region for the word lines WL11 and WL12 and may also be a step region for the word lines WL21 and WL22, the step region SZ2 may be a step region for the word lines WL13 and WL14 and may also be a step region for the word lines WL23 and WL24, and the flat region FZ may be a flat region for all the word lines WL11 to WL14 and WL21 to WL24.

[0135] As reference Fig. 9 As described, the pass transistors PT11 to PT14 connected to the first stacked word line and the pass transistors PT21 to PT24 connected to the second stacked word line can be arranged separately in the first substrate SUB1 and the second substrate SUB2, respectively. In addition, the pass transistors connected to the word lines in the same stack can be formed in the same substrate. In addition, the word line contacts WC11a to WC14a connected to the first stacked word line and the word line contacts WC21a to WC24a connected to the second stacked word line can be aligned with each other, the step area for the first stacked word line and the step area for the second stacked word line can be aligned with each other, and the flat area for the first stacked word line and the flat area for the second stacked word line can be aligned with each other. Therefore, the extension region EXR can have a relatively reduced area.

[0136] Despite Fig. 9 Although not shown in the figure, an insulating mold structure including an insulating material filled in the third direction D3 may be formed in the first substrate SUB1, and electrical connection between components may be provided by forming a through hole penetrating the insulating mold structure. Fig. 9 Not shown, but in order to electrically connect the word lines WL11 to WL14 and WL21 to WL24 with the pass transistors PT11 to PT14 and PT21 to PT24, wafer interconnections or wirings may be further formed within the first semiconductor layer L1 and the second semiconductor layer L2, and / or bonding pads may be further formed to connect the first semiconductor layer L1 and the second semiconductor layer L2 to each other.

[0137] Fig.10 is included in Fig. 9 A cross-sectional view of an example of a word line contact in a nonvolatile memory device.

[0138] Reference Fig.10 , the word line contact WC may include an insulating layer pattern IP and a conductive pattern MP, and may further include a protruding portion protruding toward the target word line. The word line contact WC may be electrically connected to the target word line through the protruding portion of the conductive pattern MP, and may be electrically insulated from other word lines by the insulating layer pattern IP. However, the present disclosure is not limited thereto, and the configuration of the word line contact WC may be variously determined according to example embodiments.

[0139] Fig.11 and Fig.12 yes Figure 2 A cross-sectional view of an example of a nonvolatile memory device is shown. Fig. 9 Duplicate description.

[0140] Reference Fig.11 , shows an example in which word lines in the same stack are divided into two groups and pass transistors connected to the word lines of the same group are formed in the same substrate.

[0141] exist Fig.11 In the example, among the word lines in the same stack, one of the odd word lines and the even word lines can be set as the first word line group (or the first group of word lines), and the other of the odd word lines and the even word lines can be set as the second word line group (or the second group of word lines).

[0142] For example, the first word lines WL11 to WL14 may be divided into a first word line group WL11 and WL13 and a second word line group WL12 and WL14. For example, when the word line WL11 is the first word line among the word lines WL11 to WL14, the first word line group WL11 and WL13 may include odd word lines WL11 and WL13 among the word lines WL11 to WL14, and the second word line group WL12 and WL14 may include even word lines WL12 and WL14 among the word lines WL11 to WL14. The plurality of pass transistors PT11 to PT14 may include a first pass transistor group PT11 and PT13 and a second pass transistor group PT12 and PT14. The first pass transistor group PT11 and PT13 may include pass transistors PT11 and PT13 connected to the first word line group WL11 and WL13, and the second pass transistor group PT12 and PT14 may include pass transistors PT12 and PT14 connected to the second word line group WL12 and WL14. The first pass transistor group PT11 and PT13 may be formed or arranged in a first substrate SUB1 of the first semiconductor layer L1, and the second pass transistor group PT12 and PT14 may be formed or arranged in a second substrate SUB2 of the second semiconductor layer L2.

[0143] Similarly, the second word lines WL21 to WL24 may be divided into a third word line group WL21 and WL23 and a fourth word line group WL22 and WL24. The second pass transistors PT21 to PT24 may include a third pass transistor group PT21 and PT23 connected to the third word line group WL21 and WL23 and a fourth pass transistor group PT22 and PT24 connected to the fourth word line group WL22 and WL24. The third pass transistor group PT21 and PT23 may be formed in the first substrate SUB1 of the first semiconductor layer L1, and the fourth pass transistor group PT22 and PT24 may be formed in the second substrate SUB2 of the second semiconductor layer L2.

[0144] Although not shown in detail, in some example embodiments, pass transistors PT11 , PT13 , PT21 , and PT23 may be formed in the second substrate SUB2 , and pass transistors PT12 , PT14 , PT22 , and PT24 may be formed in the first substrate SUB1 .

[0145] In some example embodiments, in the first substrate SUB1, the first pass transistor groups PT11 and PT13 and the third pass transistor groups PT21 and PT23 may be alternately arranged one by one along the first direction D1. Similarly, in the second substrate SUB2, the second pass transistor groups PT12 and PT14 and the fourth pass transistor groups PT22 and PT24 may be alternately arranged one by one along the first direction D1.

[0146] The extension region EXR may include a plurality of word line contacts WC11b, WC12b, WC13b, WC14b, WC21b, WC22b, WC23b, and WC24b for electrical connection between the plurality of word lines WL11 to WL14 and WL21 to WL24 and the plurality of pass transistors PT11 to PT14 and PT21 to PT24. The plurality of word line contacts WC11b to WC14b and WC21b to WC24b may include first word line contacts WC11b to WC14b and second word line contacts WC21b to WC24b. The first word line contacts WC11b to WC14b may include first word line contact groups WC11b and WC13b and second word line contact groups WC12b and WC14b. The first word line contact group WC11b and WC13b may electrically connect the first word line group WL11 and WL13 to the first pass transistor group PT11 and PT13. The second word line contact group WC12b and WC14b may electrically connect the second word line group WL12 and WL14 to the second pass transistor group PT12 and PT14. The second word line contacts WC21b to WC24b may include a third word line contact group WC21b and WC23b and a fourth word line contact group WC22b and WC24b. The third word line contact group WC21b and WC23b may electrically connect the third word line group WL21 and WL23 to the third pass transistor group PT21 and PT23. The fourth word line contact group WC22b and WC24b may electrically connect the fourth word line group WL22 and WL24 to the fourth pass transistor group PT22 and PT24.

[0147] In some example embodiments, the first word line contact group WC11b and WC13b, the second word line contact group WC12b and WC14b, the third word line contact group WC21b and WC23b, and the fourth word line contact group WC22b and WC24b may be alternately arranged one by one along the first direction D1.

[0148] In some example embodiments, each of the plurality of word line contacts WC11b to WC14b and WC21b to WC24b may extend in the third direction D3 such that each word line contact corresponds to the entire first insulating layer IL1. For example, the height of each of the plurality of word line contacts WC11b to WC14b and WC21b to WC24b may be substantially equal to the height of the first insulating layer IL1. Fig. 9 Unlike the example of FIG. 1 , the plurality of word line contacts WC11 b to WC14 b and WC21 b to WC24 b may not be aligned along the third direction D3 .

[0149] In some example embodiments, the extension region EXR may include first step regions SZ1_F1 and SZ2_F1 and second step regions SZ1_F2 and SZ2_F2. The first step regions SZ1_F1 and SZ2_F1 may have a step shape in a cross-sectional view relative to at least some of the first word lines WL11 to WL14, and the second step regions SZ1_F2 and SZ2_F2 may have a step shape in a cross-sectional view relative to at least some of the second word lines WL21 to WL24. For example, the first step region SZ1_F1 may have a step shape in a cross-sectional view relative to the first word lines WL11 and WL12, and the second step region SZ1_F2 may have a step shape in a cross-sectional view relative to the second word lines WL21 and WL22.

[0150] In some example embodiments, first word line contact groups WC11b and WC13b and second word line contact groups WC12b and WC14b may be formed in first step regions SZ1_F1 and SZ2_F1. Third word line contact groups WC21b and WC23b and fourth word line contact groups WC22b and WC24b may be formed in second step regions SZ1_F2 and SZ2_F2.

[0151] In some example embodiments, the first step regions SZ1_F1 and SZ2_F1 and the second step regions SZ1_F2 and SZ2_F2 may be alternately arranged one by one along the first direction D1. When the first step regions SZ1_F1 and SZ2_F1 and the second step regions SZ1_F2 and SZ2_F2 are alternately arranged, at least one first flat region between the first step regions SZ1_F1 and SZ2_F1 may be omitted or minimized, and at least one second flat region between the second step regions SZ1_F2 and SZ2_F2 may be omitted or minimized. Fig.11 The first and second planar regions are shown omitted.

[0152] Reference Fig.12 , shows an example in which word lines in the same stack are divided into two groups and pass transistors connected to the word lines of the same group are formed in the same substrate. Fig.11 Duplicate description.

[0153] exist Fig.12 In the example of , among the word lines in the same stack, K word lines sequentially or continuously stacked in the third direction D3 may be set as a first word line group, and then other K word lines sequentially stacked in the third direction D3 may be set as a second word line group, where K is a positive integer greater than or equal to 2. For example, Fig.12 The case where K=2 is shown.

[0154] For example, the first word lines WL11 to WL14 may be divided into a first word line group WL11 and WL12 and a second word line group WL13 and WL14. For example, among the first word lines WL11 to WL14, the first word line group WL11 and WL12 may include two word lines WL11 and WL12 stacked sequentially, and the second word line group WL13 and WL14 may include two word lines WL13 and WL14 stacked sequentially and adjacent to the first word line group WL11 and WL12. Although not shown in detail, when the first word line further includes word lines WL1A, WL1B, WL1C, and WL1D sequentially formed below the word line WL14, the word lines WL1A and WL1B may be included in the first word line group, and the word lines WL1C and WL1D may be included in the second word line group. Among the first pass transistors PT11 to PT14 connected to the first word lines WL11 to WL14, the first pass transistor group PT11 and PT12 connected to the first word line group WL11 and WL12 can be formed in the first substrate SUB1 of the first semiconductor layer L1, and the second pass transistor group PT13 and PT14 connected to the second word line group WL13 and WL14 can be formed in the second substrate SUB2 of the second semiconductor layer L2.

[0155] Similarly, the second word lines WL21 to WL24 may be divided into a third word line group WL21 and WL22 and a fourth word line group WL23 and WL24. Among the second pass transistors PT21 to PT24 connected to the second word lines WL21 to WL24, the third pass transistor group PT21 and PT22 connected to the third word line group WL21 and WL22 may be formed in the second substrate SUB2 of the second semiconductor layer L2, and the fourth pass transistor group PT23 and PT24 connected to the fourth word line group WL23 and WL24 may be formed in the first substrate SUB1 of the first semiconductor layer L1.

[0156] Although not shown in detail, in some example embodiments, pass transistors PT21 and PT22 may be formed in the first substrate SUB1, and pass transistors PT23 and PT24 may be formed in the second substrate SUB2. In some example embodiments, pass transistors PT11, PT12, PT23, and PT24 may be formed in the second substrate SUB2, and pass transistors PT13, PT14, PT21, and PT22 may be formed in the first substrate SUB1.

[0157] In some example embodiments, in the first substrate SUB1, the first pass transistor groups PT11 and PT12 and the fourth pass transistor groups PT23 and PT24 may be alternately arranged two by two (e.g., K by K) along the first direction D1. In the second substrate SUB2, the third pass transistor groups PT21 and PT22 and the second pass transistor groups PT13 and PT14 may be alternately arranged two by two along the first direction D1.

[0158] In some example embodiments, the first word line contact group WC11b and WC12b, the third word line contact group WC21b and WC22b, the second word line contact group WC13b and WC14b, and the fourth word line contact group WC23b and WC24b may be alternately arranged two by two along the first direction D1.

[0159] As reference Fig.11 and Fig.12 As described, the pass transistors PT11 to PT14 connected to the first stack word line and the pass transistors PT21 to PT24 connected to the second stack word line can be arranged separately in the first substrate SUB1 and the second substrate SUB2, respectively. In addition, the word lines in the same stack can be divided into two groups, and the pass transistors connected to the word lines of the same group can be formed in the same substrate. In addition, the flat area between the step areas can be omitted or minimized. Therefore, the extension area EXR can have a relatively reduced area.

[0160] although Fig.11 and Fig.12 It is shown that the word lines in the same stack are divided into two groups, but example embodiments are not limited thereto. For example, the word lines in the same stack may be grouped in at least one of various ways.

[0161] Fig.13A and Fig. 13B is a perspective view of a nonvolatile memory device according to an example embodiment. Figure 1 Duplicate description.

[0162] Reference Fig.13A , the nonvolatile memory device 10a may include a first semiconductor layer L1, a second semiconductor layer L2, and a plurality of pass transistors PT, and may further include a plurality of drivers DRV.

[0163] The plurality of drivers DRV may control the switching operations of the plurality of pass transistors PT. For example, the plurality of drivers DRV may correspond to Figure 3 The plurality of drivers 524 in the Figure 6 At least a portion of the driver circuit 620 in.

[0164] As reference Figure 2As described, when the plurality of pass transistors PT include a first pass transistor PTa and a second pass transistor PTb, the plurality of drivers DRV may include a first driver configured to control a switching operation of the first pass transistor PTa and a second driver configured to control a switching operation of the second pass transistor PTb. For example, the first driver may be formed in a first substrate SUB1 of a first semiconductor layer L1 and may be adjacent to the first pass transistor PTa, and the second driver may be formed in a second substrate SUB2 of a second semiconductor layer L2 and may be adjacent to the second pass transistor PTb.

[0165] Reference Fig. 13B , the nonvolatile memory device 10 b includes a first semiconductor layer L1 , a second semiconductor layer L2 , and a plurality of pass transistors PT, and may further include a plurality of drivers DRV.

[0166] In addition to a plurality of drivers DRV (eg, both a first driver and a second driver) being formed in the second substrate SUB2 of the second semiconductor layer L2, the nonvolatile memory device 10b may be formed with Fig.13A The nonvolatile memory device 10a is substantially the same.

[0167] Although not shown in detail, in some example embodiments, a plurality of drivers DRV (eg, both a first driver and a second driver) may be formed in the first substrate SUB1 of the first semiconductor layer L1.

[0168] Fig.14A and Fig. 14B yes Figure 2 A cross-sectional view of an example of a nonvolatile memory device is shown. Fig. 9 , Fig.11 and Fig.12 Duplicate description.

[0169] Reference Fig.14A , the channel CH may have a three-stack structure. The plurality of word lines WL15, WL16, WL25, WL26, WL35, and WL36 may include first word lines WL15 and WL16, second word lines WL25 and WL26, and third word lines WL35 and WL36. The plurality of pass transistors PT15, PT16, PT25, PT26, PT35, and PT36 may include first pass transistors PT15 and PT16, second pass transistors PT25 and PT26, and third pass transistors PT35 and PT36.

[0170] The first word lines WL15 and WL16 may be stacked on the first substrate SUB1 in the third direction D3 and may be formed to correspond to the first sub-channel hole at the bottom of the channel CH. The second word lines WL25 and WL26 may be stacked on the first word lines WL15 and WL16 in the third direction D3 and may be formed to correspond to the second sub-channel hole in the middle of the channel CH. The third word lines WL35 and WL36 may be stacked on the second word lines WL25 and WL26 in the third direction D3 and may be formed to correspond to the third sub-channel hole at the top of the channel CH. For ease of explanation, the number of word lines in one stack is Fig.14A Two are shown in FIG. 1 , and it is understood that the present disclosure is not limited thereto.

[0171] The first pass transistors PT15 and PT16 may be connected to the first word lines WL15 and WL16, the second pass transistors PT25 and PT26 may be connected to the second word lines WL25 and WL26, and the third pass transistors PT35 and PT36 may be connected to the third word lines WL35 and WL36. The first word line contacts WC15a and WC16a may electrically connect the first word lines WL15 and WL16 with the first pass transistors PT15 and PT16, the second word line contacts WC25a and WC26a may electrically connect the second word lines WL25 and WL26 with the second pass transistors PT25 and PT26, and the third word line contacts WC35a and WC36a may electrically connect the third word lines WL35 and WL36 with the third pass transistors PT35 and PT36.

[0172] as Fig. 9 For example, Fig.14A An example is shown in which the pass transistors connected to the word lines in the same stack are formed in the same substrate and at least some of the word line contacts WC15a, WC16a, WC25a, WC26a, WC35a and WC36a are aligned along the third direction D3. For example, the first pass transistors PT15 and PT16 may be formed in the first substrate SUB1 of the first semiconductor layer L1, the third pass transistors PT35 and PT36 may be formed in the second substrate SUB2 of the second semiconductor layer L2, and the first word line contacts WC15a and WC16a and the third word line contacts WC35a and WC36a may be aligned with each other along the third direction D3. For example, the second pass transistors PT25 and PT26 may be formed in the second substrate SUB2 of the second semiconductor layer L2. For example, the extension region EXR may include step regions SZ1_F1, SZ1_F2, and SZ1_F3, and word line contacts WC15a, WC16a, WC25a, WC26a, WC35a, and WC36a may be formed in the step regions SZ1_F1, SZ1_F2, and SZ1_F3.

[0173] Although not shown in detail, in some example embodiments, the second pass transistors PT25 and PT26 may be formed in the first substrate SUB1 of the first semiconductor layer L1.

[0174] Although not shown in detail, in some example embodiments, when the channel has a quad-stack structure, a pass transistor connected to a word line formed to correspond to two lower sub-channel holes may be formed in the first substrate SUB1, and a pass transistor connected to a word line formed to correspond to two upper sub-channel holes may be formed in the second substrate SUB2.

[0175] Reference Fig. 14B , shows an example in which word lines in the same stack are divided into two groups and the through transistors connected to the word lines of the same group are formed in the same substrate. Fig.11 and Fig.14A Duplicate description.

[0176] as Fig.11 and Fig.12 For example, Fig. 14B An example is shown in which one of the odd word lines and the even word lines among the word lines in the same stack is set as the first word line group, the other of the odd word lines and the even word lines is set as the second word line group, and the word line contacts WC15b, WC16b, WC25b, WC26b, WC35b and WC36b are alternately arranged along the first direction D1.

[0177] For example, the first word lines WL15 and WL16 may include a first word line group WL15 and a second word line group WL16, the first pass transistors PT15 and PT16 may include a first pass transistor group PT15 and a second pass transistor group PT16, and the first word line contacts WC15b and WC16b may include a first word line contact group WC15b and a second word line contact group WC16b. The first pass transistor group PT15 connected to the first word line group WL15 through the first word line contact group WC15b may be formed in the first substrate SUB1 of the first semiconductor layer L1. The second pass transistor group PT16 connected to the second word line group WL16 through the second word line contact group WC16b may be formed in the second substrate SUB2 of the second semiconductor layer L2.

[0178] Similarly, each of the second word lines WL25 and WL26, the second pass transistors PT25 and PT26, and the second word line contacts WC25b and WC26b may be divided into two groups, and the second pass transistors PT25 and PT26 may be individually arranged in the first substrate SUB1 and the second substrate SUB2, respectively. Each of the third word lines WL35 and WL36, the third pass transistors PT35 and PT36, and the third word line contacts WC35b and WC36b may be divided into two groups, and the third pass transistors PT35 and PT36 may be individually arranged in the first substrate SUB1 and the second substrate SUB2, respectively. For example, the extension region EXR may include step regions SZ1_F1, SZ1_F2, and SZ1_F3, and word line contacts WC15b, WC16b, WC25b, WC26b, WC35b, and WC36b may be formed in the step regions SZ1_F1, SZ1_F2, and SZ1_F3.

[0179] Fig.15A , Fig. 15B , Fig. 15C , Fig.15D and Fig.15E is a diagram illustrating a nonvolatile memory device according to some example embodiments.

[0180] Reference Fig.15A , the nonvolatile memory device 12 includes a first semiconductor layer L1, a second semiconductor layer L2, and a third semiconductor layer L3.

[0181] In addition to the nonvolatile memory device 12 further including the third semiconductor layer L3 and the arrangement of the pass transistor PT being partially changed, Fig.15A The example can be compared with Figure 1 The examples are basically the same. Figure 1 Duplicate description.

[0182] The first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may be arranged or stacked in the third direction D3. The nonvolatile memory device 12 may have a multi-wafer stack (or bonded) structure in which three or more semiconductor layers are stacked and / or bonded.

[0183] Like the second semiconductor layer L2, the third semiconductor layer L3 may also include a peripheral circuit PC for controlling the memory cell array MCA, and thus the third semiconductor layer L3 may be referred to as a peripheral circuit region. For example, the peripheral circuit PC included in the second semiconductor layer L2 may be defined as a first peripheral circuit, and the peripheral circuit PC included in the third semiconductor layer L3 may be defined as a second peripheral circuit. For example, the first peripheral circuit and the second peripheral circuit may include a control circuit, a page buffer circuit, and the like.

[0184] Some (e.g., the first part) of the pass transistors PT may be formed in the second semiconductor layer L2, and other (e.g., the second part) of the pass transistors PT may be formed in the third semiconductor layer L3. In other words, the pass transistors PT may be separated and / or distributed in the second semiconductor layer L2 and the third semiconductor layer L3. Therefore, the area in which the pass transistors PT are placed within one semiconductor layer may be reduced, and the wiring complexity for connecting the pass transistors PT to the word lines WL may be reduced. Therefore, the circuit area may be reduced, the manufacturing cost may be reduced, and the nonvolatile memory device 12 may be manufactured efficiently.

[0185] Reference Fig. 15B , the first semiconductor layer L1 may include a first substrate SUB1, a first word line WLa and a second word line WLb, a channel CH, and a first insulating layer IL1. The second semiconductor layer L2 may include a second substrate SUB2, a second pass transistor PTb, and a second insulating layer IL2. The third semiconductor layer L3 may include a third substrate SUB3, a first pass transistor PTa, and a third insulating layer IL3.

[0186] In addition to the third semiconductor layer L3 being formed and the first pass transistor PTa being formed in the third substrate SUB3, Fig. 15B The example can be compared with Figure 2 The examples are basically the same. Figure 2 Duplicate description.

[0187] Reference Fig. 15C , shows an example in which the pass transistors connected to the word lines in the same stack are formed in the same substrate. In addition to the first pass transistors PT11 to PT14 formed in the third substrate SUB3 of the third semiconductor layer L3, Fig. 15C The example can be compared with Fig. 9 The examples are basically the same. Fig. 9 Duplicate description.

[0188] Reference Fig.15D and 15E , shows an example in which word lines in the same stack are divided into two groups and pass transistors connected to the word lines of the same group are formed in the same substrate. In addition to the first pass transistor group PT11 and PT13 and the third pass transistor group PT21 and PT23 formed in the third substrate SUB3 of the third semiconductor layer L3, Fig.15D The example can be compared with Fig.11 Except that the first pass transistor group PT11 and PT12 and the fourth pass transistor group PT23 and PT24 are formed in the third substrate SUB3 of the third semiconductor layer L3, Fig.15EThe example can be compared with Fig.12 The examples are basically the same. Fig.11 and Fig.12 Duplicate description.

[0189] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D is a diagram illustrating a nonvolatile memory device according to some example embodiments.

[0190] Reference Fig.16A , the nonvolatile memory device 14 may include a first semiconductor layer L1 , a second semiconductor layer L2 , and a third semiconductor layer L3 .

[0191] In addition to the fact that the nonvolatile memory device 14 further includes the third semiconductor layer L3 and the arrangement of the pass transistor PT may be partially changed, Fig.16A The example can be compared with Figure 1 The examples are basically the same. Fig.16A The third semiconductor layer L3 in Fig.15A The third semiconductor layer L3 in is substantially the same as that in FIG. Figure 1 and Fig.15A Duplicate description.

[0192] Some (e.g., a first portion) of the pass transistors PT may be formed in the first semiconductor layer L1, other (e.g., a second portion) of the pass transistors PT may be formed in the second semiconductor layer L2, and the remaining (e.g., a third portion) of the pass transistors PT may be formed in the third semiconductor layer L3. In other words, the pass transistors PT may be separated and / or distributed in the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3. Therefore, the area in which the pass transistors PT are placed within one semiconductor layer may be reduced, and the wiring complexity for connecting the pass transistors PT to the word lines WL may be reduced. Therefore, the circuit area may be reduced, the manufacturing cost may be reduced, and the nonvolatile memory device 12 may be manufactured more efficiently.

[0193] Reference Fig. 16B , the first semiconductor layer L1 may include a first substrate SUB1, first, second and third word lines WLa, WLb and WLc, a channel CH, a first pass transistor PTa and a first insulating layer IL1. The second semiconductor layer L2 may include a second substrate SUB2, a second pass transistor PTb and a second insulating layer IL2. The third semiconductor layer L3 may include a third substrate SUB3, a third pass transistor PTc and a third insulating layer IL3.

[0194] In addition to forming a third semiconductor layer L3 and a third pass transistor PTc, Fig. 16B The example can be compared with Figure 2 The examples are basically the same. Fig. 16B The third semiconductor layer L3 in Fig. 15B The third semiconductor layer L3 in FIG. 1 is substantially the same as that in FIG. 1 . Figure 2 and Fig. 15B Duplicate description.

[0195] The word lines WLa, WLb, and WLc may be stacked on the first substrate SUB1 in the third direction D3. The channel CH may penetrate the word lines WLa, WLb, and WLc and may extend in a direction perpendicular to the top surface of the first substrate SUB1. The third pass transistor PTc may be formed in the third substrate SUB3 and may be connected to the third word line WLc.

[0196] In some example embodiments, at least one of widths and lengths of the first pass transistor PTa, the second pass transistor PTb, and the third pass transistor PTc may be different from each other.

[0197] Reference Fig. 16C , shows an example in which the pass transistors connected to the word lines in the same stack are formed in the same substrate. In addition, the second pass transistors PT25 and PT26 can be formed in the third substrate SUB3 of the third semiconductor layer L3. Fig. 16C The example can be compared with Fig.14A For brevity, the examples are omitted here. Fig.14A Duplicate description.

[0198] Reference Fig.16D , shows an example in which word lines in the same stack are divided into three groups and the through transistors connected to the word lines of the same group are formed in the same substrate. Fig.11 and Fig.15D Duplicate description.

[0199] The first word lines WL17, WL18, and WL19 may include a first word line group WL17, a second word line group WL18, and a third word line group WL19, the first pass transistors PT17, PT18, and PT19 may include a first pass transistor group PT17, a second pass transistor group PT18, and a third pass transistor group PT19, and the first word line contacts WC17b, WC18b, and WC19b may include a first word line contact group WC17b, a second word line contact group WC18b, and a third word line contact group WC19b. The first pass transistor group PT17 connected to the first word line group WL17 through the first word line contact group WC17b may be formed in the first substrate SUB1. The second pass transistor group PT18 connected to the second word line group WL18 through the second word line contact group WC18b may be formed in the second substrate SUB2. A third pass transistor group PT19 connected to the third word line group WL19 through a third word line contact group WC19 b ​​may be formed in the third substrate SUB3 .

[0200] Similarly, each of the second word lines WL27, WL28, and WL29, the second pass transistors PT27, PT28, and PT29, and the second word line contacts WC27b, WC28b, and WC29b may be divided into three groups, and the second pass transistors PT27, PT28, and PT29 may be individually arranged in the first substrate SUB1, the second substrate SUB2, and the third substrate SUB3, respectively. The word line contacts WC17b, WC18b, WC19b, WC27b, WC28b, and WC29b may be formed in the step regions SZ1_F1 and SZ1_F2.

[0201] Although the example embodiments are described based on a specific number of semiconductor layers, a specific number of sub-channel holes, a specific number of word lines, and a specific number of pass transistors, the present disclosure is not limited thereto. For example, the nonvolatile memory device according to the example embodiments may include any number of semiconductor layers, any number of sub-channel holes, any number of word lines, and / or any number of pass transistors.

[0202] Fig.17A and Fig. 17B is a cross-sectional view of a memory package according to some example embodiments.

[0203] Reference Fig.17A , the memory package 700 may include a base substrate 710 and a plurality of memory chips CHP1 , CHP2 , and CHP3 stacked on the base substrate 710 .

[0204] Each of the memory chips CHP1 to CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may further include a plurality of I / O pads IOPAD. The memory cell layer CLY and the peripheral circuit layer PLY may correspond to reference numerals, respectively. Figure 1 The first semiconductor layer L1 and the second semiconductor layer L2 described herein may further include the elements described herein respectively included in the first semiconductor layer L1 and the second semiconductor layer L2 according to any example embodiment described herein. Each of the memory chips CHP1 to CHP3 may include a nonvolatile memory device according to example embodiments.

[0205] In some example embodiments, the memory chips CHP1 to CHP3 may be stacked on the base substrate 710 so that the surface on which a plurality of I / O pads IOPAD are formed faces upward. In some example embodiments, relative to each of the memory chips CHP1 to CHP3, a plurality of I / O pads IOPAD may be arranged near one side of the semiconductor substrate. In this way, the memory chips CHP1 to CHP3 may be stacked in proportion (i.e., stacked in a step shape) so that a plurality of I / O pads IOPAD of each memory chip may be exposed. In this stacked state, the memory chips CHP1 to CHP3 may be electrically connected to the base substrate 710 by a plurality of bonding wires BW.

[0206] The stacked memory chips CHP1 to CHP3 and a plurality of bonding wires BW may be fixed by a sealing member 740, and an adhesive member 730 may be interposed between the base substrate 710 and the memory chips CHP1 to CHP3. Conductive bumps 720 may be formed on the bottom surface of the base substrate 710 for electrical connection with an external device.

[0207] Reference Fig. 17B , the memory package 800 may include a base substrate 810 and a plurality of memory chips CHP1 to CHP3 stacked on the base substrate 810. Fig.17A Duplicate description.

[0208] Each of the memory chips CHP1 to CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may further include a plurality of through silicon vias (TSVs, or referred to as “through silicon vias”) 830 .

[0209] In some example embodiments, with respect to each of the memory chips CHP1 to CHP3, a plurality of TSVs 830 may be arranged at the same position in each memory chip. In this way, the memory chips CHP1 to CHP3 may be stacked so that the plurality of TSVs 830 of each memory chip may be completely stacked (e.g., the arrangement of the plurality of TSVs 830 may be perfectly matched in the memory chips CHP1 to CHP3). In this stacked state, the memory chips CHP1 to CHP3 may be electrically connected to each other and to the base substrate 810 through the plurality of TSVs 830 and the conductive material 840.

[0210] The conductive bump 820 and the sealing member 850 may be Fig.17A The conductive bumps 720 and the sealing member 740 in FIG. 7 are substantially the same.

[0211] Fig.18 is a block diagram illustrating an electronic system including a nonvolatile memory device according to some example embodiments.

[0212] Reference Fig.18 , the electronic system 3000 may include a semiconductor device 3100 and a controller 3200 electrically connected to the semiconductor device 3100. The electronic system 3000 may be a storage device including one or more semiconductor devices 3100 or an electronic device including the storage device. For example, the electronic system 3000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or more semiconductor devices 3100.

[0213] The semiconductor device 3100 may be a nonvolatile memory device, for example, according to Figures 1 to 16D A nonvolatile memory device of an example embodiment is described. The semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110, a page buffer circuit 3120, and a logic circuit 3130. The second structure 3100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0214] In the second structure 3100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary according to various examples of embodiments.

[0215] In the first structure 3100F, the decoder circuit 3110, the page buffer circuit 3120 and the logic circuit 3130 may correspond to Figure 3 The address decoder 520, the page buffer circuit 530 and the control circuit 560 in.

[0216] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 3110 through the first connection wiring 3115 extending from the first structure 3100F to the second structure 3110S. The bit line BL may be electrically connected to the page buffer circuit 3120 through the second connection wiring 3125 extending from the first structure 3100F to the second structure 3100S. The I / O pad 3101 may be electrically connected to the logic circuit 3130 through the I / O connection wiring 3135 extending from the first structure 3100F to the second structure 3100S.

[0217] The controller 3200 may include a processor 3210 , a NAND controller 3220 , and a host interface 3230 . In some example embodiments, the electronic system 3000 may include a plurality of semiconductor devices 3100 , and in this case, the controller 3200 may control the plurality of semiconductor devices 3100 .

[0218] The processor 3210 may control the operation of the electronic system 3000 including the controller 3200. The processor 3210 may be operated by firmware, and may control the NAND controller 3220 to access the semiconductor device 3100. The NAND controller 3220 may include a NAND interface 3221 for communicating with the semiconductor device 3100. Through the NAND interface 3221, a control command for controlling the semiconductor device 3100, data to be written into the memory cell transistor MCT of the semiconductor device 3100, data to be read from the memory cell transistor MCT of the semiconductor device 3100, etc. may be transmitted. The host interface 3230 may provide communication between the electronic system 3000 and an external host. When a control command is received from the external host through the host interface 3230, the processor 3210 may control the semiconductor device 3100 in response to the control command.

[0219] Fig.19 is a cross-sectional view of a memory device according to some example embodiments.

[0220] Reference Fig.19 , the memory device (or non-volatile memory device) 5000 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PREG may be manufactured separately, and then the lower chip and the at least one upper chip may be connected to each other by a bonding method to realize a C2C structure. For example, the bonding method may represent or may include a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0221] The memory device 5000 may include at least one upper chip including a cell region. Fig.19 As shown in , the memory device 5000 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 5000 includes two upper chips, a first upper chip including a first cell region CREG1, a second upper chip including a second cell region CREG2, and a lower chip including a peripheral circuit region PREG may be manufactured separately, and then the memory device 5000 may be manufactured by connecting the first upper chip, the second upper chip, and the lower chip to each other by one or more bonding methods. The first upper chip may be flipped and then connected to the lower chip by a bonding method, and the second upper chip may be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip will be defined based on before flipping each of the first upper chip and the second upper chip or before realizing the C2C structure. In other words, in Fig.19 In the embodiment, the upper portion of the lower chip may refer to an upper portion defined based on the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may refer to an upper portion defined based on the -Z axis direction. However, the present disclosure is not limited thereto. In some example embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0222] Each of the peripheral circuit region PREG and the first and second cell regions CREG1 and CREG2 of the memory device 5000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0223] The peripheral circuit region PREG may include a first substrate 5210 and a plurality of circuit elements 5220a, 5220b, and 5220c formed on the first substrate 5210. An interlayer insulating layer 5215 including one or more insulating layers may be provided on the plurality of circuit elements 5220a, 5220b, and 5220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 5220a, 5220b, and 5220c may be provided in the interlayer insulating layer 5215. For example, the plurality of metal lines may include first metal lines 5230a, 5230b, and 5230c connected to the plurality of circuit elements 5220a, 5220b, and 5220c and second metal lines 5240a, 5240b, and 5240c formed on the first metal lines 5230a, 5230b, and 5230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 5230a, 5230b, and 5230c may be formed of tungsten having a relatively high resistivity, and the second metal lines 5240a, 5240b, and 5240c may be formed of copper having a relatively low resistivity. The present disclosure is not limited thereto.

[0224] In the example embodiments, the first metal lines 5230a, 5230b, and 5230c and the second metal lines 5240a, 5240b, and 5240c are shown and described. However, the example embodiments are not limited thereto. In some example embodiments, at least one or more additional metal lines may be further formed on the second metal lines 5240a, 5240b, and 5240c. In this case, the second metal lines 5240a, 5240b, and 5240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 5240a, 5240b, and 5240c may be formed of copper having a resistivity lower than the resistivity of aluminum of the second metal lines 5240a, 5240b, and 5240c.

[0225] The interlayer insulating layer 5215 may be on the first substrate 5210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0226] Each of the first cell region CREG1 and the second cell region CREG2 may include at least one memory block. The first cell region CREG1 may include a second substrate 5310 and a common source line 5320. A plurality of word lines 5330 (e.g., word lines 5331 to 5338) may be stacked on the second substrate 5310 in a direction perpendicular to the top surface of the second substrate 5310 (i.e., the Z-axis direction). The string selection line and the ground selection line may be above and below the word line 5330, and the plurality of word lines 5330 may be between the string selection line and the ground selection line. Similarly, the second cell region CREG2 may include a third substrate 5410 and a common source line 5420, and a plurality of word lines 5430 (e.g., word lines 5431 to 5438) may be stacked on the third substrate 5410 in a direction perpendicular to the top surface of the third substrate 5410 (i.e., the Z-axis direction). Each of the second substrate 5310 and the third substrate 5410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CREG1 and the second cell region CREG2.

[0227] In some example embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 5310 to penetrate or extend through the word line 5330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 5350c and the second metal line 5360c in the bit line bonding region BLBA. For example, the second metal line 5360c may be a bit line and may be connected to the channel structure CH through the first metal line 5350c. The bit line 5360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 5310.

[0228] In some example embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 5310 to penetrate or extend through the common source line 5320 and the lower word lines 5331 and 5332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate or extend through the upper word lines 5333 to 5338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 5350c and the second metal line 5360c. As the length of the channel increases, it may be difficult to form a channel having a substantially uniform width due to the characteristics of the manufacturing process. Due to the lower channel LCH and the upper channel UCH that may be formed through processes that are sequentially performed, the memory device 5000 according to some example embodiments may include a channel having improved width uniformity.

[0229] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in area "A2", a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 5332 and 5333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The level of the voltage applied to the dummy word line may be different from the level of the voltage applied to the general word line, and thus the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device can be reduced.

[0230] In some example embodiments, in region "A2", the number of lower word lines 5331 and 5332 penetrated by the lower channel LCH may be less than the number of upper word lines 5333 to 5338 penetrated by the upper channel UCH. However, example embodiments are not limited thereto. In some example embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH in the second cell region CREG2 may be substantially the same as the structural features and connection relationships of the channel structure CH in the first cell region CREG1, and for the sake of brevity, their repeated description is omitted herein.

[0231] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell region CREG1, and the second through electrode THV2 may be disposed in the second cell region CREG2. Fig.19 As shown in , the first through electrode THV1 may penetrate or extend through the common source line 5320 and the plurality of word lines 5330. In some example embodiments, the first through electrode THV1 may also penetrate the second substrate 5310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as those of the first through electrode THV1.

[0232] In some example embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 5372d and the second through metal pattern 5472d. The first through metal pattern 5372d may be formed at the bottom end of the first upper chip including the first unit region CREG1, and the second through metal pattern 5472d may be formed at the top end of the second upper chip including the second unit region CREG2. The first through electrode THV1 may be electrically connected to the first metal line 5350c and the second metal line 5360c. The lower via 5371d may be formed between the first through electrode THV1 and the first through metal pattern 5372d, and the upper via 5471d may be formed between the second through electrode THV2 and the second through metal pattern 5472d. The first through metal pattern 5372d and the second through metal pattern 5472d may be connected to each other by a bonding method.

[0233] In addition, in the bit line bonding area BLBA, an upper metal pattern 5252 may be formed in the uppermost metal layer of the peripheral circuit area PREG, and an upper metal pattern 5392 having the same shape as that of the upper metal pattern 5252 may be formed in the uppermost metal layer of the first cell area CREG1. The upper metal pattern 5392 of the first cell area CREG1 and the upper metal pattern 5252 of the peripheral circuit area PREG may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 5360c may be electrically connected to a page buffer included in the peripheral circuit area PREG. For example, some of the circuit elements 5220c of the peripheral circuit area PREG may constitute a page buffer, and the bit line 5360c may be electrically connected to the circuit elements 5220c constituting the page buffer through the upper bonding metal pattern 5370c of the first cell area CREG1 and the upper bonding metal pattern 5270c of the peripheral circuit area PREG.

[0234] Still refer to Fig.19, in the word line bonding area WLBA, the word line 5330 of the first cell region CREG1 may extend in a second direction (e.g., an X-axis direction) parallel to the top surface of the second substrate 5310, and may be connected to a plurality of cell contact plugs 5340 (e.g., cell contact plugs 5341 to 5347). The first metal line 5350b and the second metal line 5360b may be sequentially connected to the cell contact plugs 5340 connected to the word line 5330. In the word line bonding area WLBA, the cell contact plugs 5340 may be connected to the peripheral circuit region PREG through the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG.

[0235] The cell contact plug 5340 may be electrically connected to a row decoder included in the peripheral circuit region PREG. For example, some of the circuit elements 5220b of the peripheral circuit region PREG may constitute a row decoder, and the cell contact plug 5340 may be electrically connected to the circuit element 5220b constituting the row decoder through the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG. In some example embodiments, the operating voltage of the circuit element 5220b constituting the row decoder may be different from the operating voltage of the circuit element 5220c constituting the page buffer. For example, the operating voltage of the circuit element 5220c constituting the page buffer may be greater than the operating voltage of the circuit element 5220b constituting the row decoder.

[0236] Likewise, in the word line bonding area WLBA, the word lines 5430 of the second cell region CREG2 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the third substrate 5410, and may be connected to a plurality of cell contact plugs 5440 (e.g., cell contact plugs 5441 to 5447). The cell contact plugs 5440 may be connected to the peripheral circuit region PREG through the upper metal pattern of the second cell region CREG2 and the lower metal pattern, the upper metal pattern, and the cell contact plugs 5348 of the first cell region CREG1.

[0237] In the word line bonding area WLBA, the upper bonding metal pattern 5370b may be formed in the first cell region CREG1, and the upper bonding metal pattern 5270b may be formed in the peripheral circuit region PREG. The upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG may be electrically connected to each other by a bonding method. As a non-limiting example, the upper bonding metal pattern 5370b and the upper bonding metal pattern 5270b may be formed of aluminum, copper, or tungsten.

[0238] In the external pad bonding area PA, the lower metal pattern 5371e may be formed in the lower portion of the first unit region CREG1, and the upper metal pattern 5472a may be formed in the upper portion of the second unit region CREG2. The lower metal pattern 5371e of the first unit region CREG1 and the upper metal pattern 5472a of the second unit region CREG2 may be connected to each other in the external pad bonding area PA by a bonding method. Similarly, the upper metal pattern 5372a may be formed in the upper portion of the first unit region CREG1, and the upper metal pattern 5272a may be formed in the upper portion of the peripheral circuit region PREG. The upper metal pattern 5372a of the first unit region CREG1 and the upper metal pattern 5272a of the peripheral circuit region PREG may be connected to each other by a bonding method.

[0239] The common source line contact plugs 5380 and 5480 may be in the external pad bonding area PA. The common source line contact plugs 5380 and 5480 may be formed of a conductive material such as a metal, a metal compound, and / or doped polysilicon. The common source line contact plug 5380 of the first cell region CREG1 may be electrically connected to the common source line 5320, and the common source line contact plug 5480 of the second cell region CREG2 may be electrically connected to the common source line 5420. The first metal line 5350a and the second metal line 5360a may be sequentially stacked on the common source line contact plug 5380 of the first cell region CREG1, and the first metal line 5450a and the second metal line 5460a may be sequentially stacked on the common source line contact plug 5480 of the second cell region CREG2.

[0240] The input / output pads 5205, 5405, and 5406 may be in the external pad bonding area PA. Fig.19 , a lower insulating layer 5201 may cover the bottom surface of the first substrate 5210, and a first input / output pad 5205 may be formed on the lower insulating layer 5201. The first input / output pad 5205 may be connected to at least one of the plurality of circuit elements 5220a in the peripheral circuit region PREG through the first input / output contact plug 5203, and may be separated from the first substrate 5210 by the lower insulating layer 5201. In addition, a side insulating layer may be located between the first input / output contact plug 5203 and the first substrate 5210 to electrically isolate the first input / output contact plug 5203 from the first substrate 5210.

[0241] An upper insulating layer 5401 covering the top surface of the third substrate 5410 may be formed on the third substrate 5410. A second input / output pad 5405 and / or a third input / output pad 5406 may be on the upper insulating layer 5401. The second input / output pad 5405 may be connected to at least one of the plurality of circuit elements 5220a in the peripheral circuit region PREG through second input / output contact plugs 5403 and 5303, and the third input / output pad 5406 may be connected to at least one of the plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through third input / output contact plugs 5404 and 5304.

[0242] In some example embodiments, the third substrate 5410 may not be disposed in a region in which the input / output contact plugs are arranged. For example, as shown in region "B", the third input / output contact plug 5404 may be separated from the third substrate 5410 in a direction parallel to the top surface of the third substrate 5410, and may penetrate or extend through the interlayer insulating layer 5415 of the second cell region CREG2 to be connected to the third input / output pad 5406. In this case, the third input / output contact plug 5404 may be formed by at least one of various processes.

[0243] In some example embodiments, as shown in region “B1”, the third input / output contact plug 5404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 5404 may gradually increase toward the upper insulating layer 5401. In other words, the diameter of the channel structure CH described in region “A1” may gradually decrease toward the upper insulating layer 5401, but the diameter of the third input / output contact plug 5404 may gradually increase toward the upper insulating layer 5401. For example, the third input / output contact plug 5404 may be formed after the second cell region CREG2 is bonded to the first cell region CREG1 by a bonding method.

[0244] In some example embodiments, as shown in region 'B2', the third input / output contact plug 5404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 5404 may gradually decrease toward the upper insulating layer 5401. In other words, similar to the channel structure CH, the diameter of the third input / output contact plug 5404 may gradually decrease toward the upper insulating layer 5401. For example, the third input / output contact plug 5404 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0245] In some example embodiments, the input / output contact plug may overlap the third substrate 5410. For example, as shown in region "C", the second input / output contact plug 5403 may penetrate or extend through the interlayer insulating layer 5415 of the second cell region CREG2 in a third direction (e.g., Z-axis direction), and may be electrically connected to the second input / output pad 5405 through the third substrate 5410. In this case, the connection structure of the second input / output contact plug 5403 and the second input / output pad 5405 may be implemented by various methods.

[0246] In some example embodiments, as shown in region “C1”, the opening 5408 may be formed to penetrate or extend through the third substrate 5410, and the second input / output contact plug 5403 may be directly connected to the second input / output pad 5405 through the opening 5408 formed in the third substrate 5410. In this case, as shown in region “C1”, the diameter of the second input / output contact plug 5403 may gradually increase toward the second input / output pad 5405. However, example embodiments are not limited thereto, and in some example embodiments, the diameter of the second input / output contact plug 5403 may gradually decrease toward the second input / output pad 5405.

[0247] In some example embodiments, as shown in region “C2”, an opening 5408 penetrating or extending through the third substrate 5410 may be formed, and a contact 5407 may be formed in the opening 5408. One end of the contact 5407 may be connected to the second input / output pad 5405, and the other end of the contact 5407 may be connected to the second input / output contact plug 5403. Therefore, the second input / output contact plug 5403 may be electrically connected to the second input / output pad 5405 through the contact 5407 in the opening 5408. In this case, as shown in region “C2”, the diameter of the contact 5407 may gradually increase toward the second input / output pad 5405, and the diameter of the second input / output contact plug 5403 may gradually decrease toward the second input / output pad 5405. For example, the second input / output contact plug 5403 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other, and the contact 5407 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0248] In some example embodiments shown in region "C3", compared to the embodiment of region "C2", a stopper 5409 may be further formed on the bottom end of the opening 5408 of the third substrate 5410. The stopper 5409 may be a metal line formed in the same layer as the common source line 5420. Alternatively, the stopper 5409 may be a metal line formed in the same layer as at least one of the word lines 5430. The second input / output contact plug 5403 may be electrically connected to the second input / output pad 5405 through the contact 5407 and the stopper 5409.

[0249] Similar to the second input / output contact plug 5403 and the third input / output contact plug 5404 of the second unit region CREG2, the diameter of each of the second input / output contact plug 5303 and the third input / output contact plug 5304 of the first unit region CREG1 can gradually decrease toward the lower metal pattern 5371e, or can gradually increase toward the lower metal pattern 5371e.

[0250] In some example embodiments, the slit 5411 may be formed in the third substrate 5410. For example, the slit 5411 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", the slit 5411 may be located between the second input / output pad 5405 and the cell contact plug 5440 when viewed in a plan view. In some example embodiments, the second input / output pad 5405 may be located between the slit 5411 and the cell contact plug 5440 when viewed in a plan view.

[0251] In some example embodiments, as shown in region "D1", the slit 5411 may be formed to penetrate or extend through the third substrate 5410. For example, the slit 5411 may be used to prevent the third substrate 5410 from being finely broken when forming the opening 5408. However, the present disclosure is not limited thereto, and in some example embodiments, the slit 5411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 5410.

[0252] In some example embodiments, as shown in region "D2", a conductive material 5412 may be formed in the slit 5411. For example, the conductive material 5412 may be used to discharge leakage current that may occur when driving circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 5412 may be connected to an external ground line.

[0253] In some example embodiments, as shown in region 'D3', an insulating material 5413 may be formed in the slit 5411. For example, the insulating material 5413 may be used to electrically isolate the second input / output pad 5405 and the second input / output contact plug 5403 arranged in the external pad bonding area PA from the word line bonding area WLBA. Since the insulating material 5413 is formed in the slit 5411, it is possible to prevent a voltage provided through the second input / output pad 5405 from affecting a metal layer located on the third substrate 5410 in the word line bonding area WLBA.

[0254] In some example embodiments, the first to third input / output pads 5205, 5405, and 5406 may be selectively formed. For example, the memory device 5000 may be implemented to include only the first input / output pad 5205 on the first substrate 5210, only the second input / output pad 5405 on the third substrate 5410, or only the third input / output pad 5406 on the upper insulating layer 5401.

[0255] In some example embodiments, at least one of the second substrate 5310 of the first unit region CREG1 and the third substrate 5410 of the second unit region CREG2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 5310 of the first unit region CREG1 may be removed before or after the bonding process of the peripheral circuit region PREG and the first unit region CREG1, and then an insulating layer covering the top surface of the common source line 5320 or a conductive layer for connection may be formed. Similarly, the third substrate 5410 of the second unit region CREG2 may be removed before or after the bonding process of the first unit region CREG1 and the second unit region CREG2, and then an upper insulating layer 5401 covering the top surface of the common source line 5420 or a conductive layer for connection may be formed.

[0256] Fig. 20 is a diagram illustrating a manufacturing process of a memory device according to some example embodiments.

[0257] Reference Fig. 20 , corresponding integrated circuits may be formed on the first wafer WF1 and the second wafer WF2. A memory cell array may be formed in the first wafer WF1, and a peripheral circuit may be formed in the second wafer WF2.

[0258] After various integrated circuits have been formed on the first wafer WF1 and the second wafer WF2, respectively, the first wafer WF1 and the second wafer WF2 may be bonded together. The bonded wafers WF1 and WF2 may then be cut (or divided) into separate chips, wherein each chip corresponds to a semiconductor device such as a memory device 6000 including a first semiconductor die SD1 and a second semiconductor die SD2 stacked vertically (e.g., the first semiconductor die SD1 is stacked on the second semiconductor die SD2, etc.). Each cut portion of the first wafer WF1 may correspond to the first semiconductor die SD1, and each cut portion of the second wafer WF2 may correspond to the second semiconductor die SD2. For example, the memory device 6000 may be formed based on the first wafer WF1. Fig. 20 Manufacturing process to manufacture Fig.19 Memory device 5000.

[0259] Example embodiments may be applied to various electronic devices and systems including non-volatile memory devices and memory packages. For example, example embodiments may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0260] The foregoing is an illustration of example embodiments and is not to be construed as limiting the example embodiments. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the example embodiments without materially departing from the teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and is not to be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments and other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A non-volatile memory device, comprising: A first semiconductor layer, comprising a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction, the first semiconductor layer further comprising: a first substrate; and a memory cell array located on the first substrate and connected to the plurality of word lines and the plurality of bit lines; A second semiconductor layer arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, the second semiconductor layer comprising: a second substrate; and a peripheral circuit located on the second substrate and configured to control the memory cell array; and a plurality of pass transistors connected to the plurality of word lines and configured to control electrical connection between the memory cell array and a peripheral circuit, A first portion of the plurality of pass transistors is located in the first semiconductor layer, and a second portion of the plurality of pass transistors is located in the second semiconductor layer.

2. The nonvolatile memory device according to claim 1, in, The plurality of word lines include: a first word line stacked on the first substrate in a third direction; and a second word line stacked on the first word line in the third direction. The plurality of pass transistors include: a first pass transistor connected to a first word line; and a second pass transistor connected to a second word line. The first pass transistor is located in a first substrate of the first semiconductor layer, and the second pass transistor is located in a second substrate of the second semiconductor layer.

3. The nonvolatile memory device according to claim 2, in, The memory cell array comprises: a core region including a plurality of memory cells; and an extension region adjacent to a first side of the core region and comprising a plurality of word line contacts for electrical connection between the plurality of word lines and the plurality of pass transistors, The plurality of word line contacts include: a first word line contact configured to electrically connect the first word line with the first pass transistor; and a second word line contact configured to electrically connect the second word line with the second pass transistor.

4. The nonvolatile memory device according to claim 3, wherein: The first word line contact and the second word line contact are aligned with each other in the third direction.

5. The nonvolatile memory device according to claim 3, in, The extension region further includes: a plurality of step regions having a step shape in a cross-sectional view relative to the plurality of word lines; and at least one flat region having a flat shape in a cross-sectional view relative to the plurality of word lines. Wherein, the plurality of word line contacts are located in the plurality of step regions.

6. The nonvolatile memory device according to claim 2, further comprising: a plurality of drivers configured to control switching operations of the plurality of pass transistors, The plurality of drivers include: a first driver configured to control a switching operation of a first pass transistor; and a second driver configured to control a switching operation of a second pass transistor. The first driver is located in a first substrate of the first semiconductor layer adjacent to the first pass transistor, and the second driver is located in a second substrate of the second semiconductor layer adjacent to the second pass transistor.

7. The nonvolatile memory device according to claim 2, in, The memory cell array includes: a plurality of channel holes extending through the plurality of word lines in a third direction to form a plurality of memory cells, Each of the plurality of channel holes comprises: a first sub-channel hole and a second sub-channel hole, which are sequentially stacked on the first substrate in the third direction, Among them, the first word line corresponds to the first sub-channel hole, and the second word line corresponds to the second sub-channel hole.

8. The nonvolatile memory device according to claim 1, in, The plurality of word lines include: a first word line stacked on the first substrate in a third direction; and a second word line stacked on the first word line in the third direction. The first word line is divided into a first word line group and a second word line group. The plurality of pass transistors include: a first pass transistor group connected to a first word line group; and a second pass transistor group connected to a second word line group. The first pass transistor group is located in a first substrate of the first semiconductor layer, and the second pass transistor group is located in a second substrate of the second semiconductor layer.

9. The nonvolatile memory device according to claim 8, wherein: Among the first word lines, one of the odd word lines and the even word lines is set as a first word line group, and the other of the odd word lines and the even word lines is set as a second word line group.

10. The nonvolatile memory device according to claim 8, wherein: Among the first word lines, K first-first word lines stacked sequentially in the third direction are set as a first word line group, and K first-second word lines adjacent to the K first-first word lines and stacked sequentially in the third direction are set as a second word line group, where K is a positive integer greater than or equal to 2.

11. The nonvolatile memory device according to claim 8, in, The second word line is divided into a third word line group and a fourth word line group, The plurality of pass transistors further include: a third pass transistor group connected to a third word line group; and a fourth pass transistor group connected to a fourth word line group. The third pass transistor group is located in the first substrate of the first semiconductor layer, and the fourth pass transistor group is located in the second substrate of the second semiconductor layer.

12. The nonvolatile memory device according to claim 11, in, In the first substrate, the first pass transistor group and the third pass transistor group are alternately arranged along a first direction, Wherein, in the second substrate, the second pass transistor group and the fourth pass transistor group are alternately arranged along the first direction.

13. The nonvolatile memory device according to claim 11, in, The memory cell array comprises: a core region including a plurality of memory cells; and an extension region adjacent to a first side of the core region and comprising a plurality of word line contacts for electrical connection between the plurality of word lines and the plurality of pass transistors, Among them, the multiple word line contacts include: a first word line contact group, which is constructed to electrically connect the first word line group with the first pass transistor group; a second word line contact group, which is constructed to electrically connect the second word line group with the second pass transistor group; a third word line contact group, which is constructed to electrically connect the third word line group with the third pass transistor group; and a fourth word line contact group, which is constructed to electrically connect the fourth word line group with the fourth pass transistor group.

14. The nonvolatile memory device according to claim 13, wherein: The first word line contact group, the second word line contact group, the third word line contact group, and the fourth word line contact group are alternately arranged along the first direction.

15. The non-volatile memory device according to claim 13, in, The extended area also includes: a first step region having a step shape in a cross-sectional view relative to the first word line; and The second step region has a step shape in a cross-sectional view relative to the second word line, The first word line contact group and the second word line contact group are located in the first step region, and the third word line contact group and the fourth word line contact group are located in the second step region.

16. The non-volatile memory device according to claim 15, in, at least one first flat region having a flat shape in a cross-sectional view with respect to the first word line is omitted between the first step regions, At least one second flat region having a flat shape in a cross-sectional view relative to the second word line is omitted between the second step regions.

17. The nonvolatile memory device according to claim 1, wherein: A first portion of the plurality of pass transistors located in the first semiconductor layer and a second portion of the plurality of pass transistors located in the second semiconductor layer have different widths and / or different lengths.

18. The nonvolatile memory device according to claim 1, further comprising: A third semiconductor layer is disposed in a third direction relative to the first semiconductor layer, the third semiconductor layer comprising: a third substrate; and a second peripheral circuit located on the third substrate and configured to control the memory cell array, A third portion of the pass transistors among the plurality of pass transistors are located in the third semiconductor layer.

19. A non-volatile memory device, the non-volatile memory device comprising: A first semiconductor layer, comprising a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction, the first semiconductor layer further comprising: a first substrate; and a memory cell array located on the first substrate and connected to the plurality of word lines and the plurality of bit lines; A second semiconductor layer arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, the second semiconductor layer comprising: a second substrate; and a first peripheral circuit located on the second substrate and configured to control the memory cell array; A third semiconductor layer arranged in a third direction relative to the first semiconductor layer, the third semiconductor layer comprising: a third substrate; and a second peripheral circuit located on the third substrate and configured to control the memory cell array; and a plurality of pass transistors connected to the plurality of word lines and configured to control electrical connection between the memory cell array and the first peripheral circuit and the second peripheral circuit, A first portion of the plurality of pass transistors is located in the second semiconductor layer, and a second portion of the plurality of pass transistors is located in the third semiconductor layer.

20. A non-volatile memory device, the non-volatile memory device comprising: A first semiconductor layer, comprising a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction, the first semiconductor layer further comprising: a first substrate; and a memory cell array located on the first substrate and connected to the plurality of word lines and the plurality of bit lines; A second semiconductor layer arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, the second semiconductor layer comprising: a second substrate; and a peripheral circuit located on the second substrate and configured to control the memory cell array; a plurality of pass transistors connected to the plurality of word lines and configured to control electrical connection between the memory cell array and a peripheral circuit; and a plurality of drivers configured to control switching operations of the plurality of pass transistors, The memory cell array comprises: a core region including a plurality of memory cells; and an extension region adjacent to a first side of the core region and comprising a plurality of word line contacts for electrical connection between the plurality of word lines and the plurality of pass transistors. The plurality of word lines include a first word line and a second word line, wherein the plurality of pass transistors include a first pass transistor connected to a first word line and a second pass transistor connected to a second word line, The plurality of drivers include a first driver and a second driver, the first driver being configured to control a switching operation of a first pass transistor, and the second driver being configured to control a switching operation of a second pass transistor, The plurality of word line contacts include a first word line contact and a second word line contact, the first word line contact is configured to electrically connect the first word line to the first pass transistor, and the second word line contact is configured to electrically connect the second word line to the second pass transistor, wherein the first pass transistor and the first driver are located in a first substrate of the first semiconductor layer, and the second pass transistor and the second driver are located in a second substrate of the second semiconductor layer, The first word line contact and the second word line contact are located in an extension region of the first semiconductor layer.

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