Control method of power converter

Abstract

The purpose of the present invention is to reduce harmonics in a power converter. One or both of a duty ratio for turning on a switch for intermittently applying a first voltage boosted from a supercharger to a DC link and the first voltage is / are controlled. When the AC power output by the inverter is equal to or greater than a second threshold value smaller than the first threshold value, the equivalent DC voltage is controlled so as to be higher than the peak value of the rectified voltage rectified by the converter and equal to or less than the first voltage. The equivalent DC voltage when the AC power takes a first value greater than the first threshold value is higher than the equivalent DC voltage when the AC power takes a second value greater than the second threshold value and less than the first threshold value.

Description

Technical Field

[0001] The present disclosure relates to power conversion. Background Art

[0002] For example, in S12-7 of the 2013 National Conference of the Institute of Electrical Engineers (Yoshioka, Inoue, and Sasaki, "The Latest Trends in EMC Standards for Power Converters": hereinafter referred to as "Non-Patent Document 1"), it was shown that requirements regarding EMI (electromagnetic interference) will be required in the frequency band of switching operations in power converters in the future.

[0003] Non-patent document 1 describes the research status related to the standards for high-order harmonics in low-voltage systems and the standards for conduction interference in low-voltage systems. The former standard is planned to specify the measurement method and limit values ​​as IEC 61000-3-10 with the target frequency set to 2kHz to 9kHz, and the latter standard is planned to specify the measurement method and limit values ​​as IEC-61000-6-3 with the target frequency set to 9kHz to 150kHz. In these standards, a specified virtual power supply network (LISN: Line Impedance Stabilization Network) is used to evaluate the respective voltage effective values ​​and voltage positive peak values.

[0004] At present, the mainstream of the rectifier circuit of the power conversion device is the voltage type. In the voltage type rectifier circuit, the commercial voltage is switched through the reactor to obtain the DC voltage to improve the power factor. In this method, it is expected to reduce the ripple current so that the value obtained by converting the ripple current flowing through the rectifier circuit into a voltage value through the above-mentioned virtual power network does not deviate from the above-mentioned standard.

[0005] Power converters for air conditioners are required to achieve both improved efficiency and wider operating range when the load of the air conditioner is so-called partial load. In order to meet this requirement, a technology for using a rectification operation and a switching operation in the operation of the power converter has been proposed.

[0006] Japanese Patent Publication No. 6478881 (hereinafter referred to as "Patent Document 1") discloses a technology for selectively implementing synchronous rectification, partial switching, and high-speed switching. Synchronous rectification is used in the intermediate operating region with a small load, partial switching is used in the rated operating region with a larger load than the intermediate operating region, and high-speed switching is used in the operating region with a larger load.

[0007] A single-phase three-phase power converter with an active buffer is also proposed, which connects a capacitor and a switching element (hereinafter, from the perspective of controlling whether discharge occurs from the capacitor to the inverter, the switching element is also referred to as a "discharge switch") in series and is arranged in parallel between the converter and the inverter.

[0008] For example, Japanese Patent Publication No. 5804167 discloses the following technology: in a single-phase three-phase power converter with an active buffer, the voltage output from the converter (hereinafter also referred to as "converter output voltage") is boosted to charge the capacitor. Japanese Patent Publication No. 5804167 discloses the following technology: in a single-phase three-phase power converter with an active buffer, the power output from the converter is divided into power supplied to the active buffer and power supplied to the inverter, and the power supplied to the active buffer is smaller than the power supplied to the inverter.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent No. 6478881 Summary of the invention

[0012] Problems to be solved by the invention

[0013] In order to obtain the effect based on synchronous rectification in the Japanese Patent Publication No. 6478881, a reactor with an inductance of several mH is required. From the perspective of reducing costs, a reactor with such an inductance uses a silicon steel plate. The iron loss of the silicon steel plate is large, so it is preferred that the frequency based on which the partial switch or high-speed switch operates is low. On the other hand, from the perspective of reducing the noise of the reactor, it is preferred that the frequency is higher than the audible range. As a result, the frequency is only reduced to about 16kHz, which is the upper limit of the audible range.

[0014] From the perspective of complying with the standards for low-voltage conduction interference targeting frequencies in the range of 9kHz to 150kHz, it is also envisioned to increase the frequency of switching actions in the power conversion device or to increase the inductance of the reactor. However, this technology increases the loss (including heat dissipation) of the reactor, reduces the efficiency of the power conversion device, and reduces the operating range of the air conditioner. It is also envisioned to use a carrier filter, but this will lead to a decrease in efficiency during synchronous rectification and an increase in the size of the power conversion device.

[0015] In a single-phase three-phase power converter with an active buffer, particularly in a structure in which the output voltage of the converter is boosted to charge the capacitor, the DC current flowing through the inverter is switched between the current supplied from the power supply via the converter and the current supplied from the buffer circuit by turning on / off a discharge switch based on a prescribed carrier.

[0016] In a single-phase three-phase power converter with an active buffer, for example, the same period as the carrier used for the switch in the inverter is selected as the period of the carrier used for the switch in the discharge switch (for example, Japanese Patent Publication No. 2021-58002). The switch in the inverter uses a carrier with a frequency of about 5 kHz, for example, so it is preferable to meet the standard of low-voltage system higher harmonics with a frequency range of 2 kHz to 9 kHz as the target.

[0017] The converter in the single-phase three-phase power converter with active buffer is different from the technology disclosed in Japanese Patent No. 6478881, and is based on a current type converter and adopts a carrier filter. In order to increase the margin relative to the limit value in the standard of high-order harmonics in the low-voltage system, it is expected that the filter attenuation rate of the carrier filter will increase and the carrier frequency will increase, but such an increase is easily accompanied by a large-scale single-phase three-phase power converter with active buffer and a decrease in efficiency.

[0018] Techniques for reducing harmonics in power converters are presented in this disclosure.

[0019] Means for solving problems

[0020] The control method of the power converter disclosed in the present invention is a method for controlling a power converter (100). The power converter (100) comprises: a DC link (7); a converter (3) which rectifies a single-phase AC voltage (Vin), converts a first AC power based on the AC voltage into a DC power, and outputs a first instantaneous power (Pin); an active buffer (4) which exchanges power with the DC link (7) and performs buffering with a second instantaneous power (Pbuf); and an inverter (5) which converts a third instantaneous power (Pdc) input from the DC link (7) into a second AC power (Pout) and outputs the second AC power.

[0021] The active buffer (4) comprises: a booster (4b) for boosting a rectified voltage (Vrec) obtained by rectifying the AC voltage (Vin) to generate a first voltage (Vc); and a switch (4a, Sc, Qc) for intermittently applying the first voltage (Vc) from the booster (4b) to the DC link.

[0022] In a first mode of the control method of the power converter disclosed in the present invention, the switch (4a, Sc, Qc) is turned on at a first duty cycle (dc), and either or both of the first duty cycle (dc) and the first voltage (Vc) are controlled: when the second AC power (Pout) is above a second threshold value smaller than a first threshold value, the equivalent DC voltage (Vdc) is controlled to be higher than a peak value (Vm) of the rectified voltage (Vrec) and lower than the first voltage (Vc); when the second AC power (Pout) takes a first value larger than the first threshold value, the equivalent DC voltage (Vdc) is made higher than the equivalent DC voltage (Vdc) when the second AC power (Pout) takes a second value larger than the second threshold value and smaller than the first threshold value.

[0023] The equivalent DC voltage (Vdc) is applied to the DC link (7) and is a DC voltage obtained by dividing the third instantaneous power (Pdc) by a DC current (Idc) which is an average value of the current flowing through the inverter (5).

[0024] According to the first aspect of the method for controlling a power converter of the present disclosure, harmonics in the power converter are reduced.

[0025] A second mode of the control method of the power converter disclosed in the present invention is that in the first mode, the active buffer (4) inputs a fourth instantaneous power (PL) as a part of the first instantaneous power (Pin) from the DC link (7), outputs a fifth instantaneous power (Pc) to the DC link (7), and buffers the second instantaneous power (Pbuf=Pc-PL).

[0026] The third instantaneous power (Pdc) is the sum of the sixth instantaneous power (Prec) and the fifth instantaneous power (Pc) obtained by subtracting the fourth instantaneous power (PL) from the first instantaneous power (Pin). The power ratio is the ratio (Prec / Pin) of the sixth instantaneous power (Prec) to the first instantaneous power (Pin). In the second embodiment of the control method of the power converter disclosed in the present invention, the power ratio when the second AC power (Pout) takes the first value is made smaller than the power ratio when the second AC power (Pout) takes the second value.

[0027] A third aspect of the control method of the power converter of the present disclosure is that in the first aspect or the second aspect, when the second AC power (Pout) is greater than the second threshold value, a maximum value of a second duty ratio (drec) which is a value obtained by subtracting the first duty ratio (dc) from 1 is greater than 0 and less than or greater than and is equal to or less than 1. The third aspect of the control method of the power converter disclosed in the present invention further reduces harmonics.

[0028] A fourth aspect of the control method of the power converter of the present disclosure is that in the third aspect, when the second AC power (Pout) is greater than the second threshold value, the maximum value of the second duty ratio (drec) is greater than 0 and less than

[0029] According to the fourth aspect of the control method of the power converter disclosed in the present invention, the equivalent DC voltage can be increased. According to the third aspect, the maximum value of the second duty ratio is greater than When the ratio is less than 1, the efficiency of the power converter can be improved.

[0030] The fifth and sixth aspects of the control method of the power converter disclosed in the present invention are both in the fourth aspect, wherein the voltage step-up ratio (α) is a value obtained by dividing the first voltage (Vc) by the peak value (Vm), the voltage utilization rate (R) is a value obtained by dividing the equivalent DC voltage by the peak value (Vm), and the voltage step-up ratio (α) can also take any value from a third value (α1) and a fourth value (α2) greater than the third value. When the second AC power (Pout) is greater than the second threshold value: when the voltage step-up ratio (α) takes the third value (α1), for the voltage utilization rate (R) within a first range (J1) greater than 1, the amplitude (Ih') of the harmonics relative to the AC voltage (Vin) generated by the switching operation of the switch (4a, Sc, Qc) is greater than a predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the first range (J1), the amplitude (Ih') of the harmonics is less than the predetermined threshold value (TH2). When the voltage step-up ratio (α) takes the fourth value (α2), for the voltage utilization rate (R) within the second range (J2) greater than 1, the amplitude (Ih') of the harmonic is greater than the prescribed threshold value (TH2), and for the voltage utilization rate (R) outside the second range (J2), the amplitude (Ih') of the harmonic is less than the prescribed threshold value (TH2).

[0031] In a fifth aspect of the control method of the power converter of the present disclosure, when the voltage utilization rate (R) is larger than an upper limit (J2u) of the second range, the voltage step-up ratio (α) takes the fourth value (α2).

[0032] In a sixth aspect of the control method of the power converter disclosed herein, when the voltage utilization rate (R) is greater than an upper limit (J1u) of the first range and is less than an upper limit (J2u) of the second range (J2), the boost ratio (α) adopts the third value (α1).

[0033] The seventh mode of the control method of the power converter disclosed in the present invention is that in the fourth mode, the boost ratio (α) is a value obtained by dividing the first voltage (Vc) by the peak value (Vm), the voltage utilization rate (R) is a value obtained by dividing the equivalent DC voltage by the peak value (Vm), and the boost ratio (α) can also take any value between a third value (α1) and a fourth value (α2) larger than the third value (α1a; α1b). When the second AC power (Pout) is greater than the second threshold value: when the step-up ratio (α) takes the third value (α1a; α1b), for the voltage utilization rate (R) below the first lower limit value (d1) greater than 1, the amplitude (Ih') of the harmonics relative to the AC voltage (Vin) generated by the switching action of the switch (4a, Sc, Qc) is greater than a prescribed threshold value (TH3), and for the voltage utilization rate (R) greater than the first lower limit value (d1a; d1b), the amplitude (Ih') of the harmonics is less than the prescribed threshold value (TH3). When the voltage boost ratio (α) takes the fourth value (α2), for the voltage utilization rate (R) below the second lower limit value (d2) higher than the first lower limit value (d1a; d1b), the amplitude (Ih') of the harmonic is above the prescribed threshold value (TH3), and for the voltage utilization rate (R) greater than the second lower limit value (d2), the amplitude (Ih') of the harmonic is less than the prescribed threshold value (TH3).

[0034] In the seventh mode of the control method of the power converter disclosed in the present invention, when the third value (α1b) is greater than the second lower limit value (d2), when the voltage utilization rate (R) is greater than the first lower limit value (d1b) and less than the second lower limit value (d2), the boost ratio (α) adopts the third value (α1b); when the third value (α1a) is less than the second lower limit value (d2), when the voltage utilization rate (R) is greater than the first lower limit value (d1a) and less than the third value (α1), the boost ratio (α) adopts the third value (α1a).

[0035] The eighth mode of the control method of the power converter disclosed in the present invention is that in the seventh mode, when the third value (α1b) is greater than the second lower limit value (d2), when the voltage utilization rate (R) is greater than the second lower limit value (d2), the boost ratio (α) adopts the fourth value (α2).

[0036] According to the eighth aspect of the control method of the power converter of the present disclosure, the equivalent DC voltage is increased.

[0037] A ninth aspect of the control method of the power converter of the present disclosure is that in the third aspect, when the second AC power (Pout) is larger than the second threshold value, the maximum value of the second duty ratio (drec) is greater than Large and less than 1.

[0038] According to the ninth aspect of the control method of the power converter of the present disclosure, the efficiency of the power converter is improved.

[0039] The tenth and eleventh aspects of the control method of the power converter disclosed in the present invention are both in the ninth aspect, wherein the voltage step-up ratio (α) is a value obtained by dividing the first voltage (Vc) by the peak value (Vm), the voltage utilization rate (R) is a value obtained by dividing the equivalent DC voltage by the peak value (Vm), and the voltage step-up ratio (α) can also take any value from a third value (α1) and a fourth value (α2) greater than the third value. When the second AC power (Pout) is greater than the second threshold value: when the voltage step-up ratio (α) takes the third value (α1), for the voltage utilization rate (R) within a first range (J1) greater than 1, the amplitude (Ih') of the harmonics with respect to the AC voltage (Vin) generated by the switching operation of the switch (4a, Sc, Qc) is greater than a predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the first range (J1), the amplitude (Ih') of the harmonics is less than the predetermined threshold value (TH2). When the voltage step-up ratio (α) takes the fourth value (α2), for the voltage utilization rate (R) within the second range (J2) greater than 1, the amplitude (Ih') of the harmonic is greater than the prescribed threshold value (TH2), and for the voltage utilization rate (R) outside the second range (J2), the amplitude (Ih') of the harmonic is less than the prescribed threshold value (TH2).

[0040] In the tenth aspect of the control method of the power converter disclosed in the present invention, when the voltage utilization rate (R) is greater than the lower limit (J1d) of the first range and less than the lower limit (J2d) of the second range (J2), the boost ratio (α) adopts the fourth value (α2).

[0041] In the eleventh mode of the control method of the power converter of the present disclosure, when the first duty ratio (dc) takes the fifth value and the voltage step-up ratio (α) takes the fourth value (α2), the voltage utilization ratio (R) takes the lower limit (J1d) of the first range. In the eleventh mode of the control method of the power converter of the present disclosure, when the voltage utilization ratio (R) is less than the lower limit (J1d) of the first range, the first duty ratio takes a value less than the fifth value, and the voltage step-up ratio (α) takes the third value (α1).

[0042] According to the eleventh aspect of the control method of the power converter of the present disclosure, the efficiency of the power converter is improved.

[0043] A twelfth aspect of the control method of the power converter of the present disclosure is that in any one of the first to eleventh aspects, the booster (4b) has a boost chopper. In the twelfth aspect of the control method of the power converter of the present disclosure, the boost chopper chops the current (iL) input to the boost chopper using a frequency higher than the frequency of the carrier used in the switching operation of the inverter (5).

[0044] A thirteenth aspect of the control method of the power converter of the present disclosure is that in the twelfth aspect, the power converter (100) further includes a filter (2) having a cutoff frequency lower than the frequency of the carrier. The AC voltage (Vin) is input to the converter (3) via the filter (2).

[0045] A fourteenth aspect of the control method of the power converter of the present disclosure is that in the twelfth aspect, the power converter (100) further includes a filter (2) having a cutoff frequency lower than the frequency of the carrier wave. The converter (3) outputs the first instantaneous power (Pin=Prec+PL) via the filter (2).

[0046] The thirteenth and fourteenth aspects of the control method of the power converter disclosed herein both help to prevent the ripple current generated by the switching action of the inverter from propagating to the single-phase AC side, and to prevent the ripple current generated by the switching action in the booster from propagating to the single-phase AC side.

[0047] A fifteenth aspect of the control method of the power converter of the present disclosure is that in any one of the first to eleventh aspects, the booster (4b) has a boost chopper. In the fifteenth aspect of the control method of the power converter of the present disclosure, the boost chopper chops the current (iL) input to the boost chopper using a frequency higher than a frequency at which the switch (4a, Sc, Qc) performs a switching operation.

[0048] A sixteenth aspect of the control method of the power converter of the present disclosure is that in the fifteenth aspect, the power converter (100) further comprises a filter (2) having a cutoff frequency lower than the frequency at which the switch (4a, Sc, Qc) performs a switching operation. The AC voltage (Vin) is input to the converter (3) via the filter (2).

[0049] A seventeenth aspect of the control method of the power converter of the present disclosure is that in the fifteenth aspect, the power converter (100) further comprises a filter (2) having a cutoff frequency lower than the frequency at which the switch (4a, Sc, Qc) performs a switching operation. The converter (3) outputs the first instantaneous power (Pin=Prec+PL) via the filter (2).

[0050] The sixteenth and seventeenth aspects of the control method of the power converter disclosed herein both help to prevent the ripple current generated by the switching action of the switch from propagating to the single-phase AC side, and to prevent the ripple current generated by the switching action in the booster from propagating to the single-phase AC side.

[0051] The eighteenth mode of the control method of the power converter disclosed in the present invention, in any mode among the first to seventeenth modes, when the first duty cycle (dc) is controlled and the second AC power is smaller than the second threshold value, any of the following controls is adopted: alternately setting a non-conduction period in which the first duty cycle (dc) is 0 and a conduction period in which the first duty cycle (dc) is positive, and the non-conduction period and the conduction period both have a length of one quarter of the cycle of the AC voltage (Vin); and other controls in which the length of the non-conduction period is substantially 0.

[0052] According to the eighteenth aspect of the control method of the power converter of the present disclosure, the efficiency of the power converter is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 : is a circuit diagram showing the power converter and its periphery according to the present embodiment.

[0054] Figure 2 This is a block diagram schematically showing the balance of electric power in the electric power converter.

[0055] Figure 3 This is a circuit diagram showing an equivalent circuit of a power converter.

[0056] Figure 4 It is a graph showing the dependency of the power ratio on the voltage utilization rate.

[0057] Figure 5 is a graph illustrating equivalent PWM modulation.

[0058] Figure 6 This is a graph showing the relationship between the order and the amplitude of the harmonic component when the power supply frequency is set to the fundamental frequency.

[0059] Figure 7This is a graph showing the relationship between the order and the amplitude of the harmonic component when the power supply frequency is set to the fundamental frequency.

[0060] Figure 8 It is a graph that uses a broken line to represent the harmonic amplitude relative to frequency.

[0061] Fig. 9 It is a graph that uses a broken line to represent the harmonic amplitude relative to frequency.

[0062] Fig.10 It is a graph that uses a broken line to represent the harmonic amplitude relative to frequency.

[0063] Fig.11 is a graph illustrating the relationship between the modulation rate and the harmonic amplitude.

[0064] Fig.12 It is a graph that uses a broken line to represent the harmonic amplitude relative to frequency.

[0065] Fig.13 It is a graph that uses a broken line to represent the harmonic amplitude relative to frequency.

[0066] Fig.14 It is a graph that uses a broken line to represent the harmonic amplitude relative to frequency.

[0067] Fig.15 is a graph illustrating the relationship between the modulation rate and the harmonic amplitude.

[0068] Fig.16 It is a graph showing the dependence of harmonic amplitude on voltage utilization factor.

[0069] Fig.17 It is a graph showing the dependence of harmonic amplitude on voltage utilization factor.

[0070] Fig.18 This is a block diagram showing an example of a conceptual structure of a control device that controls a power converter.

[0071] Fig.19 This is a flowchart illustrating a routine for distinguishing the control methods of the power converter.

[0072] Fig. 20 It is a graph showing the pulse waveform in the carrier period.

[0073] Fig.21 It is a graph showing the relationship between the time ratio and the amplitude of the component of the converter-side carrier frequency of the pulse waveform.

[0074] Fig. 22 It is a graph showing the relationship between the phase of a signal wave and the time ratio.

[0075] Fig.23It is a graph showing the relationship between the phase of a signal wave and the time ratio.

[0076] Fig.24 This is a circuit diagram partially showing a power converter. DETAILED DESCRIPTION

[0077] A. The structure of the power converter.

[0078] (a-1) Overall structure and electricity revenue and expenditure

[0079] Figure 1 1 is a circuit diagram showing a power converter 100 and its periphery according to the present embodiment. The power converter 100 is a direct power conversion device, and its structure itself is known, for example, from Japanese Patent No. 5804167. The power converter 100 can be said to be an example of a power converter to which the power conversion method according to the present disclosure is applied, or an example of a power converter according to the present disclosure that is realized by performing a predetermined control.

[0080] Figure 2 1 is a block diagram schematically showing the balance of electric power in the electric power converter 100. The structure of this block diagram itself is also known from, for example, Japanese Patent No. 5804167.

[0081] The power converter 100 includes a filter 2, a converter 3, an active snubber 4, an inverter 5, and a DC link 7. The active snubber 4 buffers power as described later, and is therefore introduced as a "power snubber circuit 4" in Japanese Patent No. 5804167.

[0082] A single-phase AC voltage Vin and a single-phase AC current Iin are input to the power converter 100 from a single-phase AC power source 1 .

[0083] The converter 3 rectifies the AC voltage Vin to obtain a rectified voltage Vrec. The converter 3 converts the AC power into DC power by the rectification and outputs the instantaneous power Pin.

[0084] The active buffer 4 receives the instantaneous power PL (denoted as "Pl" in Japanese Patent No. 5804167) which is a part of the instantaneous power Pin from the converter 3, outputs the instantaneous power Pc, and buffers the instantaneous power Pbuf (=Pc-PL).

[0085] The inverter 5 receives the instantaneous power Prec (= Pin-PL) obtained by subtracting the instantaneous power PL from the instantaneous power Pin from the converter 3, and receives the instantaneous power Pc from the active buffer 4. The inverter 5 converts the instantaneous power Pdc, which is the sum of the instantaneous power Prec and the instantaneous power Pc, into the instantaneous power Pout and outputs it (the mark "Pout" is omitted in the Japanese Patent No. 5804167). The instantaneous power Pout is output to the AC load 6.

[0086] The DC link 7 includes DC power supply lines LH and LL.

[0087] (a-2) Description of Filter 2

[0088] The converter 3 is connected to the active buffer 4 via the filter 2. The filter 2 functions as a low-pass filter. For example, the filter 2 includes a reactor L2 and a capacitor C2. The capacitor C2 is provided between the DC power supply line LH and the DC power supply line LL, and is provided in parallel with the input side of the active buffer 4.

[0089] The filter 2 suppresses the ripple current generated by the switching operation accompanying the operation of the active snubber 4 and the operation of the inverter 5 from propagating to the single-phase AC power supply 1. On the other hand, the filter 2 also has a function of transmitting the rectified voltage Vrec to the active snubber 4. Therefore, the cutoff frequency of the filter 2 is set to be high enough to transmit the rectified voltage Vrec from the converter 3 to the active snubber 4, and low enough to suppress the ripple current generated by the switching operation from propagating to the single-phase AC power supply 1.

[0090] For example, the cutoff frequency of the filter 2 is lower than the frequency of the carrier used for the switching operation of the inverter 5 (hereinafter also referred to as "inverter-side carrier frequency"). For example, the cutoff frequency of the filter 2 is lower than the frequency of the switching operation of the switch (described later) that determines whether the capacitor provided in the active snubber 4 is discharged.

[0091] The filter 2 can be ignored in the balance of power. When the loss in the converter 3 is ignored, the main power supplied to the converter 3 by the AC voltage Vin and the AC current Iin is supplied to the DC link 7 as the instantaneous power Pin.

[0092] (a-3) Description of Converter 3

[0093] The converter 3 is, for example, a diode bridge and includes diodes D31 to D34. The diodes D31 to D34 form a bridge circuit and perform single-phase full-wave rectification on the AC voltage Vin to convert it into a rectified voltage Vrec (ideally equal to the absolute value |Vin| of the AC voltage Vin).

[0094] The converter 3 applies a rectified voltage Vrec to the active buffer 4 via the filter 2. The rectified voltage Vrec is output between the DC power supply lines LH and LL, and a higher potential than that of the DC power supply line LL is applied to the DC power supply line LH.

[0095] (a-4) Description of Active Buffer 4

[0096] The active buffer 4 includes a switching circuit 4 a and a booster 4 b . The active buffer 4 receives instantaneous power PL from the DC link 7 and outputs instantaneous power Pc to the DC link 7 .

[0097] (a-4-1) Description of Switching Circuit 4a

[0098] The switch circuit 4a includes a diode D42 and a transistor Qc. The diode D42 is connected in series with a capacitor C4 described later between the DC power supply lines LH and LL. The forward direction of the diode D42 is arranged in a direction from the DC power supply line LH toward the DC power supply line LL. The diode D42 is arranged closer to the DC power supply line LH than the capacitor C4.

[0099] The transistor Qc is, for example, an insulated gate bipolar transistor (hereinafter referred to as "IGBT"). The transistor Qc is connected in reverse parallel to the diode D42. Here, reverse parallel connection means parallel connection with forward directions opposite to each other. Specifically, the forward direction of the transistor Qc is the direction from the DC power line LL to the DC power line LH, and the forward direction of the diode D42 is the direction from the DC power line LH to the DC power line LL.

[0100] The capacitor C4 is discharged by turning on the transistor Qc, and the instantaneous power Pc is output from the active buffer 4 to the DC link 7. The current ic flows from the capacitor C4 to the DC link 7, and the instantaneous power Pc is output from the active buffer 4 to the DC link 7.

[0101] The current irec1 flows from the converter 3 to the inverter 5 (described later) via the DC link 7 .

[0102] The direct current Idc supplied to the inverter 5 is divided into currents ic and irec1 based on the conduction ratios dc and drec as shown in the equation (1).

[0103] [Mathematical formula 1]

[0104] ic=dc·Idc, irec1=drec·Idc…(1)

[0105] (a-4-2) Description of Supercharger 4b

[0106] The booster 4b includes a capacitor C4, a diode D40, a reactor L4, and a transistor QL.

[0107] The diode D40 has a cathode and an anode, and the cathode is connected between the transistor Qc and the capacitor C4. The reactor L4 is connected between the DC power supply line LH and the anode of the diode D40. The transistor QL is connected between the DC power supply line LL and the anode of the diode D40. The transistor QL is, for example, an IGBT. In the booster 4b, the capacitor C4 is charged to a voltage Vc via the diode D40. Hereinafter, the voltage Vc applied to both ends of the capacitor C4 is also referred to as a "capacitor voltage".

[0108] For example, by intermittently switching transistor QL (through so-called chopper), reactor L4 accumulates and releases energy, thereby boosting rectified voltage Vrec to charge capacitor C4. By performing such an operation, diode D40, reactor L4, and transistor QL can be understood as a boost chopper.

[0109] However, the booster 4b can also charge the capacitor C4 without boosting the rectified voltage Vrec. For example, by continuously turning on the transistor QL (maintaining non-conduction), the current iL flowing through the reactor L4 charges the capacitor C4 via the diode D40. Through this charging, the capacitor voltage Vc can be regarded as being equal to the peak value Vm (which is also the amplitude of the AC voltage Vin, and is assumed to be a constant value) of the rectified voltage Vrec. This is because the peak value Vm is usually large enough to ignore the voltage drop in the diodes D31, D33, D40 and the reactors L2 and L4.

[0110] The operation of the supercharger 4b in which Vc=Vm is known in, for example, Japanese Patent Application Publication No. 2021-58002. The operation of the supercharger 4b in which Vc>Vm is known in, for example, Japanese Patent Application Publication No. 5804167.

[0111] The booster 4b further includes a diode D41. The diode D41 is connected in reverse parallel to the transistor QL. Specifically, the forward direction of the transistor QL is from the DC power line LH to the DC power line LL, and the forward direction of the diode D41 is from the DC power line LL to the DC power line LH.

[0112] Since the potential of the DC power supply line LH is higher than the potential of the DC power supply line LL, basically no current flows through the diode D41. Since Vc≥Vm≥Vrec, basically no current flows through the diode D42.

[0113] A current irec (which is equal to the absolute value |Iin| of the AC current Iin, ignoring the harmonic components blocked by the filter 2) flows from the converter 3 into the DC link 7. A current iL flows from the DC link 7 into the booster 4b, and a current irec1 flows in the DC link 7 between the booster 4b and the switch circuit 4a. Since the currents iL and irec1 are separated from the current irec, equation (2) holds.

[0114] [Mathematical formula 2]

[0115] irec=irec1+iL…(2)

[0116] As shown in equation (1), the DC current Idc is split into a current irec1 and a current ic via the DC link 7 .

[0117] (a-4-3) Description of Current Blocking Element D0

[0118] The current blocking element D0 is inserted into the DC power line LH between the switch circuit 4a and the booster 4b. When the switch circuit 4a is turned on, the capacitor voltage Vc is applied from the active buffer 4 to the DC power line LH on the inverter 5 side of the current blocking element D0, and the rectified voltage Vrec is applied from the converter 3 to the DC power line LH via the filter 2 on the converter side of the current blocking element D0. The converter 3 outputs the instantaneous power Pin via the filter 2.

[0119] Since Vc≥Vm≥Vrec, the current blocking element D0 helps to maintain the potential of the inverter 5 side higher than the potential of the converter 3 side. The current blocking element D0 blocks the current from flowing from the capacitor C4 to the filter 2 via the DC power supply line LH, thereby blocking the charging of the capacitor C2 based on the capacitor voltage Vc.

[0120] The current blocking element D0 is, for example, a diode. The anode of the diode is connected to the anode of the diode D40 via the reactor L4. The cathode of the diode is connected to the cathode of the diode D40 via the switch circuit 4a.

[0121] (a-5) Description of Inverter 5

[0122] The inverter 5 converts the DC voltage between the DC power lines LH and LL on the inverter 5 side relative to the current blocking element D0 into an AC voltage, and outputs the AC voltage to the output terminals Pu, Pv, and Pw. The inverter 5 includes six switching elements Sup, Svp, Swp, Sun, Svn, and Swn. The switching elements Sup, Svp, and Swp are respectively connected between the output terminals Pu, Pv, and Pw and the DC power line LH, and the switching elements Sun, Svn, and Swn are respectively connected between the output terminals Pu, Pv, and Pw and the DC power line LL. The inverter 5 constitutes a so-called voltage-type inverter, and includes six diodes Dup, Dvp, Dwp, Dun, Dvn, and Dwn.

[0123] The diodes Dup, Dvp, Dwp, Dun, Dvn, and Dwn are configured such that their cathodes face the DC power line LH side and their anodes face the DC power line LL side. The diode Dup is connected in reverse parallel to the switching element Sup between the output terminal Pu and the DC power line LH. Similarly, the diodes Dvp, Dwp, Dun, Dvn, and Dwn are connected in reverse parallel to the switching elements Svp, Swp, Sun, Svn, and Swn, respectively.

[0124] The output terminals Pu, Pv, and Pw respectively output alternating currents Iu, Iv, and Iw, which constitute a three-phase alternating current, to the load 6. For example, the switching elements Sup, Svp, Swp, Sun, Svn, and Swn are IGBTs.

[0125] (a-6) Description of AC load 6

[0126] The AC load 6 is an inductive load, such as a three-phase motor. Figure 1 In the figure, an equivalent circuit representing an AC load 6 as an inductive load is illustrated. Specifically, the AC load 6 is shown to include reactors Lu, Lv, Lw and resistors Ru, Rv, Rw. One end of the series connection of the reactor Lu and the resistor Ru is connected to the output terminal Pu. One end of the series connection of the reactor Lv and the resistor Rv is connected to the output terminal Pv. One end of the series connection of the reactor Lw and the resistor Rw is connected to the output terminal Pw. The other ends of each of these three series connections are connected to each other, and the AC load 6 has a structure called a so-called star connection.

[0127] (a-7) Description of equivalent circuit

[0128] Figure 3 : is a circuit diagram showing an equivalent circuit of the power converter 100. In this equivalent circuit, the single-phase AC power source 1, the filter 2, and the converter 3 are collectively represented as a voltage source that outputs the voltage |Vin|.

[0129] In this equivalent circuit, the current irec1 is equivalently expressed as the current irec1 passing through the switch Srec when the switch Srec is conducting. The conduction of the switch Srec indicates irec1>0, and the non-conduction of the switch Srec indicates irec1=0. How the switch Srec is conducted / non-conducted will be described later.

[0130] The current ic is equivalently expressed as the current ic passing through the switch Sc when the switch Sc is on. The on state of the switch Sc indicates ic>0, and the off state of the switch Sc indicates ic=0. The on / off state of the switch Sc equivalently indicates the on / off state of the transistor Qc.

[0131] The equivalent circuit shows capacitor C4, reactor L4, diode D40 and switch SL constituting booster 4b, and current iL flowing through reactor L4 is indicated. On / off of switch SL equivalently indicates on / off of transistor QL.

[0132] The inverter 5 is represented by a switch Sz, a DC current source Idc, and an equivalent voltage source Vo. The conduction of the switch Sz equivalently represents a condition in which the output terminals Pu, Pv, and Pw of the inverter 5 are connected to any one of the DC power supply lines LH and LL (hereinafter also referred to as a "return condition"). When the switch Sz is turned on, the current iz flows through the switch Sz. The current iz equivalently represents the current flowing to the AC load 6 via the inverter 5 under the return condition (hereinafter also referred to as a "zero-sequence current").

[0133] When the switch Sz is not turned on, the DC current Idc flows from the voltage source of the output voltage |Vin| to the inverter 5 as the current irec1 and flows from the booster 4b to the inverter 5 as the current ic in a time-division manner.

[0134] The equivalent current source Io converts the AC currents Iu, Iv, and Iw flowing from the inverter 5 to the AC load 6 into a DC current Io and equivalently represents the equivalent voltage source Vo converts the AC voltage applied by the inverter 5 to the AC load 6 into a DC voltage and equivalently represents the equivalent voltage source Vo.

[0135] In the equivalent circuit, the modulation rate D of the inverter 5 is expressed as Vo / Vdc using the equivalent DC voltage Vdc between the DC power supply lines LH and LL and the DC voltage Vo output by the equivalent voltage source Vo.

[0136] The instantaneous power Pdc input to the inverter 5 is equal to the instantaneous power Pout output from the inverter 5 (see Figure 2 ), the instantaneous power Pdc is represented by the product of the equivalent DC voltage Vdc and the DC current Idc, and the instantaneous power Pout is represented by the product of the DC voltage Vo and the DC current Io flowing through the equivalent current source Io, so the modulation rate D is also represented by Idc / Io.

[0137] Introducing the duty ratios drec, dc, and dz of the switches Srec, Sc, and Sz when they are turned on in the equivalent circuit, equation (3) is established through equation (2). The duty ratios drec and dc are equal to the conduction ratios drec and dc described above.

[0138] [Mathematical formula 3]

[0139]

[0140] The currents irec1, ic, iz are obtained by multiplying the direct current Idc by the duty cycles drec, dc, dz, respectively, and therefore they are average values ​​in the switching period of the switches Srec, Sc, Sz.

[0141] In addition, the DC current Idc is the sum of the currents irec1, ic, iz flowing through the switches Srec, Sc, Sz, respectively, so the equation (4) holds. Where, 0≤drec≤1, 0≤dc≤1, 0≤dz≤1.

[0142] [Formula 4]

[0143] drec+dc+dz=1…(4)

[0144] Specific examples of the duty ratios drec, dc, and dz are introduced in, for example, Japanese Patent No. 5804167, Japanese Patent No. 5629885, and Japanese Patent Application Laid-Open No. 2021-58002.

[0145] When the switch Sz is turned on, the currents irec1 and ic are both 0, and the switches Srec and Sc are both equivalently non-conductive. When the switch Sz is non-conductive, the switch Sc can be turned on. When the switch Sc is turned on, the capacitor voltage Vc (≥Vm≥Vrec) is applied to the DC link 7, so irec1=0, and the switches Srec and Sz are both equivalently non-conductive. If the switch Sc is also non-conductive when the switch Sz is non-conductive, the current irec1 flows through the DC power supply line LH. Therefore, it can be said that one of the switches Srec, Sc, and Sz is turned on instantaneously.

[0146] Converter 3 actively prevents current irec1 from flowing to DC link 7. Switching of inverter 5 limited by duty cycle dz and switching of switch Sc by duty cycle dc determine conduction / non-conduction of switch Srec, and current irec1 flows (irec1>0) or does not flow (irec1=0) accordingly.

[0147] The DC voltage used to supply power to the inverter 5 in the DC link 7 is meaningful in power conversion. In other words, the instantaneous DC voltage and the inverter 5 not being used for power conversion are meaningless from the perspective of power and harmonics. In addition, the inverter 5 cannot use the DC voltage in the DC link 7 to perform power conversion while the zero-sequence current iz flows.

[0148] From this viewpoint, the equivalent DC voltage Vdc is applied to the DC link 7 and is a DC voltage obtained by dividing the instantaneous power Pdc by the DC current Idc.

[0149] When the switch Srec is conducting, the switch Sc is non-conducting, and the rectified voltage Vrec is applied to the DC link 7. When the switch Sc is conducting, the switch Srec is non-conducting, and the capacitor voltage Vc is applied to the DC link 7. Therefore, in this embodiment, as the equivalent DC voltage Vdc, the sum of the product Vrec·drec of the duty cycle drec and the rectified voltage Vrec and the product Vc·dc of the duty cycle dc and the capacitor voltage Vc is used.

[0150] The equivalent DC voltage Vdc can also be grasped as the voltage applied to the DC link 7 as the average of the maximum value of the voltage that the inverter 5 can output with respect to the period of the switching operation of the control switches Sc and SL and the inverter 5. This is because, during the period corresponding to the duty cycle dz, the switches Srec and Sc are both non-conductive, the inverter 5 is in a reflux state, and the inverter 5 is not electrically connected to the DC link 7.

[0151] The equivalent DC voltage Vdc is Figure 3 denoted as the voltage applied to the input side of the inverter 5 .

[0152] B. Reduction of harmonics caused by the carrier wave used in the switching action of the inverter 5

[0153] (b-1) Control based on equivalent DC voltage Vdc

[0154] The carrier component of the switching action in the inverter 5 is a harmonic for the current irec and thus for the AC current Iin. And, according to equations (1) and (2), irec = drec·Idc+iL. The smaller the DC current Idc, the smaller the harmonics in the current irec caused by the switching action of the inverter 5. With respect to the modulation rate D, the following equation (5) holds.

[0155] [Formula 5]

[0156] D=Idc / Io=Vo / Vdc…(5)

[0157] If the instantaneous power Pout (=Io·Vo) is constant, increasing the equivalent DC voltage Vdc helps reduce the DC current Idc, which in turn helps reduce the harmonics in the frequency band related to the low-voltage system harmonics in the power converter 100 (hereinafter also referred to as "higher harmonics").

[0158] The equivalent DC voltage Vdc is the sum of the product drec·Vrec and the product dc·Vc. If the duty cycle dz is constant (e.g., zero), the larger the duty cycle dc, the smaller the duty cycle drec. Therefore, by increasing either or both of the duty cycle dc and the capacitor voltage Vc, the equivalent DC voltage Vdc can be increased.

[0159] For convenience of description, the operation of the power converter 100 when Vm<Vdc (≤Vc) may be referred to as a boost operation, and the operation of the power converter 100 when Vdc≤Vm may be referred to as a non-boost operation.

[0160] (b-2) Control based on duty cycle dc or capacitor voltage Vc

[0161] When instantaneous power Pc is supplied to the DC link 7, the switch Srec is non-conductive and the switch Sc is conductive. When instantaneous power Prec is supplied to the DC link 7, the switch Sc is non-conductive and the switch Srec is conductive. The conduction of the switch Srec transmits the carrier component of the switching operation in the inverter 5 to the current irec. From this point of view, it can be said that the reduction of the instantaneous power Prec contributes to the reduction of higher harmonics in the power converter 100.

[0162] For the convenience of the following description, the voltage step-up ratio α and the voltage utilization rate R are introduced. In addition, for the sake of simplicity of description, the case where the duty ratio dz is 0 (that is, the case where drec=1-dc) is exemplified.

[0163] The voltage step-up ratio α is defined by a ratio Vc / Vm of the capacitor voltage Vc to the peak value Vm.

[0164] The voltage utilization rate R is defined by the ratio Vdc / Vm of the equivalent DC voltage Vdc to the peak value Vm. If the duty cycle dc is fixed, the equivalent DC voltage Vdc increases as the boost ratio α increases. If the boost ratio α is fixed, the equivalent DC voltage Vdc increases as the duty cycle dc increases. Since dc≤1, R≤α.

[0165] Figure 4 Graph showing the dependence of the power ratios Prec / Pin and PL / Pin on the voltage utilization rate R when the voltage step-up ratio α is used as a parameter. The example shows a case where the equivalent DC voltage Vdc is controlled to be a constant value independent of the phase ωt of the AC voltage Vin.

[0166] In any voltage step-up ratio α, regardless of the voltage utilization rate R, there is a relationship of Prec / Pin+PL / Pin=1. The broken lines G11 and G12 represent the ratio Prec / Pin, and the broken lines G21 and G22 represent the ratio PL / Pin. The broken lines G11 and G21 represent the case of α=1.29, and the broken lines G12 and G22 represent the case of α=1.47.

[0167] The voltage utilization rate R is controlled by the duty ratio drec and dc. When dc=1, Vdc=Vc, R=α, Prec / Pin=0 in any of the broken lines G11 and G12, and PL / Pin=1 in any of the broken lines G21 and G22.

[0168] When the capacitor voltage Vc or the boost ratio α is considered to be fixed, when the duty cycle dc increases, the instantaneous power Prec decreases due to the decrease in the duty cycle drec. At this time, the equivalent DC voltage Vdc also increases. Therefore, in the broken lines G11 and G12 where the boost ratio α is fixed, the ratio Prec / Pin decreases relative to the increase in the voltage utilization rate R. When the capacitor voltage Vc is maintained, it can be said that the decrease in the instantaneous power Prec accompanied by the increase in the equivalent DC voltage Vdc contributes to the reduction of higher harmonics in the power converter 100.

[0169] On the other hand, when it is not necessary to maintain the capacitor voltage Vc, the instantaneous power Prec can be reduced without increasing the equivalent DC voltage Vdc. This is because, for example, even if the capacitor voltage Vc is reduced and the duty cycle dc is increased while maintaining the product dc·Vc, the ratio Prec / Pin becomes smaller. This can also be understood from the fact that the broken line G11 represents a value lower than the broken line G12 regardless of the value of the voltage utilization rate R.

[0170] As described above, since the ratio Prec / Pin decreases with increasing voltage utilization rate R, increasing the equivalent DC voltage Vdc when increasing instantaneous power Pout helps reduce higher harmonics in power converter 100. Also, as described above, increasing duty cycle dc increases the equivalent DC voltage Vdc.

[0171] (b-3) Summary

[0172] In (b-1), it is explained that by increasing the equivalent DC voltage Vdc and reducing the DC current Idc, even if the duty cycle dc is not necessarily increased, the higher harmonics in the power converter 100 can be reduced. In (b-2), it is explained that even if the equivalent DC voltage Vdc is not necessarily increased, by increasing the duty cycle dc, the higher harmonics in the power converter 100 can be reduced.

[0173] By introducing two threshold values ​​for the instantaneous power Pout, specifically, introducing a first threshold value and a second threshold value smaller than the first threshold value, the following description is obtained based on (b-1) and (b-2).

[0174] The voltage step-up operation is adopted when the instantaneous power Pout outputted from the inverter 5 is equal to or higher than the second threshold value. By adopting the voltage step-up operation, even if the instantaneous power Pout is large, the direct current Idc can be reduced, thereby reducing harmonics.

[0175] When the instantaneous power Pout is above the second threshold and the boost action is adopted, the control depending on the instantaneous power Pout is different with the first threshold as the boundary. When the instantaneous power Pout takes a value greater than the first threshold (an example of the value at this time is temporarily referred to as the "first value") and when the instantaneous power Pout takes a value less than the first threshold (an example of the value at this time is temporarily referred to as the "second value": the second value is greater than the second threshold), the equivalent DC voltage Vdc is different.

[0176] More specifically, the equivalent DC voltage Vdc when the instantaneous power Pout takes the first value is higher than the equivalent DC voltage Vdc when the instantaneous power Pout takes the second value. This is because, as described above, harmonics are reduced by reducing the DC current Idc or by reducing the instantaneous power Prec.

[0177] If the latter case is explained in conjunction with (b-2), it can be explained that the ratio Prec / Pin when the instantaneous power Pout takes the first value is smaller than the ratio Prec / Pin when the instantaneous power Pout takes the second value.

[0178] C. Reduction of harmonics caused by the switching action of switch Sc

[0179] The switch Sc determines whether the current ic is merged with the current irec1. The switching operation of the switch Sc generates harmonics in the power converter 100.

[0180] For example, as disclosed in Japanese Patent Publication No. 2021-58002, the period of the carrier used to set the timing of conduction / non-conduction of the switch Sc is equal to the period of the carrier used to set the timing of conduction / non-conduction of the switching elements Sup, Svp, and Swp. The switch Sc switches from the conduction state to the non-conduction state once in one period of the carrier, and switches from the non-conduction state to the conduction state once. Therefore, the frequency of the harmonics caused by the carrier component of the inverter 5 and the frequency of the harmonics caused by the switching action of the switch Sc are both the standard objects of the high-order harmonics of the low-voltage system.

[0181] Combination Figure 3From the equivalent circuit shown, the current irec1 flowing from the converter 3 to the DC link 7 is positive / zero due to the conduction / non-conduction of the switch Srec. Therefore, as long as the current irec1 is focused, the converter 3 can be equivalently regarded as a current source rectifier that performs PWM modulation. Hereinafter, the above PWM modulation when the converter 3 is regarded as an equivalent current source rectifier is temporarily referred to as "equivalent PWM modulation".

[0182] The modulation rate ks in the equivalent PWM modulation can be considered to be controlled by the duty cycle drec of the switch Srec. The duty cycle drec is passively determined by the duty cycle dc of the switch Sc, so the modulation rate ks can be considered to be controlled by the duty cycle dc.

[0183] The harmonics are processed by taking the AC current Iin as the fundamental wave, and the fundamental wave of the current irec1 is consistent with the product of the modulation rate ks and the current irec, ks·irec. The current irec is obtained by full-wave rectification of the AC current Iin. Therefore, as a signal wave in the equivalent PWM modulation, a sine wave having the same period as the AC current Iin and therefore the same period as the AC voltage Vin is assumed.

[0184] Since the current iL flows, the current irec1 is different from the current irec and is not limited to a sine wave. However, the current irec1 has the same period as the current irec. Therefore, as long as at least the tendency of increase and decrease of higher harmonics is understood, it is appropriate to assume a sine wave as described above for the signal wave.

[0185] Figure 5 is a graph illustrating equivalent PWM modulation. As described above, the signal wave drecb uses a sine wave having the same period as the AC voltage Vin. Two carrier waves Cp and Cn are used for equivalent PWM modulation.

[0186] For example, any of the carrier waves Cp and Cn is a symmetrical triangular wave having a frequency 16 times the frequency of the AC voltage Vin (fs=ω / 2π, hereinafter also referred to as the "power supply frequency"). Here, the following case is exemplified: the power supply frequency is 50 Hz, and the frequencies of the carrier waves Cp and Cn (hereinafter also referred to as the "converter-side carrier frequency") are 0.8 kHz. In practice, the converter-side carrier frequency uses a higher frequency, such as 4.5 kHz as described above, but the case of 0.8 kHz is exemplified here to improve visual recognition in the diagram. The carrier wave Cp takes a value greater than 0 and less than 1, and the carrier wave Cn takes a value greater than -1 and less than 0.

[0187] The signal wave drecb is a sine wave with the power supply frequency. Figure 5 exemplified in the case where the modulation rate ks is 1, that is, the minimum value of the signal wave drecb is -1 and the maximum value is 1.

[0188] The pulse waveform Srecb reflects the conduction / non-conduction of the switch Srec. The pulse waveform Srecb is determined by the intersection of the carrier waves Cp and Cn and the signal wave drecb. As described above, the signal wave drecb uses the above-mentioned sine wave, so the pulse waveform Srecb takes any value among -1, 0, and 1.

[0189] Specifically, when the value of the signal wave drecb is higher than any value of the carrier waves Cp and Cn, the pulse waveform Srecb takes a value of 1, and when the value of the signal wave drecb is lower than any value of the carrier waves Cp and Cn, the pulse waveform Srecb takes a value of -1. When the value of the signal wave drecb is higher than the value of the carrier wave Cn and lower than the value of the carrier wave Cp, the pulse waveform Srecb takes a value of 0.

[0190] The case where the pulse waveform Srecb takes a value between -1 and 1 corresponds to the conduction of the switch Srec, and the case where the pulse waveform Srecb takes a value of 0 corresponds to the non-conduction of the switch Srec. If the case where dz=0 is considered in the boost operation, the case where the pulse waveform Srecb takes a value between -1 and 1 corresponds to the non-conduction of the switch Sc, and the case where the pulse waveform Srecb takes a value of 0 corresponds to the conduction of the switch Sc.

[0191] By obtaining the Fourier coefficients of the pulse waveform Srecb (described in detail later), the harmonic current caused by the switching operation of the switch Sc is analyzed. Figure 6 and Figure 7 Each of them is a graph showing the relationship between the order when the power supply frequency is the fundamental frequency and the amplitude of the harmonic component of the current irec1 (hereinafter also referred to as “harmonic amplitude”). However, this amplitude is standardized according to the amplitude of the fundamental frequency component of the current irec1.

[0192] Figure 6 and Figure 7 All about Figure 5 The graph shown is a PWM modulation graph using carriers Cp, Cn. Figure 6 The harmonic amplitude when the modulation rate ks is 1 is represented by a broken line. Figure 7 The broken line represents the harmonic amplitude when the modulation rate ks is 0.5, that is, when the minimum value of the signal wave drecb is -0.5 and the maximum value is 0.5. Figure 6 and Figure 7 It can be seen from the comparison that the magnitude and distribution of harmonic amplitude are affected by the modulation rate ks.

[0193] This effect is explained in other viewpoints as follows. The duty cycle drec is indirectly controlled by controlling the duty cycle dc. According to the principle of PWM modulation and Figure 5It can be seen that by controlling the pulse waveform Srecb, the waveform of the signal wave drecb can be approximately obtained. As long as the signal wave drecb is related to the analysis of higher harmonics, it can be treated as the waveform of the current irec1. In this way, the modulation rate ks is controlled by controlling the duty cycle dc, and the distribution and amplitude of the higher harmonics in the current irec1 and the AC current Iin are controlled.

[0194] When the AC load 6 functions as a constant current load, the DC current Idc supplied to the inverter 5 does not change. At this time, the increase or decrease of the duty cycle dc also affects the amplitude of the current irec1 itself. This is because the larger the duty cycle dc, the larger the current ic. According to formula (1), when the DC current Idc does not change, the current irec1 is smaller. For example, when the duty cycle dc takes a value of 0, the current ic also takes a value of 0, and the modulation rate ks takes a value of 1. At this time, the voltage utilization factor R takes a value of 1 (that is, Vdc = Vm). For example, when the duty cycle dc takes a value of 1, the current irec1 takes a value of 0, and the modulation rate ks takes a value of 0. At this time, the voltage utilization factor R is equal to the boost ratio α (that is, Vdc = Vc).

[0195] Figure 8 , Fig. 9 , Fig.10 Each of them is a graph showing harmonic amplitude relative to frequency using a broken line. Fig.11 is a graph illustrating the relationship between the modulation rate ks and the harmonic amplitude. Figure 5 to Figure 7 different, Figure 8 to Figure 11 The case where the frequency of the carrier waves Cp and Cn (hereinafter also referred to as "converter-side carrier frequency") is 4.5 kHz and 90 times the basic frequency is shown. It is assumed that the DC current Idc supplied to the inverter 5 does not change.

[0196] Figure 8 , Fig. 9 , Fig.10 Both represent the carrier frequency on the converter side and its nearby harmonic amplitudes. Figure 8 , Fig. 9 , Fig.10 They represent the harmonic amplitudes when the modulation rate ks is 0.2, 0.6, and 1.0 respectively.

[0197] exist Fig.11 In FIG. 1 , the broken line G31 represents the harmonic amplitude of the frequency (fc-fs) when the converter side carrier frequency is set to fc=4.5kHz and the fundamental frequency is set to the power supply frequency fs=50Hz. This is also equal to the harmonic amplitude of the frequency (fc+fs). Hereinafter, the harmonic of the frequency (fc-fs) is temporarily referred to as the primary side band harmonic.

[0198] exist Fig.11In FIG. 1 , the broken line G33 represents the harmonic amplitude of the frequency having the value (fc-3·fs). It is also equal to the harmonic amplitude of the frequency having the value (fc+3·fs). Hereinafter, the harmonic of the frequency having the value (fc-3·fs) is temporarily referred to as the third side band harmonic.

[0199] exist Fig.11 In FIG. 1 , the broken line G35 represents the harmonic amplitude of the frequency having the value (fc-5·fs). It is also equal to the harmonic amplitude of the frequency having the value (fc+5·fs). Hereinafter, the harmonic of the frequency having the value (fc-5·fs) is temporarily referred to as the fifth side band harmonic.

[0200] For example, the duty cycle dc is set to a value of (Vrec-Vdc) / (Vrec-Vc), and the duty cycle drec is set to a value of (Vdc-Vc) / (Vrec-Vc) (Vc≥Vdc≥Vrec: for example, refer to equations (9) and (10) of Japanese Patent No. 6418287). When the duty cycle dc=0, Vdc=Vrec, and when the duty cycle dc=1, Vdc=Vc.

[0201] When the modulation rate ks takes a value of 0, the duty cycle drec=0, the current irec1=0, the duty cycle dc=1, there is no switching action of the switch Sc, and no harmonics are generated. Therefore, when the modulation rate ks takes a value of 0, the primary side band harmonics, the third side band harmonics, and the fifth side band harmonics are all 0.

[0202] Over substantially all values ​​of the modulation rate ks (at modulation rates ks substantially less than a value of 0.98), the harmonic amplitude of the primary sideband harmonics is greater than the harmonic amplitude of any of the third sideband harmonics and the fifth sideband harmonics.

[0203] As the modulation rate increases, the harmonic amplitudes of the third-order side harmonics and the fifth-order side harmonics increase monotonically. The harmonic amplitudes of the primary-order side harmonics take a maximum value relative to the modulation rate. According to the approximate calculation described later, the value of the modulation rate ks that gives the primary-order side harmonics a maximum value is

[0204] From the viewpoint of reducing the higher harmonics of the power converter 100, for example, the duty ratio dc is controlled so as to avoid the modulation rate ks at which the harmonic amplitude of the primary-side band harmonics takes a maximum value.

[0205] Fig.12 , Fig.13 , Fig.14 Both are graphs that use broken lines to represent harmonic amplitudes relative to frequency. Figure 8 to Figure 11 Similarly, in Figure 12 to Figure 14 The case where the converter side carrier frequency fc is 4.5kHz and 90 times the basic frequency (which is equal to the power supply frequency fs) is also illustrated in FIG. Figure 8 to Figure 11 Differently, the case where sawtooth waves are used as carrier waves Cp and Cn is shown. Here, it is also assumed that the direct current Idc supplied to the inverter 5 does not change.

[0206] Fig.12 , Fig.13 , Fig.14 Both represent the carrier frequency on the converter side and its nearby harmonic amplitudes. Fig.12 , Fig.13 , Fig.14 They represent the harmonic amplitudes when the modulation rate ks is 0.2, 0.6, and 1.0 respectively.

[0207] Fig.15 is a graph showing the relationship between the modulation rate ks and the harmonic amplitude when a sawtooth wave is used as the carrier wave Cp, Cn. Fig.15 In FIG. 1 , broken lines G41 , G43 , and G45 respectively represent the harmonic amplitude of the primary side band harmonic, the harmonic amplitude of the third side band harmonic, and the harmonic amplitude of the fifth side band harmonic.

[0208] Figure 8 to Figure 11 Corresponding to Figure 12 to Figure 15 , and the difference between the two groups is derived from the waveform of the carrier waves Cp and Cn. In the case where sawtooth waves are used for the carrier waves Cp and Cn ( Figure 12 to Figure 15 ), the distribution of higher harmonics is better than that of symmetrical triangle wave for carriers Cp and Cn ( Figure 8 to Figure 11 ) has a wider distribution of higher harmonics and a smaller harmonic amplitude in the primary band (see Fig.11 The polyline G31 and Fig.15 The broken line G41).

[0209] Fig.16 Graph showing the dependence of the harmonic amplitude Ih of the primary band harmonic on the voltage utilization factor R. The broken line G51 represents the case where the voltage step-up ratio α takes a value of 1.29. The broken line G52 represents the case where the voltage step-up ratio α takes a value of 1.47. Fig.16 Equivalent to Fig.11 The polyline G31, but the horizontal axis is Fig.11 different. Fig.16 The circle shown is Fig.11 The circles shown correspond.

[0210] exist Fig.11 In the case of modulation rate ks = 1, Vdc = Vm. Fig.16 In , the voltage utilization rate R takes the value of 1 (corresponding to the circles at the left ends of the broken lines G51 and G52 respectively: the two are consistent). Fig.11 When the modulation rate ks=0, Vdc=Vc, and the voltage utilization factor R is equal to the voltage step-up ratio α (corresponding to the circles at the right ends of the broken lines G51 and G52).

[0211] As described above, the fundamental wave component of the current irec1 is introduced with a modulation rate ks and represented by ks·irec. As long as the harmonics are focused on, the amplitude Cm of the carrier waves Cp and Cn can be introduced, and the signal wave drecb can adopt ks·sin(ωt)·Cm. In the above description, it is treated as Cm=1, so the amplitude of the current irec1 is also treated as 1, which is the same as the value of the duty cycle drec. When considering that the current irec is a waveform after full-wave rectification, when the phase ωt=π / 2 and 3π / 2 are any, the absolute value ks·|sin(ωt)| of the duty cycle drec and the signal wave drecb both take their respective peak values, and the peak values ​​of the two are consistent (ks=drec).

[0212] When the phase ωt=π / 2 or 3π / 2, |sin(ωt)|=1, Vrec=Vm, and therefore, the duty ratio drec used to make the equivalent DC voltage Vdc constant regardless of the phase ωt takes the following value: ks=drec=(Vdc-Vc) / (Vm-Vc)=(α-R) / (α-1). Therefore, there is a relationship of R=ks+(1-ks)α.

[0213] For example, the fourth circle from the right of the fold line G51 corresponds to ks=0.3, and if α=1.29 is considered, R=1.203. The fourth circle from the left of the fold line G51 corresponds to ks=0.7, and if α=1.29 is considered, R=1.087.

[0214] The voltage utilization rate R is the ratio of the equivalent DC voltage Vdc to the peak value Vm, and it is usually assumed that the peak value Vm is constant. Therefore, a large voltage utilization rate R means a large equivalent DC voltage Vdc. On the other hand, Fig.11 The harmonic amplitudes shown are normalized by the amplitude of the fundamental frequency component (the component of the power supply frequency fs) of the current irec1. Fig.16 The harmonic amplitude Ih shown as an example represents a value when the instantaneous power Pout (=Pdc) increases as the voltage utilization rate R increases.

[0215] The dependence of the harmonic amplitude of the primary-side band harmonic on the voltage utilization factor R when the instantaneous power Pout is maintained at a specified value is obtained as follows. First, in order to normalize the equivalent DC voltage Vdc, the quotient obtained by dividing the harmonic amplitude Ih by the voltage utilization factor R is assumed. Furthermore, considering the reduction effect based on the filter 2, the product of the coefficient G shown in the following formula (6) and the quotient is assumed. The inductance value L of the reactor L4 and the electrostatic capacitance C of the capacitor C2 are introduced.

[0216] [Mathematical formula 6]

[0217] G=[{1-(ωd / ω0) 2} 2 ] -1 / 2 ,ωo 2 =L·C,ω d =2π(fc-fs)…(6)

[0218] The limit value of low voltage higher harmonics is represented by the voltage value detected in the specified LISN. In order to obtain the harmonic amplitude relative to the actual current value flowing rather than the harmonic amplitude relative to the standardized current value, the above product is further multiplied by the DC current Idc. Idc = Pdc / Vm, Pdc = Pout. Therefore, the harmonic amplitude Ih' of the first harmonic side band converted to the actual current value flowing when the instantaneous power Pout is constant is obtained by the following formula (7).

[0219] [Mathematical formula 7]

[0220] Ih′=(Ih / R)·G·(Pout / Vm)…(7)

[0221] Fig.17 Graph showing the dependence of harmonic amplitude Ih' on voltage utilization factor R. For simplicity, the description is made assuming that the voltage step-up ratio α can take any value between 1.29 and 1.47. The voltage step-up ratio α can take a value less than 1.29 or a value greater than 1.47.

[0222] The broken line G61a represents the case where the boost ratio α takes a value of α1a=1.29. The broken line G61b represents the case where the boost ratio α takes a value of α1b=1.41. The broken line G62 represents the case where the boost ratio α takes a value of α2=1.47. In any of the broken lines G61a, G61b, and G62, the circle is Fig.16 The circles shown likewise represent a duty cycle dc (or duty cycle drec) of 0.1 scale.

[0223] As the voltage step-up ratio α increases, the maximum value of the harmonic amplitude Ih' decreases, and the voltage utilization R providing the maximum value increases. In addition, when the harmonic amplitude Ih' having the same value is obtained at different voltage step-up ratios α, the voltage utilization R giving the value increases as the voltage step-up ratio α increases. At R = 1, the harmonic amplitude Ih' takes 1 regardless of the voltage step-up ratio α. At R = α, the harmonic amplitude Ih' takes a value of 0 regardless of the voltage step-up ratio α.

[0224] exist Fig.17 The thresholds TH1, TH2, and TH3 are also recorded. The thresholds TH1, TH2, and TH3 are examples of the limit values ​​in the standard of high-order harmonics in low-voltage systems (TH1>TH2>TH3). The limit values ​​are set depending on the frequency. Fig.11 and Fig.15 As observed, the harmonic amplitude Ih' of the first harmonic side band is the main harmonic of the low-voltage system. Therefore, the following description takes the case where the limit value set for the frequency of the value (fc-fs) is any of the thresholds TH1, TH2, and TH3 as an example.

[0225] When α is any value of 1.29≤α≤1.47, the threshold TH1 is greater than the harmonic amplitude Ih' regardless of the voltage utilization factor R. When the limit value adopts the threshold TH1, as long as 1.29≤α≤1.47 and 1≤R≤α, the harmonic amplitude Ih' is suppressed to be less than the limit value regardless of how the step-up ratio α and the voltage utilization factor R are set.

[0226] The broken line G61a indicates that TH2 ≤ Ih' when J1d ≤ R ≤ J1u. The broken line G62 indicates that TH2 ≤ Ih' when J2d ≤ R ≤ J2u. These can also be explained as follows.

[0227] When the voltage step-up ratio α takes a value of α1a (=1.29), the harmonic amplitude Ih' becomes greater than the threshold value TH2 at the voltage utilization rate R in the range J1. The harmonic amplitude Ih' is less than the threshold value TH2 at the voltage utilization rate R outside the range J1. The lower limit J1d (about 1.04) of the range J1 is greater than 1, and the upper limit J1u (about 1.16) of the range J1 is less than the value α1a.

[0228] When the voltage step-up ratio α takes a value of α2 (=1.47), the harmonic amplitude Ih' becomes greater than the threshold value TH2 at the voltage utilization rate R in the range J2. The harmonic amplitude Ih' is less than the threshold value TH2 at the voltage utilization rate R outside the range J2. The lower limit J2d (about 1.09) of the range J2 is greater than the lower limit J1d, and the upper limit J2u (about 1.24) of the range J2 is greater than the upper limit J1u and less than the value α2.

[0229] When the threshold TH2 is the limit value and the voltage utilization rate R is greater than the upper limit J2u, the harmonic amplitude Ih' is smaller than the limit value even if the voltage step-up ratio α takes any value from the value α1a to the value α2.

[0230] At this time, for any voltage utilization rate R, the voltage step-up ratio α is preferably set to α2. This is because from the perspective of improving efficiency, the equivalent DC voltage Vdc is increased without reducing the duty cycle drec. The increase in the equivalent DC voltage Vdc makes it easier to operate the motor at high speed when the AC load 6 is a three-phase motor, for example.

[0231] The control of setting the voltage utilization rate R to be greater than the upper limit J2u and increasing the voltage step-up ratio α as described above is sometimes temporarily referred to as the first control below. The first control is achieved by increasing the duty ratio dc when the power supply phase is π / 2 and 3π / 2 and increasing the capacitor voltage Vc.

[0232] When the threshold TH2 is the limit value and the voltage utilization rate R is greater than the upper limit J1u and less than the upper limit J2u, the step-up ratio α is preferably α1a. This is because the harmonic amplitude Ih' is less than the limit value for any voltage utilization rate R at this time. As described above, the control of setting the voltage utilization rate R to be greater than the upper limit J1u and less than the upper limit J2u and reducing the step-up ratio α is sometimes temporarily referred to as the second control below. The second control is achieved by setting the duty cycle dc when the power supply phase is π / 2 and 3π / 2 and reducing the capacitor voltage Vc.

[0233] When the threshold TH2 is the limit value and the voltage utilization rate R is greater than or equal to the lower limit J1d and less than the lower limit J2d, the step-up ratio α is preferably α2 because the harmonic amplitude Ih' is less than the limit value for any voltage utilization rate R.

[0234] The control of setting the voltage utilization rate R to be greater than or equal to the lower limit J1d and less than the lower limit J2d and increasing the voltage step-up ratio α as described above is sometimes temporarily referred to as the third control below. The third control is implemented by reducing the duty cycle dc when the power supply phase is π / 2 and 3π / 2 and increasing the capacitor voltage Vc.

[0235] When the threshold TH2 is the limit value and the voltage utilization rate R is less than the lower limit J1d, even if the voltage step-up ratio α is any of the values ​​α1a and α2, the harmonic amplitude Ih' is less than the limit value. At this time, compared with the case where the voltage step-up ratio α is α2, the case where the voltage step-up ratio α is α1a can improve the efficiency of the supercharger 4b, thereby improving the efficiency of the power converter 100.

[0236] The control of setting the voltage utilization rate R to be less than the lower limit J1d and increasing the voltage step-up ratio α as described above is sometimes temporarily referred to as the fourth control below. The fourth control is implemented by reducing the duty cycle dc when the power supply phase is π / 2 and 3π / 2 and reducing the capacitor voltage Vc.

[0237] In the fourth control, the duty cycle dc preferably takes a value smaller than the value dc2. Here, the value dc2 is the value of the duty cycle dc when the voltage utilization rate R takes the lower limit J1d when the voltage step-up ratio α takes the value α2.

[0238] Regarding the value of the duty cycle dc required to obtain the same voltage utilization rate R, the case where the boost ratio α takes the value α1a is larger than the case where the boost ratio α takes the value α2. Therefore, taking the duty cycle dc as a value less than the value dc2 helps to reduce the possibility of the harmonic amplitude Ih' exceeding the limit value. In addition, the reduction of the duty cycle dc helps to improve the efficiency of the power converter 100.

[0239] The broken line G61a indicates that TH3 ≤ Ih' when R ≤ d1a. The broken line G62 indicates that TH3 ≤ Ih' when R ≤ d2. These can also be explained as follows.

[0240] When the voltage step-up ratio α takes a value α1a, the harmonic amplitude Ih' becomes greater than or equal to the threshold value TH3 for the voltage utilization factor R below the lower limit value d1a. For the voltage utilization factor R greater than the lower limit value d1a, the harmonic amplitude Ih' becomes less than the threshold value TH3.

[0241] When the voltage step-up ratio α takes a value of α2, the harmonic amplitude Ih' becomes greater than or equal to the threshold value TH3 for the voltage utilization factor R below the lower limit value d2. For the voltage utilization factor R greater than the lower limit value d2, the harmonic amplitude Ih' becomes less than the threshold value TH3.

[0242] When R≥d1a, the harmonic amplitude Ih' decreases monotonically regardless of the boost ratio α. When α=α1a, R=α1a and Ih'=0, and when α=α2, R=d2 and Ih'>0. Therefore, α1a<d2. d1a<α1a, d1a<d2.

[0243] When the threshold TH3 is the limit value and the voltage utilization rate R is greater than the lower limit value d1a and less than the value α1a, the value α1a is preferably used as the step-up ratio α. This is because the harmonic amplitude Ih' is less than the limit value for any voltage utilization rate R.

[0244] The control of setting the voltage utilization rate R to be greater than the lower limit value d1a and less than the value α1a and reducing the step-up ratio α as described above is sometimes temporarily referred to as the fifth control below. The fifth control is implemented by setting the duty ratio dc when the power supply phase is π / 2 and 3π / 2 and reducing the capacitor voltage Vc.

[0245] Next, the behavior of the harmonic amplitude Ih' with respect to the voltage utilization rate R when the voltage step-up ratio α takes the value α1b=1.41 is examined. The broken line G61b represents this behavior. There is a relationship of α1a<α1b<α2.

[0246] The broken line G61b indicates that TH3 ≤ Ih' when R ≤ d1b. This can also be explained as follows.

[0247] When the voltage step-up ratio α takes a value of α1b, the harmonic amplitude Ih' becomes greater than or equal to the threshold value TH3 for the voltage utilization rate R below the lower limit value d1b. For the voltage utilization rate R greater than the lower limit value d1b, the harmonic amplitude Ih' becomes less than the threshold value TH3.

[0248] like Fig.17 As shown, there is a relationship of d1a<α1a<d1b<d2<α1b<α2. When the boost ratio α is not smaller than the value α1b, the following cases are classified. This is also the case when α1b=d2.

[0249] When the voltage utilization rate R is greater than the lower limit value d1b and less than the lower limit value d2, the voltage step-up ratio α preferably takes the value α1b, because at this time the harmonic amplitude Ih' is less than the limit value for any voltage utilization rate R.

[0250] The control of setting the voltage utilization rate R to be greater than the lower limit value d1b and less than the lower limit value d2 and reducing the step-up ratio α as described above is sometimes temporarily referred to as the sixth control below. The sixth control is implemented by setting the duty ratio dc when the power supply phase is π / 2 and 3π / 2 and reducing the capacitor voltage Vc.

[0251] When the voltage utilization rate R is greater than the lower limit d2, the voltage step-up ratio α is preferably set to α2. This is because from the perspective of improving efficiency, the equivalent DC voltage Vdc is increased without reducing the duty cycle drec. The increase in the equivalent DC voltage Vdc makes it easier to operate the motor at high speed when the AC load 6 is a three-phase motor, for example.

[0252] The control of increasing the voltage utilization factor R and increasing the voltage step-up ratio α as described above is sometimes temporarily referred to as the seventh control below. The seventh control is achieved by increasing the duty ratio dc when the power supply phase is π / 2 and 3π / 2 and increasing the capacitor voltage Vc.

[0253] Hereinafter, a case where the AC load 6 is a three-phase motor will be described.

[0254] <Description of Speed ​​Detection Unit 9>

[0255] The speed detection unit 9 inputs the AC currents Iu, Iv, Iw, and obtains the currents Id, Iq and the rotational angular velocity ωm of the AC load 6. The currents Id, Iq are currents obtained by converting the AC currents Iu, Iv, Iw into a so-called dq axis coordinate system.

[0256] <Description of Control Device 10>

[0257] Fig.18 1 is a block diagram showing an example of a conceptual structure of the control device 10 for controlling the power converter 100 . The control device 10 includes a module 10 a that functions as a control device for the active buffer 4 and a module 10 b that functions as a control device for the inverter 5 .

[0258] The module 10 a includes a current sharing ratio generating unit 11 , a voltage command generating unit 15 , an adder 13 , a chopper control unit 16 , comparators 12 and 14 , and carrier generating units 23 and 24 .

[0259] The module 10 b includes an output voltage command generating unit 31 , calculation units 32 , 33 , comparators 34 , 35 , and a logical OR / logical AND calculation unit 36 ​​.

[0260] The current distribution ratio generating unit 11 is input with the peak value Vm also as the amplitude of the AC voltage Vin, the amplitude Im of the AC current Iin, the command value Vdc* for the equivalent DC voltage Vdc, the command value Vc* for the capacitor voltage Vc, and the power supply angular velocity ω. The peak value Vm, the amplitude Im, and the power supply angular velocity ω are detected by, for example, providing a known detection unit and input to the current distribution ratio generating unit 11. The command values ​​Vdc* and Vc* are input from the voltage command generating unit 15.

[0261] The current sharing ratio generating unit 11 outputs the duty ratios drec, dc, dz and the command value iL* for the current iL (hereinafter also referred to as "current command value"). The current sharing ratio generating unit 11 determines the duty ratios drec, dc, dz so that the equivalent DC voltage Vdc follows the command value Vdc*, and determines the current command value iL* so that the capacitor voltage Vc follows the command value Vc*.

[0262] The voltage command generating unit 15 receives the command values ​​Vd*, Vq*, currents Id, and Iq as inputs to obtain the instantaneous power Pout. The command values ​​Vd* and Vq* are the command values ​​of the voltages Vd and Vq, respectively. The voltages Vd and Vq are voltages obtained by converting the three-phase voltage output by the inverter 5 into the so-called dq axis coordinate system. The currents Id and Iq are currents obtained by converting the alternating currents Iu, Iv, and Iw into the so-called dq axis coordinate system. For example, Pout = Vd*·Id+Vq*·Iq. The voltage command generating unit 15 determines the command values ​​Vdc* and Vc* according to the instantaneous power Pout. The command values ​​Vd* and Vq* are obtained from the output voltage command generating unit 31, and the currents Id and Iq are obtained from the speed detecting unit 9.

[0263] The duty cycle drec and the duty cycle dz are added in the adder 13, and the result (drec+dz) is compared with the carrier C1 in the comparator 12. The carrier C1 is generated by the carrier generator 23, and is a triangular wave having a minimum value of 0 and a maximum value of 1, for example.

[0264] The comparison result of the comparator 12 is output as a switch signal SSc provided to the switch Sc. For example, the comparator 12 outputs a signal activated during a period when the carrier C1 is greater than the value (drec+dz) as the switch signal SSc. The transistor Qc (equivalent switch Sc) is turned on by the activation of the switch signal SSc.

[0265] The chopper control unit 16 receives the peak value Vm, the power supply angular velocity ω (or the AC voltage Vin), and the command value Vc*, and outputs the duty ratio dL based on the current command value iL* according to the inductance Lm of the reactor L4. The technology for determining the duty ratio dL based on the provided current command value iL*, the capacitor voltage Vc, the AC voltage Vin, and the inductance Lm is known, for example, from Japanese Patent No. 5772915 and Japanese Patent No. 5629885. The capacitor voltage Vc is controlled to follow the command value Vc*, so the chopper control unit 16 can be easily realized by referring to Japanese Patent No. 5772915 and Japanese Patent No. 5629885, for example.

[0266] The duty cycle dL is compared with the carrier C3 in the comparator 14. The carrier C3 is generated by the carrier generator 24 and is, for example, a triangular wave having a minimum value of 0 and a maximum value of 1. The comparison result of the comparator 14 is output as a control signal SSL for controlling the opening and closing of the switch SL. For example, the comparator 14 outputs a signal activated during a period when the carrier C3 is less than the duty cycle dL as the control signal SSL. The transistor QL (equivalently the switch SL) is turned on by the activation of the control signal SSL.

[0267] The output voltage command generation unit 31 generates command values ​​Vd*, Vq* and phase voltage commands Vu*, Vv*, Vw*. Fig.18 In the example of , the rotational angular velocity ωm of the AC load 6 and its command value ωm* are input to the output voltage command generating unit 31. The rotational angular velocity ωm is obtained by the speed detecting unit 9, and the command value ωm* is input by an external structure not shown. The output voltage command generating unit 31 generates the command values ​​Vd*, Vq* and the phase voltage commands Vu*, Vv*, Vw* in a manner that reduces the deviation between the rotational angular velocity ωm and its command value ωm* by a known method.

[0268] For example, the output voltage command generating unit 31 receives the rotational angular velocity ωm, the command value ωm*, and the currents Id and Iq, and generates a modulation factor D and a phase of the voltage output by the inverter 5. (Omitted from the diagram). Using the modulation rate D and phase Phase voltage commands Vu*, Vv*, Vw* and command values ​​Vd*, Vq* are generated. This technique can be considered as a combination of the functions of the speed control unit 1010 and the output voltage command unit 1011 in Japanese Patent No. 6721097, for example.

[0269] The duty ratios drec, dz, dc and the phase voltage commands Vu*, Vv*, Vw* are input to the operation unit 32. The operation unit 32 calculates the value (drec+dz+dc·Vx*) (where x represents u, v, w) and outputs it. The duty ratio drec and the phase voltage commands Vu*, Vv*, Vw* are input to the operation unit 33, and the value (drec·(1-Vx*)) is calculated and output.

[0270] The value (drec+dz+dc·Vx*) is compared with the carrier C1 in the comparator 34, and the value (drec·(1-Vx*)) is compared with the carrier C1 in the comparator 35. The comparator 34 outputs a signal that is activated, for example, during a period when the carrier C1 is equal to or greater than the value (drec+dz+dc·Vx*), and the comparator 35 outputs a signal that is activated, for example, during a period when the carrier C1 is equal to or less than the value (drec·(1-Vx*)).

[0271] In this way, the carrier C1 can be used in any of the modules 10a and 10b. Figure 2 The medium carrier wave generating unit 23 is shown to be provided across the boundary between the modules 10 a and 10 b .

[0272] The comparison results of the comparators 34 and 35 are input to the logical OR / logical AND operation unit 36. The logical OR of the comparison results of the comparators 34 and 35 is output as the switching signals SSup, SSvp, SSwp respectively provided to the switching elements Sup, Svp, Swp, and the logical NOT of them is output as the switching signals SSun, SSvn, SSwn respectively provided to the switching elements Sun, Svn, Swn.

[0273] As described above, the technology for generating switching signals SSup, SSvp, SSwp, SSun, SSvn, SSwn based on duty ratios drec, dz, dc and phase voltage instructions Vu*, Vv*, Vw* is well known, so detailed description of the technology is omitted.

[0274] <Differentiation and use of various control methods>

[0275] Fig.19 This is a flowchart illustrating a routine used by the control device 10 to distinguish the control methods of the power converter 100. As described above, the operation of the power converter 100 can be controlled by controlling one or both of the capacitor voltage Vc and the duty cycle dc for controlling the operation of the power converter 100.

[0276] In step S11, it is determined whether the instantaneous power Pout is less than a certain threshold value P1. The threshold value P1 is equivalent to the second threshold value described in (b-3). When the instantaneous power Pout is less than the threshold value P1, the determination result in step S11 is affirmative, and step S14 is executed. In the case where step S14 is executed because the determination result in step S11 is affirmative, it is not necessary to increase the equivalent DC voltage Vdc, and non-boost control is adopted. In step S14, as non-boost control, for example, a continuous switching method or an alternating conduction method is adopted.

[0277] The term "alternating conduction method" is a temporary name in this embodiment for control that alternately provides a non-conduction period with a duty cycle dc of 0 and an on period with a positive duty cycle dc. The alternating conduction method is achieved by controlling one or both of the duty cycle dc and the capacitor voltage Vc, for example.

[0278] The alternating conduction mode includes a half-cycle switching mode. The "half-cycle switching mode" is a control of charging and discharging the instantaneous power Pbuf through the active buffer 4 in each half cycle of the AC voltage Vin. It is introduced in Japanese Patent Publication No. 2021-58002 using Japanese Invention Patent Publication No. 5629885 as an example. In the half-cycle switching mode, the non-conduction period and the conduction period are both one-quarter of the power supply cycle, that is, one-quarter of the cycle of the AC voltage Vin.

[0279] The "continuous switching method" is a control method in which no exclusive period is set in the power supply phase of the AC voltage Vin, but charging and discharging are continuously performed through the active buffer 4. Japanese Patent Application Publication No. 2021-58002 introduces Japanese Patent Application No. 5804167 as an example. In the continuous switching method, for example, the length of the non-conduction period is controlled to be substantially zero.

[0280] The half-cycle switching method and the continuous switching method are advantageous in terms of improving the efficiency of the power converter 100 .

[0281] In the alternating conduction mode, in the first interval where the command value Vdc* of the equivalent DC voltage Vdc is higher than the absolute value of the AC voltage Vin, the duty cycle dc is 0, and the duty cycle drec can be the value obtained by dividing the command value Vdc* of the equivalent DC voltage Vdc by the rectified voltage Vrec. The first interval can be understood as a non-conduction period. In the second interval where the command value Vdc* is less than the absolute value of the AC voltage Vin, the duty cycle drec is 0, and the duty cycle dc is the value obtained by dividing the command value Vdc* by the peak value Vm. The second interval can be understood as a conduction period. This control method is disclosed, for example, in Japanese Patent Gazette No. 2021-58002 (hereinafter temporarily referred to as "the 0th control"). According to the 0th control, regardless of the power supply phase, an equivalent DC voltage Vdc corresponding to the command value Vdc* can be obtained.

[0282] If the equivalent DC voltage Vdc is the same, the half-cycle switching method generally requires a smaller power capacity for the active snubber 4 than the continuous switching method, and the effective value of the current for charging the capacitor C4 is smaller, so it is advantageous from the viewpoint of improving the efficiency of the partial load. By adopting the 0th control, the capacitor C4 is charged without switching operation in the booster 4b, so it can be expected that the efficiency of the partial load will be further improved.

[0283] In step S11, if it is determined that the instantaneous power Pout is greater than a certain threshold value P1, the determination result in step S11 is negative and the voltage step-up control is performed. If the determination result in step S11 is negative, the control method of the power converter 100 is allocated according to the determination results in steps S12 and S13.

[0284] In steps S12 and S13, a limit threshold TH for the harmonic amplitude Ih' is introduced as a judgment criterion. In the example of this embodiment, the limit threshold TH corresponds to the above-mentioned thresholds TH1, TH2, and TH3 (see Fig.17 )

[0285] Step S12 is performed before executing step S13. In step S12, it is determined whether the harmonic amplitude Ih' is always smaller than the limit value when the equivalent DC voltage Vdc is greater than the peak value Vm and smaller than the capacitor voltage Vc.

[0286] based on Fig.17 For example, when TH=TH1, the judgment result in step S12 is positive. In this case, the control method of the power converter 100 can be selected from a perspective other than the harmonic amplitude Ih', such as from a perspective of improving efficiency or from a perspective of improving the voltage utilization factor R, and step S27 described later is executed, and the differentiated use of the control method is terminated.

[0287] based on Fig.17 For example, when TH=TH2 or TH=TH3, the judgment result in step S12 is negative, and step S13 is executed.

[0288] In step S13, it is determined whether the harmonic amplitude Ih' when the equivalent DC voltage Vdc is at a peak value Vm, that is, when the voltage utilization factor R is 1, is less than the limit value. Fig.17 For example, when TH=TH2, the judgment result in step S13 is affirmative, and when TH=TH3, the judgment result in step S13 is negative.

[0289] If the determination result of step S13 is affirmative, as described in the description when threshold value TH2 is the limit value, the control of power converter 100 may adopt any of the first control, the second control, the third control, and the fourth control.

[0290] If the judgment result of step S13 is positive, step S15 is executed. Step S15 judges whether the equivalent DC voltage Vdc is greater than the upper limit J2u times of the peak value Vm. Fig.19 In the above, the voltage utilization rate R is used and the determination criterion of step S15 is omitted. If the determination result of step S15 is positive, the first control is adopted in step S16. Step S16 is executed to end the use of the control method.

[0291] If the judgment result of step S15 is negative, step S17 is executed. In step S17, it is judged whether the equivalent DC voltage Vdc is greater than the upper limit J1u times of the peak value Vm. Fig.19 In the above, the voltage utilization rate R is used and the determination criterion of step S17 is omitted.

[0292] When step S17 is executed, R≤J2u is established by the judgment of step S15. Therefore, when the judgment result of step S17 is affirmative, the second control is adopted in step S18. Step S18 is executed to end the use of the control method.

[0293] If the judgment result of step S17 is negative, step S19 is executed. In step S19, it is judged whether the equivalent DC voltage Vdc is less than the lower limit J1d times of the peak value Vm. Fig.19 In the above, the voltage utilization rate R is used and the determination criterion of step S19 is omitted. If the determination result of step S19 is positive, the fourth control is adopted in step S20. Step S20 is executed to end the use of the control method.

[0294] If the judgment result of step S19 is negative, step S21 is executed. In step S21, it is judged whether the equivalent DC voltage Vdc is greater than the lower limit J2d times of the peak value Vm. Fig.19In the above, the voltage utilization rate R is used and the determination criterion of step S21 is omitted.

[0295] When step S21 is executed, J1d≤R is established by the determination in step S19. Therefore, when the determination result in step S21 is affirmative, the third control is adopted in step S22. Step S22 is executed to end the differentiated use of the control method.

[0296] If the result of the judgment in step S21 is negative, J2d≤R≤J1u is satisfied. Adopting such a voltage utilization ratio R will result in TH2≤Ih', which is not preferable. Therefore, in step S30, the equivalent DC voltage Vdc is reset. Step S30 is executed to end the differentiated use of the control method.

[0297] If the determination result of step S13 is negative, as described in the description when the threshold value TH3 is the limit value, any of the fifth control, the sixth control, and the seventh control may be adopted.

[0298] If the result of step S13 is negative, step S23 is executed. In step S23, it is determined whether the equivalent DC voltage Vdc is less than the lower limit value d1 times the peak value Vm. The lower limit value d1 is a value representing the above lower limit values ​​d1a and d1b. Fig.19 In the above, the voltage utilization rate R is used and the judgment criterion of step S23 is omitted.

[0299] If the result of the determination in step S23 is positive, TH3 ≤ Ih' is established, which is not preferable. Therefore, in step S30, the equivalent DC voltage Vdc is reset. Step S30 is executed to end the use of the control method.

[0300] If the result of the determination in step S23 is negative, step S24 is executed. Step S24 determines whether the equivalent DC voltage Vdc is greater than or equal to the lower limit value d2 times of the peak value Vm. Fig.19 In the above, the voltage utilization rate R is used and the determination criterion of step S24 is omitted. If the determination result of step S24 is positive, the seventh control is adopted in step S25. Step S25 is executed to end the use of the control method.

[0301] If the judgment result of step S24 is negative, step S26 is executed to adopt the fifth control or the sixth control. When step S24 is executed, d1<R has been determined by the judgment of step S23. Therefore, if the judgment result of step S24 is negative, d1<R<d2. In this case, the fifth control or the sixth control is selected depending on the magnitude relationship between the value α1 and the lower limit value d2. Fig.19In FIG. 1 , this selection is shown as step S26 described as “fifth and sixth control.” Step S26 is executed to end the differentiated use of the control method.

[0302] When the determination result of step S12 is positive, any of the first to seventh controls described above may be adopted. Fig.19 In the embodiment, this selection is shown as step S27 expressed as "first control to seventh control". Step S27 is executed to end the selection of the control methods.

[0303] <Fourier coefficients of pulse waveform Srecb>

[0304] Below, we will show an example to find Figure 5 Calculation of the Fourier coefficients of the pulse waveform Srecb shown in FIG. The pulse waveform Srecb is an odd function with a period of 2π and an average value of 0. Therefore, the phase ωt of the AC voltage Vin is expressed as the phase θ, which is expressed by equations (8) and (9). In equation (9), according to the symmetry of the waveform, the integration interval is 0 to π / 2.

[0305] [Mathematical formula 8]

[0306]

[0307] [Mathematical formula 9]

[0308]

[0309] In the phase θ1~θ k+1 (θ k+1 is an even number less than π / 2), the carrier wave Cp is equal to the signal wave drecb. Figure 5 Example in θ k+1 =π / 2. Phase θ1~θ k+1 For example, it is obtained by numerical calculation.

[0310] According to the phase θ1~θ k+1 The Fourier coefficients of the pulse waveform Srecb are obtained by using equation (9) to analyze the harmonic current generated by the switching action of the switch Sc.

[0311] <Modulation rate ks that provides a maximum value of the harmonic amplitude Ih'>

[0312] It can be considered that the signal wave drecb is modulated by the fundamental component of the converter side carrier frequency of the pulse waveform Srecb to generate harmonics. The harmonic amplitude Ih of the primary side band harmonic is expressed by formula (10). The amplitude Π0 is introduced in formula (10). The amplitude Π0 is the average value of the fundamental amplitude of the converter side carrier frequency of the pulse waveform Srecb over one cycle (2π / ω) of the phase ωt. In this way, since the carrier frequency is understood as the average value, cos(2π·fc·t) in formula (10) represents the fundamental component of the square wave signal with an amplitude of 1.

[0313] [Formula 10]

[0314] Ih=∏0·cos(2π·fc·t)·(4 / π)cos(2π·fs·t)…(10)

[0315] The following describes how to calculate the amplitude Π0 and then the modulation rate ks that provides the extreme value of the harmonic amplitude Ih.

[0316] Each of the pulse waveforms Srecb is a square wave, and has a time ratio d that determines the width of the square wave relative to the carrier cycle (1 / fc) that is the cycle of the carrier waves Cp and Cn. The converter side carrier frequency component of each square wave depends on the time ratio d of each square wave.

[0317] The width of the square wave depends on the phase of the square wave. Figure 5 In general, the width of the square wave taking the value 1 in the phase θ1~θ2 is narrower than the width of the square wave taking the value 1 near the phase π / 2.

[0318] Fig. 20 is in phase (θ j +θ j+1 ) / 2 is the center of the carrier cycle, indicating that the phase θ j At the rising point, at the phase θ j+1 The falling pulse waveform Π j Pulse waveform ∏ j The time ratio d j It is obtained by expression (11).

[0319] [Mathematical formula 11]

[0320] d j =(θ j+1 -θ j ) / 2π…(11)

[0321] By finding the Fourier coefficients of the pulse waveform Πj, the amplitude Πm of the converter-side carrier frequency component of the pulse waveform Πj is found by equation (12): j .

[0322] [Mathematical formula 12]

[0323] ∏m j =(2 / π)sin(d j ·π)…(12)

[0324] Fig.21 is the time ratio d j With amplitude Πm j Amplitude Πm j Relative to time ratio d j , with d j = 1 / 2 is the axis and the time ratio is d j symmetry.

[0325] Amplitude Πm j It depends on the phase of the signal wave drecb. Therefore, the amplitude Π0 as its average value uses the time ratio d in one cycle of the signal wave drecb. j The average value d^ is expressed by equation (13) similar to equation (12).

[0326] [Mathematical formula 13]

[0327] ∏0=(2 / π)sin(d^·π)…(13)

[0328] However, according to the above amplitude Πm j Relative to time ratio d j When the symmetry of is used to calculate the average value d^, when 1 / 2≤dj≤1, ​​the value (1-d j ) to replace the time ratio d j .

[0329] The signal wave drecb is a sine wave, and its waveform J introduces a phase θ so that equation (14) holds.

[0330] [Mathematical formula 14]

[0331] J(θ)=ks·sin(θ)…(14)

[0332] Fig. 22 The modulation rate ks is used as a parameter to represent the phase and time ratio d of the signal wave drecb j Or value (1-d j ) is a graph showing the relationship between the time ratio and the time ratio. j When it is 1 / 2 or more, the value (1-d j ) to replace the time ratio d j .

[0333] Curves G71, G72, G73, G74, G75, G76, and G77 represent the cases where the modulation rate ks takes values ​​of 0.2, 0.4, 0.5, q1, q2, q3, and 1, respectively.

[0334] Import time ratio d j The phase Θ of the signal wave drecb when the value is 1 / 2 (0<Θ<π / 2). When the modulation rate ks is less than 1 / 2, there is no phase Θ. The larger the modulation rate ks is, the smaller the phase Θ is.

[0335] If the case of θ=θ is considered, equation (15) holds.

[0336] [Mathematical formula 15]

[0337] ks=(1 / 2) / sin(Θ)…(15)

[0338] The phase θ does not exist when the curves G71 and G72 do not take the value 1 / 2. In the curve G73, θ=90 degrees. In the curve G74, θ=75 degrees. In the curve G75, θ=60 degrees. In the curve G76, θ=45 degrees. In the curve G77, θ=30 degrees (refer to equation (15)).

[0339] Fig.23 is the phase-time ratio d of the signal wave drecb when θ=π / 3 (60 degrees). j Or value (1-d j ) of the relationship (in Fig. 22 The signal wave drecb is a sine wave. According to its symmetry, the time ratio d is obtained in the phase range of 0 to π / 2. j Or value (1-d j ) is taken, and the average value d^ is obtained by dividing the integral value by π / 2.

[0340] Based on the above integral value, the average value d^ is calculated by formula (16).

[0341] [Formula 16]

[0342] d^=(2 / π){(1 / 2) / sin(Θ))·(1-2cos(Θ))+(π / 2-Θ)}…(16)

[0343] The phase θ that maximizes the average value d^ is the phase θ (<π / 2) at which equation (16) is differentiated by the phase θ to become 0. Differentiation with respect to the phase θ is represented by the symbol Δ / Δθ, yielding equation (17).

[0344] [Mathematical formula 17]

[0345] Δd^ / ΔΘ=(1 / 2)(-cos(Θ) / sin 2 (Θ))(1-2cos((Θ))…(17)

[0346] According to formula (17), the phase θ that maximizes the average value d^ is π / 3, and the corresponding modulation rate ks is (Refer to formula (16)).

[0347] The carrier period is shown Fig.21 The relationship between the time ratio and the pulse width is established regardless of the size of the period, and it is clear that the phase Θ (<π / 2) that maximizes the average value d^ sets the value sin(d^·π) to the maximum. Therefore, the amplitude ∏0 represented by equation (13) is also the maximum when Θ = π / 3, and at the modulation rate When the harmonic amplitude Ih reaches the maximum value (refer to formula (10)).

[0348] According to the above description, the modulation rate that provides the maximum value of the harmonic amplitude Ih is However, when the equivalent DC voltage Vdc is made constant regardless of the phase ωt, the relationship R = ks + (1-ks) α exists, so the voltage utilization factor R that provides the maximum value of the harmonic amplitude Ih increases as the voltage step-up ratio α increases. This is manifested as Fig.16 In FIG. 1 , the value of the voltage utilization rate R providing the local maximum value of the broken line G52 is larger than the value of the voltage utilization rate R providing the local maximum value of the broken line G51 .

[0349] The duty cycle drec is equal to the modulation rate ks and takes the maximum value when θ=π / 2. From the perspective of reducing the harmonic amplitude Ih independently of the value of the step-up ratio α, the maximum value of the duty cycle drec is preferably less than or greater than And is less than 1.

[0350] When the duty ratio dz in the boost control is 0, the maximum value of the value obtained by subtracting the duty ratio dc from 1 is preferably greater than 0 and less than or greater than And is less than 1.

[0351] From the viewpoint of increasing the equivalent DC voltage Vdc, it is preferred that the maximum value of the duty ratio drec is less than From the viewpoint of improving the efficiency of the power converter 100, it is preferred that the maximum value of the duty cycle drec is greater than And is less than 1.

[0352] The selection of such duty ratios drec and dc is not only for the purpose of reducing the harmonic amplitude Ih, but also for the purpose of reducing the harmonic amplitude Ih'. Indeed, according to equation (7), the voltage utilization rate R that provides the maximum value of the harmonic amplitude Ih' at a certain step-up ratio α is greater than the voltage utilization rate R that provides the maximum value of the harmonic amplitude Ih at the same step-up ratio α. However, for example, when the duty ratio drec takes the value The value of the harmonic amplitude Ih' is relative to the value when the duty cycle drec is The increase rate of the harmonic amplitude Ih at this time is less than 1%, which can be ignored in actual control.

[0353] Reference Fig.17 and Fig.19 It can be seen that the first control, the second control, the fifth control, the sixth control, and the seventh control are all equivalent to the maximum value of the duty cycle drec being less than Similarly, it can be seen that the third control and the fourth control are equivalent to the maximum value of the duty cycle drec being greater than And it is less than 1.

[0354] D. Function and Configuration of Filter 2

[0355] The filter 2 may also be arranged closer to the single-phase AC power source 1 than the converter 3 relative to the single-phase AC power source 1. For example, the reactor L2 is arranged between one of the two output terminals of the single-phase AC power source 1 and the converter 3. The capacitor C2 is connected in series with the reactor L2 between the two output terminals of the single-phase AC power source 1.

[0356] Fig.24 FIG. 1 is a circuit diagram partially showing a power converter 100 in which the filter 2 is arranged as described above. The configuration of the power converter 100 is similar to that of FIG. 1 except for the arrangement of the filter 2. Figure 1 The structure is the same as illustrated in .

[0357] Reference Fig.18 The basic frequency of the boost chopper of the supercharger 4b for chopping the current iL adopts the frequency of the carrier C3. In addition, the inverter side carrier frequency is the frequency of the carrier C1. For example, the frequency of the carrier C3 is set higher than the frequency of the carrier C1. The basic frequency of the switching action of the transistor Qc in the switching circuit 4a adopts the frequency of the carrier C1.

[0358] Furthermore, the fact that the cutoff frequency of the filter 2 is lower than the frequency of the carrier C1 contributes to not only preventing the ripple current generated by the switching action of the inverter 5 from being propagated to the single-phase AC power supply 1, but also preventing any or both of the ripple current generated by the switching action in the switching circuit 4a and the ripple current generated by the switching action in the booster 4b from being propagated to the single-phase AC power supply 1. This contribution does not depend on whether the filter 2 is Figure 1 That configuration is still like Fig.24 Configure it like that.

[0359] Although the embodiments have been described above, it should be understood that various modifications of the modes and details can be made without departing from the spirit and scope of the claims. The various embodiments and modifications described above can be combined with each other.

[0360] Description of Reference Numerals

[0361] 2: filter; 3: converter; 4: active buffer; 4a: switching circuit; 4b: booster; 5: inverter; 7: DC link; 100: power converter; Idc: DC current; Ih': amplitude; J1, J2: range; J1d, J2d: lower limit; J1u, J2u: upper limit; PL, Pbuf, Pc, Pdc, Pin, Pout, Prec: instantaneous power; Qc: transistor; R: voltage utilization; Sc: switch; TH1, TH2, TH3: threshold; Vc: capacitor voltage; Vdc: equivalent DC voltage; Vin: AC voltage; Vm: peak value; Vrec: rectified voltage; d1, d1a, d1b, d2: lower limit; dc, drec: duty cycle; iL: current; α: boost ratio; α1, α1a, α1b, α2: value.

Claims

1. A method for controlling a power converter, which is a method for controlling a power converter (100), wherein: The power converter (100) comprises: DC link (7); A converter (3) which rectifies a single-phase AC voltage (Vin), converts a first AC power based on the AC voltage into a DC power, and outputs a first instantaneous power (Pin); An active buffer (4) exchanges power with the DC link (7) and performs buffering with a second instantaneous power (Pbuf); as well as an inverter (5) which converts the third instantaneous power (Pdc) input from the DC link (7) into the second AC power (Pout) and outputs the second AC power, The active buffer (4) has: a booster (4b) for boosting a rectified voltage (Vrec) obtained by rectifying the AC voltage (Vin) to generate a first voltage (Vc); and a switch (4a, Sc, Qc) for intermittently applying the first voltage (Vc) from the booster (4b) to the DC link, The switch (4a, Sc, Qc) is turned on with a first duty cycle (dc), Controlling either or both of the first duty cycle (dc) and the first voltage (Vc): When the second AC power (Pout) is greater than a second threshold value smaller than the first threshold value, controlling the equivalent DC voltage (Vdc) to be higher than the peak value (Vm) of the rectified voltage (Vrec) and less than the first voltage (Vc); The equivalent DC voltage (Vdc) when the second AC power (Pout) takes a first value greater than the first threshold is made higher than the equivalent DC voltage (Vdc) when the second AC power (Pout) takes a second value greater than the second threshold and smaller than the first threshold, The equivalent DC voltage (Vdc) is applied to the DC link (7) and is a DC voltage obtained by dividing the third instantaneous power (Pdc) by a DC current (Idc) which is an average value of the current flowing through the inverter (5).

2. The control method of the power converter according to claim 1, wherein: The active buffer (4) inputs a fourth instantaneous power (PL) as a part of the first instantaneous power (Pin) from the DC link (7), outputs a fifth instantaneous power (Pc) to the DC link (7), and buffers the second instantaneous power (Pbuf=Pc-PL). The third instantaneous power (Pdc) is the sum of the sixth instantaneous power (Prec) obtained by subtracting the fourth instantaneous power (PL) from the first instantaneous power (Pin) and the fifth instantaneous power (Pc), The power ratio is a ratio (Prec / Pin) of the sixth instantaneous power (Prec) to the first instantaneous power (Pin), The power ratio when the second AC power (Pout) takes the first value is made smaller than the power ratio when the second AC power (Pout) takes the second value.

3. The control method of the power converter according to claim 1, wherein: When the second AC power (Pout) is greater than the second threshold, The maximum value of the second duty ratio (drec), which is a value obtained by subtracting the first duty ratio (dc) from 1, is greater than 0 and less than or greater than And is less than 1.

4. The control method of the power converter according to claim 3, wherein: When the second AC power (Pout) is greater than the second threshold, The maximum value of the second duty cycle (drec) is greater than 0 and less than 5. The control method of the power converter according to claim 4, wherein: The voltage step-up ratio (α) is a value obtained by dividing the first voltage (Vc) by the peak value (Vm). The voltage utilization ratio (R) is the value obtained by dividing the equivalent DC voltage by the peak value (Vm). The voltage step-up ratio (α) can also take any value from a third value (α1) to a fourth value (α2) larger than the third value. When the second AC power (Pout) is greater than the second threshold: When the voltage step-up ratio (α) takes the third value (α1), for the voltage utilization rate (R) within a first range (J1) greater than 1, the amplitude (Ih') of the harmonics relative to the AC voltage (Vin) generated by the switching action of the switch (4a, Sc, Qc) is greater than a predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the first range (J1), the amplitude (Ih') of the harmonics is less than the predetermined threshold value (TH2); When the voltage step-up ratio (α) takes the fourth value (α2), for the voltage utilization rate (R) within a second range (J2) greater than 1, the amplitude (Ih') of the harmonic is greater than the predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the second range (J2), the amplitude (Ih') of the harmonic is less than the predetermined threshold value (TH2); When the voltage utilization rate (R) is greater than the upper limit (J2u) of the second range, the voltage step-up ratio (α) adopts the fourth value (α2).

6. The control method of the power converter according to claim 4, wherein: The voltage step-up ratio (α) is a value obtained by dividing the first voltage (Vc) by the peak value (Vm). The voltage utilization ratio (R) is the value obtained by dividing the equivalent DC voltage by the peak value (Vm). The voltage step-up ratio (α) can also take any value from a third value (α1) to a fourth value (α2) larger than the third value. When the second AC power (Pout) is greater than the second threshold: When the voltage step-up ratio (α) takes the third value (α1), for the voltage utilization rate (R) within a first range (J1) greater than 1, the amplitude (Ih') of the harmonics relative to the AC voltage (Vin) generated by the switching action of the switch (4a, Sc, Qc) is greater than a predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the first range (J1), the amplitude (Ih') of the harmonics is less than the predetermined threshold value (TH2); When the voltage step-up ratio (α) takes the fourth value (α2), for the voltage utilization rate (R) within a second range (J2) greater than 1, the amplitude (Ih') of the harmonic is greater than the predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the second range (J2), the amplitude (Ih') of the harmonic is less than the predetermined threshold value (TH2); When the voltage utilization rate (R) is greater than an upper limit (J1u) of the first range and is less than an upper limit (J2u) of the second range (J2), the voltage step-up ratio (α) takes the third value (α1).

7. The control method of the power converter according to claim 4, wherein: The voltage step-up ratio (α) is a value obtained by dividing the first voltage (Vc) by the peak value (Vm). The voltage utilization ratio (R) is the value obtained by dividing the equivalent DC voltage by the peak value (Vm). The voltage step-up ratio (α) can also take any value from a third value (α1) and a fourth value (α2) greater than the third value (α1a; α1b). When the second AC power (Pout) is greater than the second threshold: When the voltage step-up ratio (α) takes the third value (α1a; α1b), for the voltage utilization rate (R) below the first lower limit value (d1) greater than 1, the amplitude (Ih') of the harmonics with respect to the AC voltage (Vin) generated by the switching action of the switch (4a, Sc, Qc) is greater than a predetermined threshold value (TH3), and for the voltage utilization rate (R) greater than the first lower limit value (d1a; d1b), the amplitude (Ih') of the harmonics is less than the predetermined threshold value (TH3); When the voltage step-up ratio (α) takes the fourth value (α2), for the voltage utilization rate (R) below the second lower limit value (d2) higher than the first lower limit value (d1a; d1b), the amplitude (Ih') of the harmonic is greater than the predetermined threshold value (TH3), and for the voltage utilization rate (R) greater than the second lower limit value (d2), the amplitude (Ih') of the harmonic is less than the predetermined threshold value (TH3); When the third value (α1b) is greater than or equal to the second lower limit value (d2), and when the voltage utilization rate (R) is greater than the first lower limit value (d1b) and less than the second lower limit value (d2), the voltage step-up ratio (α) adopts the third value (α1b); When the third value (α1a) is smaller than the second lower limit value (d2), and when the voltage utilization rate (R) is greater than the first lower limit value (d1a) and smaller than the third value (α1), the boost ratio (α) adopts the third value (α1a).

8. The control method of the power converter according to claim 7, wherein: When the third value (α1b) is equal to or greater than the second lower limit value (d2), and when the voltage utilization rate (R) is greater than the second lower limit value (d2), the voltage step-up ratio (α) adopts the fourth value (α2).

9. The control method of the power converter according to claim 3, wherein: When the second AC power (Pout) is greater than the second threshold, The maximum value of the second duty cycle (drec) is Large and less than 1.

10. The control method of the power converter according to claim 9, wherein: The voltage step-up ratio (α) is a value obtained by dividing the first voltage (Vc) by the peak value (Vm). The voltage utilization ratio (R) is the value obtained by dividing the equivalent DC voltage by the peak value (Vm). The voltage step-up ratio (α) can also take any value from a third value (α1) to a fourth value (α2) larger than the third value. When the second AC power (Pout) is greater than the second threshold: When the voltage step-up ratio (α) takes the third value (α1), for the voltage utilization rate (R) within a first range (J1) greater than 1, the amplitude (Ih') of the harmonics relative to the AC voltage (Vin) generated by the switching action of the switch (4a, Sc, Qc) is greater than a predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the first range (J1), the amplitude (Ih') of the harmonics is less than the predetermined threshold value (TH2); When the voltage step-up ratio (α) takes the fourth value (α2), for the voltage utilization rate (R) within a second range (J2) greater than 1, the amplitude (Ih') of the harmonic is greater than the predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the second range (J2), the amplitude (Ih') of the harmonic is less than the predetermined threshold value (TH2); When the voltage utilization rate (R) is equal to or greater than a lower limit (J1d) of the first range and less than a lower limit (J2d) of the second range (J2), the voltage step-up ratio (α) adopts the fourth value (α2).

11. The control method of the power converter according to claim 9, wherein: The voltage step-up ratio (α) is a value obtained by dividing the first voltage (Vc) by the peak value (Vm). The voltage utilization ratio (R) is the value obtained by dividing the equivalent DC voltage by the peak value (Vm). The voltage step-up ratio (α) can also take any value from a third value (α1) to a fourth value (α2) larger than the third value. When the second AC power (Pout) is greater than the second threshold: When the voltage step-up ratio (α) takes the third value (α1), for the voltage utilization rate (R) within a first range (J1) greater than 1, the amplitude (Ih') of the harmonics relative to the AC voltage (Vin) generated by the switching action of the switch (4a, Sc, Qc) is greater than a predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the first range (J1), the amplitude (Ih') of the harmonics is less than the predetermined threshold value (TH2); When the voltage step-up ratio (α) takes the fourth value (α2), for the voltage utilization rate (R) within a second range (J2) greater than 1, the amplitude (Ih') of the harmonic is greater than the predetermined threshold value (TH2), and for the voltage utilization rate (R) outside the second range (J2), the amplitude (Ih') of the harmonic is less than the predetermined threshold value (TH2); When the first duty cycle (dc) takes the fifth value and the voltage step-up ratio (α) takes the fourth value (α2), the voltage utilization rate (R) takes the lower limit (J1d) of the first range, When the voltage utilization rate (R) is less than the lower limit (J1d) of the first range, the first duty ratio adopts a value less than the fifth value, and the voltage step-up ratio (α) adopts the third value (α1).

12. The control method of the power converter according to any one of claims 1 to 11, wherein: The supercharger (4b) has a boost chopper. The step-up chopper is used to chop the current (iL) input to the step-up chopper using a frequency higher than the frequency of a carrier wave used in the switching operation of the inverter (5).

13. The control method of the power converter according to claim 12, wherein: The power converter (100) further includes a filter (2) having a cutoff frequency lower than the frequency of the carrier. The AC voltage (Vin) is input to the converter (3) via the filter (2).

14. The control method of the power converter according to claim 12, wherein: The power converter (100) further includes a filter (2) having a cutoff frequency lower than the frequency of the carrier. The converter (3) outputs the first instantaneous power (Pin=Prec+PL) via the filter (2).

15. The control method of the power converter according to any one of claims 1 to 11, wherein: The supercharger (4b) has a boost chopper. The step-up chopper chops a current (iL) input to the step-up chopper using a frequency higher than a frequency at which the switch (4a, Sc, Qc) performs a switching operation.

16. The control method of the power converter according to claim 15, wherein: The power converter (100) further includes a filter (2) having a cutoff frequency lower than the frequency at which the switch (4a, Sc, Qc) performs a switching operation. The AC voltage (Vin) is input to the converter (3) via the filter (2).

17. The control method of the power converter according to claim 15, wherein: The power converter (100) further includes a filter (2) having a cutoff frequency lower than the frequency at which the switch (4a, Sc, Qc) performs a switching operation. The converter (3) outputs the first instantaneous power (Pin=Prec+PL) via the filter (2).

18. The control method of a power converter according to any one of claims 1 to 11, wherein: When the first duty cycle (dc) is controlled and the second AC power is smaller than the second threshold value, any of the following controls is adopted: Controlling to alternately set a non-conduction period in which the first duty ratio (dc) is 0 and a conduction period in which the first duty ratio (dc) is positive; and Another control in which the length of the non-conduction period is substantially zero.

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