A mask plate for etching square array patterns and a method for etching square array patterns using the same

Abstract

This invention discloses a mask for etching a square array pattern and a method for etching the square array pattern using the mask. The dry etching method of this invention avoids the use of photoresist or polar solvents, improves the compatibility of MEMS processes, and enables more high-performance new thin films to be applied in microelectronic devices. The array pattern made using the layout etching method of this invention is compatible with any MEMS manufacturing plant, and the alignment marks of the substrate and mask are compatible with the first layer circuit wiring process, saving manufacturing costs.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, specifically relating to a mask for etching a square array pattern and a method for etching a square array pattern using the mask. Background Technology

[0002] Etching is a crucial process in semiconductor device and integrated circuit manufacturing, and a vital means of patterning integrated circuit devices. Typically, etching follows photolithography, transferring the device structure pattern created by photolithography onto a lower substrate. Simply put, photolithography first reacts the photoresist under light or laser exposure, revealing the pattern to be removed after immersion in a developing solution. Then, etching removes the areas of the pattern not covered by photoresist, followed by the removal of the photoresist itself. Etching includes wet etching and dry etching. Wet etching uses various etching solutions to remove the pattern protected by the photoresist through immersion; while dry etching utilizes specialized etching techniques, including reactive ion etching (RIE), inductively coupled plasma etching (ICP), and ion beam etching (IBE).

[0003] The etching methods described above are commonly used strategies in semiconductor device and integrated circuit manufacturing. However, with the continuous emergence of high-performance new materials, challenging problems are constantly being posed to MEMS manufacturing processes. This is because the physicochemical properties of new materials often cannot be fabricated using existing MEMS technologies (for example, some materials are easily corroded by photoresists or polar solvents). Therefore, process incompatibility has become a barrier restricting the application of new materials in microelectronic chips. For example, halide perovskite materials, which have attracted global attention in recent years due to their suitable band gap, high carrier mobility, high absorption coefficient, low exciton binding energy, and long carrier lifetime, have become a new generation of optoelectronic functional materials with quantum dot and nanowire structures. They have shown excellent performance in light-emitting diodes, photosensors, and memristors, but they are easily corroded by polar solutions (water, ethanol, acetone, photoresist, etc.). Another example is MnBi2Te4 material, an antiferromagnetic topological insulator, which possesses exotic states such as quantum anomalous Hall insulator, axion insulator, and Weyl half-metal. It is attractive not only in basic research but also has great potential in practical applications. However, this functional material is easily corroded by polar solvents. With the development of technology, the number and types of this type of new material are becoming increasingly diverse. To avoid contact with solvents of the same polarity, photolithography and wet etching methods must be ruled out first, so only dry etching can be used. However, a mask is required to pattern the material by masking.

[0004] Typically, a perforated photomask has a shielded and protected portion that needs to be patterned, while the exposed portion is the part to be removed. A key characteristic is that the non-perforated portion of the photomask must have a continuous pattern; that is, the shielded and protected portion must have a continuous pattern. Conversely, if the perforated portion has a continuous pattern, but the shielded and protected portion has a discontinuous pattern, such a photomask design is not feasible. Based on this background, this invention proposes a design method for etching patterns on a square array photomask and a method for etching patterns on a square array photomask using this method. Summary of the Invention

[0005] The purpose of this invention is to provide a mask for etching a square array pattern, and the second objective of this invention is to provide a method for etching a square array pattern using the mask.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0007] A mask for etching a square array pattern, wherein the number of etched square array points is N*N, the size of the point array is an a*a square, and the resolution is b.

[0008] The mask includes a first layer layout and a second layer layout;

[0009] The first layer layout is used to fabricate the lower-layer circuitry for various applications of alignment markers and functional thin films, including:

[0010] 1) Functional thin film and circuit area, and blank area, wherein the blank area is the layout area for drawing other leads and pads of the circuit, and the functional thin film and circuit area (purple area) is a square centered at the layout center (0,0) with a side length of N*b;

[0011] 2) Alignment markers for the etching array are placed at the four corners outside the functional thin film and circuit area. The center position of the alignment marker is c away from the center position (0, 0) of the layout, where c > Nb / 2. 1 / 2 The angle between the adjacent lines connecting the center of the map and the centers of the four counterpoints is 90°, and the etched counterpoint layer structure can range from a cross shape at the level of hundreds of micrometers to a cross shape at the level of a few micrometers.

[0012] 3) Set in the first layer version Figure 4The corner alignment markers are used for alignment between the mask and the substrate. These markers have a cross-shaped structure and a multi-precision layer design. The size of the cross can range from thousands of micrometers to micrometers. The next layer is placed in the blank corners of the previous layer. The alignment marker layer is determined according to the precision of the etching pattern. For example, if the pattern precision is hundreds of micrometers, the alignment marker cross can be drawn from thousands of micrometers to tens of micrometers. The first layer of the pattern has a cross at the thousands of micrometers (millimeters) level, which can be used to initially determine the position between the mask and the substrate with the naked eye. The second layer has a cross at the hundreds of micrometers level, which can be determined with an optical microscope. The third layer has a cross at the tens of micrometers level. The fourth layer has a cross at the several micrometers level. And so on, according to the increasing precision layer, the cross of each layer is located in the blank corners of the previous layer.

[0013] The second layer pattern is used to fabricate an etching mask, including:

[0014] 4) Includes a cutout area and a mask area, which correspond to the functional thin film and circuit area and the blank area of ​​the first layer layout, respectively; the cutout area is the etched area mask area layout: the etched mask area layout is a grid stripe structure, wherein each stripe is N*b in length and a in width, with a total of N stripes, and the center of the N stripes is the layout center (0,0);

[0015] 5) Etching alignment marks for the etching array are placed at the four corners of the etching mask area, consistent with the etching alignment marks of the first layer layout, for positional alignment between the etching area of ​​the mask and the substrate.

[0016] 6) Four-corner alignment marks: Consistent with the four-corner alignment marks of the first layer layout, used for direct alignment of the mask and the substrate.

[0017] A method for etching a square array pattern using a mask for etching a square array pattern includes the following steps:

[0018] S1: Utilizing the first layer of the map:

[0019] S11: Fabricate the circuitry of the lower layer of the functional thin-film array region on the substrate, and also graphically represent each alignment mark;

[0020] S12: After the lower layer circuit and alignment mark patterning of the array points are completed, a functional thin film is deposited on the upper layer of the circuit. The functional thin film can be deposited by thermal evaporation, spin coating, or other processes. The specific method is set according to the specific functional thin film fabrication situation, and will not be described in detail here.

[0021] S2: The second layer of the pattern is used to create a mask and etch it.

[0022] S21: The mask material can be stainless steel or other metal materials, or silicon-based wafers or ceramic thin film materials such as silicon nitride and silicon dioxide. The removal area of ​​the mask is the cutout area, and the retention area is the mask area.

[0023] S22: Mask and substrate alignment: Initial alignment can be determined visually. Based on the thousand-micron-level crosshair alignment marks at the four corners of the mask and substrate, move the relative positions of the mask and substrate to make the first contact between them. Next, use a substrate transfer platform to continue adjusting the positions of the mask and substrate. Based on the hundred-micron-level crosshair alignment marks at the four corners of the mask and substrate, coarsely adjust the alignment between the mask and substrate. Again, use the substrate transfer platform to finely adjust the alignment between the mask and substrate based on the ten-micron-level and micron-level crosshair alignment marks at the four corners of the mask and substrate.

[0024] S23: Etching position alignment confirmation: After the mask and substrate are aligned, use the substrate transfer platform to observe whether the alignment marks at the four corners of the functional thin film and the circuit area are aligned at each level.

[0025] S24: After alignment, use resin glue or pressure springs to fix the mask and substrate;

[0026] S25: Place the fixed mask and substrate together in the etching machine for the first etching;

[0027] S3: After the first etching is completed, remove the mask, rotate it 90°, and align the mask and substrate again. Repeat step S2 to complete the etching of the square array dot matrix pattern.

[0028] As a further preferred embodiment of the present invention, in step S11, the fabrication of the circuit and the alignment mark does not involve photoresist or polar solvent etching. Using general MEMS processes, the first layer pattern is used as a photolithography pattern to complete the patterning process: photolithography—development—deposition of conductive metal layer—lifting or deposition of conductive metal layer—photolithography—development—etching; or, the first layer pattern can be fabricated as a mask, attached to the substrate surface, and the thin film fabrication of the circuit and the alignment mark can be completed using physical vapor deposition.

[0029] As a further preferred embodiment of the present invention, the physical vapor deposition process includes any one of electron beam evaporation coating process, thermal evaporation coating process, and magnetron sputtering coating process.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. This invention is the first to propose a mask and method for dry etching of rectangular array matrix array points.

[0032] 2. This invention avoids the use of photoresist or polar solvents, improves the inclusiveness of MEMS processes, and enables more high-performance new thin films to be applied in microelectronic devices.

[0033] 3. The array pattern made using the pattern etching method of this invention can be compatible with any MEMS manufacturing plant. The alignment marks of the substrate and the mask can be compatible with the first layer circuit wiring process, saving manufacturing costs. Attached Figure Description

[0034] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 It is a square array of points that needs to be completed;

[0036] Figure 2 It is the first layer of layout design scheme and description;

[0037] Figure 3 It is the design scheme and explanation for the second layer of the layout;

[0038] Figure 4 This is a schematic diagram of the etching process of the square array pattern in this invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described in detail below. However, the following embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0040] Example 1

[0041] A mask for etching a square array pattern, the etched square array pattern being as follows: Figure 1 The etched square array shown has N*N dots, with a dot size of a*a square and a resolution of b.

[0042] The mask includes, for example, Figure 2 The first layer of the map shown and as follows Figure 3 The second layer of the map is shown;

[0043] The first layer layout is used to fabricate the lower-layer circuitry for various applications of alignment markers and functional thin films, including:

[0044] 1) Functional thin film and circuit area (purple area), and blank area. The blank area is the layout area for drawing other circuit leads and pads. The functional thin film and circuit area (purple area) is a square centered at the layout center (0,0) with a side length of N*b (N is the number of rows / columns of the dot matrix, and b is the dot matrix resolution). The circuit layout design scheme of the layer below the thin film and the circuit leads outside the thin film layer are determined based on the dot matrix and device structure of the functional thin film. This layout does not provide a specific design scheme; only the functional thin film and the circuit area of ​​the layer below the thin film are drawn using the purple area.

[0045] 2) Alignment markers for the etching array are placed at the four corners of the functional thin film and the circuit area (purple area). The distance from the center of the alignment marker to the center of the layout (center of the purple area) (0, 0) is c, where c > Nb / 2. 1 / 2 The angle between the adjacent lines connecting the center of the map and the centers of the four counterpoints is 90°, and the etched counterpoint layer structure can range from a cross shape at the level of hundreds of micrometers to a cross shape at the level of a few micrometers.

[0046] 3) Set in the first layer version Figure 4 Diagonal position label ( Figure 2 (Right) This alignment marker is used for alignment between the mask and the substrate. It features a cross-shaped structure with multi-level precision design. The size of the cross can range from thousands of micrometers to micrometers. The next level marker is placed in the blank corners of the previous level. The alignment marker level is determined by the precision of the etching pattern. For example, if the pattern precision is at the hundred-micrometer level, the alignment marker cross can be drawn from thousands to tens of micrometers. The first level cross is at the thousand-micrometer (millimeter) level, allowing for initial visual judgment of the mask and substrate position; the second level is at the hundred-micrometer level, requiring an optical microscope; the third level is at the tens of micrometer level; the fourth level is at several micrometers; and so on, with each level's cross located in the blank corners of the previous level's cross.

[0047] Instructions for use: First, place the mask on the substrate surface and determine its position visually based on the first-level thousand-micron cross shape. Second, use a substrate transfer stage to coarsely adjust the position between the mask and the substrate based on the second-level hundred-micron cross shape. Then, use a substrate transfer stage to finely adjust the position between the mask and the substrate based on the third-level ten-micron and fourth-level several-micron cross shapes.

[0048] The second layer (mask) is used to fabricate the etching mask, such as... Figure 3 Shown, including:

[0049] 4) Includes a cutout area (red area) and a mask area (white area), corresponding to the functional thin film and circuit area and the blank area of ​​the first layer layout, respectively; the cutout area is the etched area mask area layout (e.g., Figure 3(As shown on the left): The etched mask area layout is a grid stripe structure, where each stripe is N*b in length (N is the number of rows / columns of the dot matrix, b is the resolution of the square dot matrix), and a in width (the side length of the square array dots). There are a total of N stripes, and the center of the N stripes is the center of the layout (0, 0).

[0050] 5) Etching alignment marks for the etching array are placed at the four corners of the etching mask area, consistent with the etching alignment marks of the first layer layout, for positional alignment between the etching area of ​​the mask and the substrate.

[0051] 6) Four corner alignment marks (e.g.) Figure 3 (As shown on the right): The four corner alignment marks are consistent with those of the first layer layout and are used for direct alignment between the mask and the substrate.

[0052] Example 2

[0053] The method for etching a square array pattern using a mask with an etchable square array pattern in this embodiment includes the following steps:

[0054] S1: Utilizing the first layer of the map:

[0055] S11: Fabricate the circuitry of the functional thin-film array region on the substrate, and simultaneously pattern the various alignment markers. The fabrication of the circuitry and alignment markers does not involve photoresist or polar solvent etching, so general MEMS processes can be used. The first layer pattern can be used as a photolithography pattern to complete the patterning process: photolithography—development—deposition of conductive metal layer—lifting or deposition of conductive metal layer—photolithography—development—etching (wet / dry etching); or, the first layer pattern can be fabricated as a mask, attached to the substrate surface, and the thin film fabrication of the circuitry and alignment markers can be completed using physical vapor deposition processes (electron beam evaporation deposition, thermal evaporation deposition, magnetron sputtering deposition).

[0056] S12: After the lower layer circuit and alignment mark patterning of the array points are completed, a functional thin film is deposited on the upper layer of the circuit. The functional thin film can be deposited by thermal evaporation, spin coating, or other processes. The specific method is set according to the specific functional thin film fabrication situation, and will not be described in detail here.

[0057] S2: The second layer of the pattern is used to create a mask and etch it.

[0058] S21: The mask material can be stainless steel or other metal materials, or silicon-based wafers or ceramic thin film materials such as silicon nitride and silicon dioxide. The red area of ​​the layout is the area to be removed (cutout area) of the mask, and the white area is the area to be retained (mask area).

[0059] S22: Mask and substrate alignment: Initial alignment can be determined visually. Based on the thousand-micron-level crosshair alignment marks at the four corners of the mask and substrate, move the relative positions of the mask and substrate to make the first contact between them. Next, use a substrate transfer platform to continue adjusting the positions of the mask and substrate. Based on the hundred-micron-level crosshair alignment marks at the four corners of the mask and substrate, coarsely adjust the alignment between the mask and substrate. Again, use the substrate transfer platform to finely adjust the alignment between the mask and substrate based on the ten-micron-level and micron-level crosshair alignment marks at the four corners of the mask and substrate.

[0060] S23: Etching position alignment confirmation: After the mask and substrate are aligned, use the substrate transfer platform to observe whether the alignment marks at the four corners of the functional thin film and the circuit area are aligned at each level.

[0061] S24: After alignment, use resin glue or pressure springs to fix the mask and substrate;

[0062] S25: Place the fixed mask and substrate together in the etching machine for the first etching. The specific equipment used in the etching process, etching parameters, and other details are related to the physicochemical properties of the etched film and require adjustments to each step of the process depending on the specific circumstances. This instruction does not provide specific details.

[0063] S3: After the first etching is completed, remove the mask, rotate it 90°, and align the mask and substrate again. Repeat step S2 to complete the etching of the square array dot matrix pattern.

[0064] A schematic diagram of the etching array patterning process of this invention is shown below. Figure 4 As shown.

[0065] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be considered as equivalent replacement methods and are included in the scope of protection of the present invention.

Claims

1. A mask for etching a square array pattern, characterized in that, The etching array pattern has N*N etching array points, the array size is a*a square, and the resolution is b. The mask plate includes two layers of layout: a first layer and a second layer. The first layer layout is used to fabricate the lower-layer circuitry for various applications of alignment markers and functional thin films, including: 1) Functional thin film and circuit area, and blank area, wherein the blank area is the layout area for drawing other leads and pads of the circuit, and the functional thin film and circuit area is a square centered at the layout center (0,0) with a side length of N*b; 2) Alignment markers for the etching array are placed at the four corners outside the functional thin film and circuit area. The center position of the alignment marker is c away from the center position (0, 0) of the layout, where c > Nb / 2. 1 / 2 The angle between the adjacent lines connecting the center of the map and the centers of the four counterpoints is 90º, and the etched counterpoint layer structure ranges from a cross shape at the level of hundreds of micrometers to a cross shape at the level of a few micrometers. 3) Alignment marks are placed at the four corners of the first layer layout for alignment between the mask and the substrate. The alignment marks are cross-shaped with a multi-precision layer design. The size of the cross ranges from thousands of micrometers to micrometers. The next layer is placed in the blank position at the four corners of the previous layer. The second layer pattern is used to fabricate an etching mask, including: 4) Includes a cutout area and a mask area. The cutout area corresponds to the functional thin film and circuit area of ​​the first layer layout, and the mask area corresponds to the blank area of ​​the first layer layout. The cutout area is an etched mask area layout: the etched mask area layout is a grid stripe structure, wherein each stripe has a length of N*b and a width of a, with a total of N stripes, and the center of the N stripes is the layout center (0,0). 5) Etching alignment marks for the etching array are placed at the four corners of the etching mask area, consistent with the etching alignment marks of the first layer layout, for positional alignment between the etching area of ​​the mask and the substrate; 6) Four-corner alignment marks: These are consistent with the four-corner alignment marks of the first layer layout and are used for direct alignment between the mask and the substrate.

2. A method for etching a square array pattern using a mask for etching a square array pattern, characterized in that, Includes the following steps: S1: Utilizing the first layer of the map: S11: Fabricate the circuitry of the lower layer of the functional thin-film array region on the substrate, and also graphically represent each alignment mark; S12: After the lower layer circuit and alignment mark patterning of the array points are completed, a functional thin film is deposited on the upper layer of the circuit. The functional thin film is deposited by thermal evaporation or spin coating. S2: The second layer of the pattern is fabricated using a mask and etched. S21: The mask material is a metal material, a silicon-based wafer, or a ceramic thin film material. The removal area of ​​the mask is the cutout area, and the retention area is the mask area. S22: Mask and substrate alignment: Initial alignment is determined visually. Based on the thousand-micron-level crosshair alignment marks at the four corners of the mask and substrate, the relative positions of the mask and substrate are moved, and the mask and substrate are brought into initial contact. Next, the position of the mask and substrate is further adjusted using a substrate transfer platform. Based on the hundred-micron-level crosshair alignment marks at the four corners of the mask and substrate, the alignment between the mask and substrate is coarsely adjusted. Then, the alignment between the mask and substrate is finely adjusted again using the substrate transfer platform based on the ten-micron-level and micron-level crosshair alignment marks at the four corners of the mask and substrate. S23: Etching position alignment confirmation: After the mask and substrate are aligned, use the substrate transfer platform to observe whether the alignment marks at the four corners of the functional thin film and the circuit area are aligned at each level. S24: After alignment, use resin glue or pressure springs to fix the mask and substrate; S25: Place the fixed mask and substrate together in the etching machine for the first etching; S3: After the first etching is completed, remove the mask, rotate it 90º, and align the mask and substrate again. Repeat step S2 to complete the etching of the square array dot matrix pattern.

3. The method for etching a square array pattern on a mask according to claim 2, characterized in that, The metal material is stainless steel; the ceramic thin film material is silicon nitride thin film or silicon dioxide thin film.

4. The method for etching a square array pattern on a mask according to claim 2, characterized in that, In step S11, the fabrication of the circuit and the alignment mark does not involve photoresist or polar solvent etching. Using general MEMS processes, the first layer layout is used as the photolithography layout to complete the patterning process: photolithography—development—deposition of conductive metal layer—lifting or deposition of conductive metal layer—photolithography—development—etching; or, the first layer layout is fabricated as a mask, attached to the substrate surface, and the thin film fabrication of the circuit and the alignment mark is completed using physical vapor deposition.

5. The method for etching a square array pattern on a mask according to claim 4, characterized in that, The physical vapor deposition process includes any one of electron beam evaporation coating process, thermal evaporation coating process, and magnetron sputtering coating process.

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