Chip and electronic equipment

Abstract

The embodiment of the invention provides a chip and electronic equipment, the chip comprises a plurality of chip ports, a port multiplexing logic module and a scanning test logic module, the port multiplexing logic module is provided with a plurality of groups of first ports and a plurality of groups of second ports, and the plurality of chip ports are divided into a plurality of groups according to preset granularity; each group of chip ports is connected to at least one of a plurality of groups of first ports and a plurality of groups of second ports of the port multiplexing logic module, and the plurality of groups of first ports or the plurality of groups of second ports of the port multiplexing logic module are connected to the scanning test logic module; and the port multiplexing logic module is used for controlling gating of a path between the chip port and the scanning test logic module by taking a preset granularity as a unit according to the control instruction. According to the embodiment of the invention, the problems of unreasonable I / O allocation and long test time of large-scale complex chips in related technologies can be solved, the degree of freedom of I / O allocation is improved by setting the granularity of I / O allocation, the I / O resources are dynamically adjusted in the test stage, and the chip test time is shortened.

Description

Technical Field

[0001] The present application relates to the field of chip design, and more specifically, to a chip and an electronic device. Background Art

[0002] As the complexity of integrated circuits continues to increase, scan chain testing technology plays an important role in effectively screening out chip faults and reducing test time. With the continuous development of the scale of integrated circuits, in order to avoid the scan chain being too long and unfavorable for testing, it is necessary to introduce embedded deterministic testing (EDT) compression technology to increase the number of scan chains and reduce the length of scan chains. The number of scan chains is increasing, while the input / output (I / O) resources of the chip are relatively limited, so I / O resources need to be time-divided and multiplexed.

[0003] The commonly used pin multiplexing (PinMux) method in the industry is to group different modules and allocate fixed I / O resources to them. However, in the early stage of chip design, it is impossible to accurately judge the complexity of each module and the power consumption distribution of each module. The optimal grouping strategy can only be obtained after signoff or even tape-out. The I / O allocation of the traditional grouping method is fixed, and it is impossible to adjust the design according to the optimal grouping, which easily leads to unreasonable I / O allocation, resulting in complex modules not obtaining a sufficient number of I / O resources, resulting in long testing time, uneven power consumption distribution, and device voltage drop.

[0004] In summary, there is no good solution to the problems of unreasonable I / O allocation and long testing time for large-scale complex chips in related technologies. Summary of the invention

[0005] The embodiments of the present application provide a chip and an electronic device to at least solve the problems of unreasonable I / O allocation and long testing time of large-scale complex chips in the related art.

[0006] According to one embodiment of the present application, a chip is provided, which includes multiple chip ports, a port multiplexing logic module and a scan test logic module, wherein: the port multiplexing logic module has multiple groups of first ports and multiple groups of second ports, and the multiple chip ports are divided into multiple groups according to a preset granularity; each group of chip ports is connected to at least one of the multiple groups of first ports and the multiple groups of second ports of the port multiplexing logic module, and the multiple groups of first ports or the multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module; the port multiplexing logic module is used to control the selection of the path between the chip port and the scan test logic module in units of the preset granularity according to a control instruction.

[0007] According to another embodiment of the present application, an electronic device is provided, comprising the chip in any one of the above embodiments.

[0008] Through the embodiments of the present application, a chip is designed, which improves the freedom of I / O allocation by setting the granularity of I / O allocation, and controls the conduction relationship between the input port and the output port in units of granularity. This can solve the problems of unreasonable I / O allocation and long testing time for large-scale complex chips in related technologies, and can also dynamically adjust I / O resources during the testing phase, effectively reducing the chip testing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a structural block diagram of a chip according to an embodiment of the present application;

[0010] Figure 2 is a structural block diagram of another chip according to an embodiment of the present application;

[0011] Figure 3 is a schematic diagram of the circuit structure of the chip of the embodiment of the present application;

[0012] Figure 4 1 is a circuit structure diagram of a port multiplexing logic module according to an embodiment of the present application (I);

[0013] Figure 5 This is a circuit structure diagram of a port multiplexing logic module according to an embodiment of the present application (II);

[0014] Figure 6 Schematic diagram of the circuit structure of a port multiplexing logic module of an embodiment of the present application (III);

[0015] Figure 7 This is a circuit structure diagram of a port multiplexing logic module of an embodiment of the present application (IV). DETAILED DESCRIPTION

[0016] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0017] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0018] In the embodiment of the present application, a chip is provided for embedded deterministic testing. As the chip scale continues to grow, the number of scan chains to be tested is also increasing, but the I / O resources of the chip are relatively limited. The chip to be tested designed according to the following embodiment can readjust the connection relationship between the chip port and the scan chain to be tested inside the chip during the chip testing phase, so as to realize dynamic adjustment and flexible allocation of I / O resources.

[0019] Figure 1 is a structural block diagram of a chip according to an embodiment of the present application, such as Figure 1 As shown, the chip includes the following structures:

[0020] A plurality of chip ports 12 , a port multiplexing logic module 14 and a scan test logic module 16 .

[0021] In this embodiment, the port multiplexing logic module has multiple groups of first ports and multiple groups of second ports, and the multiple chip ports are divided into multiple groups according to a preset granularity.

[0022] In this embodiment, each group of chip ports is connected to at least one of the multiple groups of first ports and the multiple groups of second ports of the port multiplexing logic module, and the multiple groups of first ports or the multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module.

[0023] In this embodiment, the port multiplexing logic module is used to control the gating of the path between the chip port and the scan test logic module in units of the preset granularity according to the control instruction.

[0024] Through the embodiments of the present application, port grouping can be achieved by presetting the granularity, thereby improving the freedom of I / O allocation. The conduction relationship between the input port and the output port is controlled in units of granularity, which can solve the problems of unreasonable I / O allocation and long testing time of large-scale complex chips in related technologies. I / O resources can also be dynamically adjusted during the testing phase, effectively reducing chip testing time.

[0025] In some embodiments, the plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, where i is less than j, and i and j are positive integers. In the case where the chip ports are chip input ports, the plurality of groups of first ports of the port multiplexing logic module are plurality of groups of input ports, and the plurality of groups of second ports of the port multiplexing logic module are plurality of groups of output ports, each group of chip ports is connected to at least one group of the plurality of groups of first ports of the port multiplexing logic module, the plurality of groups of second ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is i+1, and the number of output port groups of the port multiplexing logic module is j+1.

[0026] In some embodiments, the port multiplexing logic module includes j+1 first multiplexer groups, wherein each of the first multiplexer groups is connected to i+1 input port groups of the port multiplexing logic module, and each of the first multiplexer groups is connected to one output port group of the port multiplexing logic module; the first multiplexer group is used to select a target input port group among the i+1 input port groups and a corresponding target output port group according to the control instruction.

[0027] In some embodiments, when the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the first multiplexer groups includes N first multiplexers.

[0028] In some embodiments, the port multiplexing logic module further includes: i+1 input register groups and j+1 input channel register groups; the i+1 input port groups are connected to each of the first multiplexer groups through the i+1 input register groups; and each of the first multiplexer groups is connected to one output port group through one of the input channel register groups.

[0029] In some embodiments, the port multiplexing logic module includes i+1 first demultiplexer groups and j+1 OR operation modules, wherein each of the first demultiplexer groups is connected to one input port group of the port multiplexing logic module, each of the first demultiplexer groups is connected to the j+1 OR operation modules, and each of the OR operation modules is connected to one of the output port groups of the port multiplexing logic module; the first demultiplexer group is used to select a target output port group among the j+1 output port groups and the corresponding target input port group according to the control instruction.

[0030] In some embodiments, when the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the first demultiplexer groups includes N first demultiplexers.

[0031] In some embodiments, the port multiplexing logic module further includes: i+1 input register groups and j+1 input channel register groups; each input port group is connected to a first demultiplexer group via an input register group; and each OR operation module is connected to an output port group via an input channel register group.

[0032] In some embodiments, the plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, where i is less than j, and i and j are positive integers. In the case where the chip ports are chip output ports, the plurality of groups of second ports of the port multiplexing logic module are plurality of groups of output ports, and the plurality of groups of first ports of the port multiplexing logic module are plurality of groups of input ports, each group of chip ports is connected to at least one group of the plurality of groups of second ports of the port multiplexing logic module, the plurality of groups of first ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is j+1, and the number of output port groups of the port multiplexing logic module is i+1.

[0033] In some embodiments, the port multiplexing logic module includes i+1 second multiplexer groups, wherein each of the second multiplexer groups is connected to j+1 input port groups of the port multiplexing logic module, and each of the second multiplexer groups is connected to one output port group of the port multiplexing logic module; the second multiplexer group is used to select a target input port group among the j+1 input port groups and a corresponding target output port group according to the control instruction.

[0034] In some embodiments, when the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the second multiplexer groups includes N second multiplexers.

[0035] In some embodiments, the port multiplexing logic module further includes: j+1 output channel register groups and i+1 output register groups; each input port group is connected to each second multiplexer group via one output channel register group, and each second multiplexer group is connected to one output port group via one output register group.

[0036] In some embodiments, the port multiplexing logic module includes j+1 second demultiplexer groups and i+1 OR operation modules, wherein each of the second demultiplexer groups is connected to one input port group of the port multiplexing logic module, each of the second demultiplexer groups is connected to the i+1 OR operation modules, and each of the OR operation modules is connected to one of the output port groups of the port multiplexing logic module; the second demultiplexer group is used to select a target output port group among the i+1 output port groups and the corresponding target input port group according to the control instruction.

[0037] In some embodiments, when the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the second demultiplexer groups includes N second demultiplexers.

[0038] In some embodiments, the port multiplexing logic module further includes: j+1 output channel register groups and i+1 output register groups; each input port group is connected to a second demultiplexer group via an output channel register group; each OR operation module is connected to an output port group via an output register group.

[0039] A test chip is also provided in an embodiment of the present application.

[0040] Figure 2 is a structural block diagram of another chip in an embodiment of the present application, such as Figure 2 As shown, the chip includes:

[0041] Chip port 22 , controller 24 , port multiplexing logic module 26 and scan test logic module 28 .

[0042] In this embodiment, the chip ports are connected to the ports of the scan test logic module through the port multiplexing logic module, wherein the number of the chip ports is less than the number of the ports of the scan test logic module.

[0043] In this embodiment, the controller is used to send a control instruction to the port multiplexing logic module.

[0044] In this embodiment, the port multiplexing logic module is the port multiplexing logic module in any of the above embodiments, and may be a port multiplexing logic module and / or a port multiplexing logic module.

[0045] In this embodiment, the scan test logic module includes: a plurality of embedded deterministic test EDT channel chains, wherein the ports of the scan test logic module are ports of the EDT channel chains.

[0046] Furthermore, the scan test logic module is used to test the EDT channel chain connected to the chip port.

[0047] In some embodiments, the scan test logic module may include multiple scan test modules, wherein each of the scan test modules includes at least one EDT channel chain; the scan test logic module is used to test each test group in a plurality of test groups at different times, wherein each of the test groups includes at least one EDT channel chain group, wherein the plurality of EDT channel chains are divided into a plurality of EDT channel chain groups according to the preset granularity, and the plurality of test groups are allocated according to the attribute parameters of the plurality of scan test modules.

[0048] Through the embodiments of the present application, the test grouping can be dynamically adjusted according to the attribute parameters of the test module during the chip testing phase, effectively reducing the test time, thereby solving the problems of unreasonable IO allocation and long test time for large-scale complex chips in related technologies.

[0049] Figure 3 is a schematic diagram of the circuit structure of the chip of the embodiment of the present application, such as Figure 3 As shown, the chip includes the following structure:

[0050] A plurality of general input ports 100 , a port multiplexing logic module 200 , a scan test logic module 300 , a port multiplexing logic module 400 , a plurality of general output ports 500 and a controller 600 .

[0051] In this embodiment, the plurality of universal input ports 100 are equivalent to the chip input ports in the above embodiment, and the plurality of universal output ports 500 are equivalent to the chip output ports in the above embodiment.

[0052] In this embodiment, a plurality of general input ports and a plurality of general output ports are divided into a plurality of I / O groups according to a preset granularity.

[0053] Furthermore, data is input from a general-purpose input port in a general-purpose input / output (GPIO) into the port multiplexing logic module, and after the logic module is scanned and tested, the test data result is output from a general-purpose output port.

[0054] In this embodiment, multiple general input ports are connected to multiple input ends of the port multiplexing logic module, multiple output ends of the port multiplexing logic module are connected to multiple input ends of the scan test logic module, multiple output ends of the scan test logic module are connected to multiple input ends of the port multiplexing logic module, multiple output ends of the port multiplexing logic module are connected to the multiple general output ports, and the controller is respectively connected to the port multiplexing logic module and the port multiplexing logic module.

[0055] In this embodiment, the granularity is used to describe the I / O grouping, that is, the number of I / Os contained in each group. The size of the granularity directly affects the degree of freedom of I / O allocation in the scan test and the logic increment in the I / O multiplexing logic module. The minimum granularity can be set to 1.

[0056] Furthermore, the smaller the granularity, the higher the freedom of I / O allocation, but at the same time, more scan I / O reuse logic needs to be introduced; the larger the granularity, the scan io reuse logic will be effectively simplified, but the freedom of I / O allocation in the corresponding scan test will be limited. Therefore, the granularity should be reasonably configured in the chip design stage to achieve a balance between the freedom of I / O allocation and the amount of I / O reuse logic.

[0057] In this embodiment, the grouping of logic units in each port or module in the chip is based on granularity.

[0058] In this embodiment, the scan test logic module is used to test the embedded deterministic test EDT channel chain that is connected to the universal input port and the universal output port.

[0059] Specifically, the EDT channel chain is obtained by compressing the scan chain, and is the basic unit of Embedded Deterministic Testing (EDT).

[0060] In this embodiment, the controller is used to send control instructions to the port multiplexing logic module and the port multiplexing logic module respectively.

[0061] In this embodiment, the port multiplexing logic module is used to turn on the multiple general input ports and some input ends of the scan test logic module in units of the I / O group according to the control instruction, wherein the number of the multiple general input ports is less than the number of the multiple input ends of the scan test logic module.

[0062] In this embodiment, the port multiplexing logic module is used to connect part of the output ends of the scan test logic module to the multiple general output ports in units of the I / O group according to the control instruction, wherein the number of the multiple general output ports is less than the number of the multiple output ends of the scan test logic module.

[0063] Furthermore, the port multiplexing logic module is used to implement time-division multiplexing of the general input port, and the port multiplexing logic module is used to implement time-division multiplexing of the general output port.

[0064] Specifically, the number of general-purpose input / output ports is less than the number of input / output terminals of the scan test logic module. By instructing the port multiplexing logic module and the port multiplexing logic module through the controller, the general-purpose output / output ports can be turned on with different input / output terminals in the scan test logic module at different times, that is, time-sharing multiplexing of the general-purpose output / output ports is realized, thereby ensuring the test effect of the scan test logic module when I / O resources are limited.

[0065] In some embodiments, the controller 600 may be a test access port controller (TAP for short), or other devices that can output control signals and control a multiplexer / demultiplexer, which is not limited in the present application.

[0066] Through the embodiments of the present application, dynamic adjustment of I / O resources is achieved in the test phase, so that I / O allocation is not restricted by the chip design phase. It is even possible to dynamically adjust the grouping of test modules under different test modes according to the actual conditions of the modules to be tested, thereby effectively reducing the chip testing time and solving the problems of unreasonable I / O allocation and long testing time for large-scale complex chips in related technologies.

[0067] In some embodiments, the preset granularity is N, each I / O group includes N general input ports and N general output ports, and N is a positive integer.

[0068] In some embodiments, the scan test logic module includes multiple scan test modules, wherein each of the scan test modules includes at least one EDT channel chain, the input end of each of the EDT channel chains is an input end of the scan test logic module, and the output end of each of the EDT channel chains is an output end of the scan test logic module.

[0069] In some embodiments, a scan test logic module is used to test each test group in a plurality of test groups at different times, wherein each of the test groups includes at least one EDT channel chain group, each of the EDT channel chain group includes N EDT channel chains, and the plurality of test groups are allocated according to attribute parameters of the plurality of scan test modules.

[0070] Furthermore, the number of ports in each I / O group and the number of EDT channel chains in each EDT channel chain group are the same as the preset granularity. When a port in an I / O group is connected to an EDT channel chain in an EDT channel chain group, the other ports in the I / O group are respectively connected to the other EDT channel chains in the EDT channel chain group.

[0071] In this embodiment, the number of general input / output ports is less than the number of EDT channel chains to be tested. By configuring the controller, the conduction status of the general input / output ports and the EDT channel chains can be dynamically adjusted to achieve data transmission between the I / O and EDT channel chains.

[0072] In some embodiments, the attribute parameters of the scan test module may include but are not limited to any one or combination of the following parameters: number of EDT channels, cross-talk between scan test modules, test mode, number of test vector patterns, power consumption. The attribute parameters may also include any other parameters that may affect the test process or test results.

[0073] In some embodiments, the port multiplexing logic module and the port multiplexing logic module can be implemented by a multiplexer or a demultiplexer. The technician can also implement time-division multiplexing of the I / O input / output port by a selector or other logic operation modules, and this application does not limit this.

[0074] Figure 4 1 is a circuit structure diagram of a port multiplexing logic module of an embodiment of the present application (I), such as Figure 4 As shown, the port multiplexing logic module may include the following structure:

[0075] A plurality of first multiplexer groups 240 .

[0076] In this embodiment, the number of the plurality of first multiplexer groups is the same as the number of the plurality of EDT channel chain groups.

[0077] In this embodiment, each first multiplexer group includes multiple groups of input terminals and one group of output terminals, and one group of input terminals and one group of output terminals can be selected under the control of a control instruction.

[0078] In some embodiments, according to a preset granularity, the input ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_in_0 to dft_edt_in_i, each group of input ports is connected to a group of general input ports, and the output ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_in_channel_0 to dft_edt_in_channel_j, each group of output ports is connected to an EDT channel chain group. Correspondingly, the number of the first multiplexer group is j+1, and i is less than j.

[0079] In some embodiments, the port multiplexing logic module may further include a plurality of input registers 220 and a plurality of input channel registers 260 .

[0080] In some embodiments, the preset granularity is N, the input / output port group (I / O group) includes N input / output ports, each first multiplexer group includes N first multiplexers, and each EDT channel chain group includes N EDT channel chains.

[0081] Furthermore, Figure 4 The circuit connections in the system are carried out in the form of buses, and each bus contains a group of N lines. Figure 4 The number of input registers 220 and input channel registers 260 is omitted, and in fact each line can be connected to a register.

[0082] In this embodiment, the input (dft_edt_in) register is located at the input port side of the port multiplexing logic module, the input channel (dft_edt_in_channel) register is located at the output port side of the port multiplexing logic module, and the logic between the input register and the input channel register is the I / O multiplexing (scan ioreuse) logic in the port multiplexing logic module.

[0083] In this embodiment, each group universal input port is respectively connected to the multiple first multiplexer groups through the input register, and each of the first multiplexer groups is connected to one of the EDT channel chain groups through the input channel register, wherein each first multiplexer in the first multiplexer group corresponds to an EDT channel chain in an EDT channel chain group.

[0084] In this embodiment, the first multiplexer group is used to select a target I / O group among the multiple I / O groups and the corresponding target EDT channel chain group according to the control instruction, wherein the N general input ports in the target I / O group are connected to the input ends of the N EDT channel chains in the target EDT channel chain group.

[0085] In some embodiments, when the granularity is N, each first multiplexer group includes N first multiplexers. Each first multiplexer has i+1 input terminals and 1 output terminal, the i+1 input terminals are respectively connected to one universal input port in the i+1 I / O groups, and the 1 output terminal is connected to the input terminal of one EDT channel chain. The first multiplexer can select one of the i+1 universal input ports as the target universal input port to be connected to the corresponding uniquely connected EDT channel chain, thereby implementing the test of the EDT channel chain.

[0086] In some embodiments, each group of N first multiplexers can be controlled by a control signal to achieve the gating of N paths. For example, the input end of the first first multiplexer in the first multiplexer group can be connected to the first port in each bus (or each group of universal input ports), and one of the multiple first ports is selected to be connected to the first output port in the output port group of the first multiplexer group. Correspondingly, the other first multiplexers in the first multiplexer group are sequentially connected to the corresponding ports in each bus (or each group of universal input ports).

[0087] Furthermore, Figure 4 The first first multiplexer in each first multiplexer group can be connected to ports such as dft_edt_in_0[0], dft_edt_in_1[N], and dft_edt_in_i[N·i], and one port is selected to be connected to the first port in the corresponding output port group. The second first multiplexer can be connected to ports such as dft_edt_in_0[1], dft_edt_in_1[N+1], and dft_edt_in_i[N·i+1], and the other first multiplexers can be connected in the same manner.

[0088] In some embodiments, the logic of the I / O reuse logic module (scan io reuse) is controlled by a configuration chain in the tap controller. The configuration chain can be used to control the conduction logic of the first multiplexer or the first multiplexer group, thereby realizing dynamic I / O reuse allocation.

[0089] In this embodiment, the configure chain in the tap controller is connected to the selection end dft_edt_in_sel of each multiplexer, so that only one path from dft_edt_in to dft_edt_in_channel in the multiplexer is selected, thereby realizing dynamic allocation and time-division multiplexing of the scan io input end, and the bit width of the dft_edt_in_sel signal is related to the I / O granularity N.

[0090] In some embodiments, the control instructions include a first serial instruction and a second serial instruction.

[0091] In some embodiments, the controller is used to control a plurality of first multiplexer groups or a plurality of first demultiplexer groups in the port multiplexing logic module to select the plurality of general input ports and part of the input ends of the scan test logic module through the first serial instruction.

[0092] In some embodiments, the controller is further used to control multiple second multiplexer groups or multiple second demultiplexer groups in the port multiplexing logic module through the second serial instruction to select part of the output ends of the scan test logic module and the multiple general output ports.

[0093] In an embodiment of the present application, by controlling the I / O multiplexing logic through the controller, time-sharing multiplexing of the chip's general input and output ports can be achieved, and adjustment of the I / O grouping can be achieved during the test process, thereby effectively reducing the EDT test time.

[0094] Figure 5 Schematic diagram (II) of the circuit structure of a port multiplexing logic module of an embodiment of the present application, such as Figure 5 As shown, the port multiplexing logic module may include the following structure:

[0095] A plurality of first demultiplexer groups 230 and a plurality of OR operation modules 250 .

[0096] In this embodiment, the number of the plurality of first demultiplexer groups is the same as the number of the plurality of I / O groups.

[0097] In this embodiment, each first demultiplexer group includes a group of input ends and multiple groups of output ends. Under the control of the control instruction, one group of input ends and one group of output ends can be selected.

[0098] In some embodiments, according to a preset granularity, the input ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_in_0 to dft_edt_in_i, each group of input ports is connected to a group of general input ports, and the output ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_in_channel_0 to dft_edt_in_channel_j, each group of output ports is connected to an EDT channel chain group, and multiple EDT channel chains are divided into j+1 EDT channel chain groups. Correspondingly, the number of the first demultiplexer group is i+1, and i is less than j.

[0099] In some embodiments, the port multiplexing logic module may further include a plurality of input registers 220 and a plurality of input channel registers 260 .

[0100] In some embodiments, the preset granularity is N, the input / output port group (I / O group) includes N input / output ports, each first demultiplexer group includes N first demultiplexers, and each EDT channel chain group includes N EDT channel chains.

[0101] Furthermore, Figure 5 The circuit connections in the system are carried out in the form of buses, and each bus contains a group of N lines. Figure 5 The number of input registers 220 and input channel registers 260 is omitted, and in fact each line can be connected to a register.

[0102] In this embodiment, each group of universal input ports is connected to one of the first demultiplexer groups through the input register, each of the first demultiplexer groups is respectively connected to the multiple OR operation modules, and each of the OR operation modules is connected to one of the EDT channel chain groups through the input channel register.

[0103] In this embodiment, the first demultiplexer group is used to select a target EDT channel chain group among the multiple EDT channel chain groups and the corresponding target I / O group according to the control instruction, wherein the N general input ports in the target I / O group are connected to the input ends of the N EDT channel chains in the target EDT channel chain group.

[0104] In some embodiments, when the granularity is N, each first demultiplexer group includes N first demultiplexers. Each first demultiplexer has 1 input terminal and j+1 output terminals, 1 input terminal is connected to a universal input port in 1 I / O group, and each output terminal is respectively connected to multiple OR operation modules.

[0105] Furthermore, each first demultiplexer selects a target output end from j+1 output ends under the control of the control instruction, connects the input end with the target output end, and then transmits it to a target EDT channel chain in the corresponding EDT channel chain group through the OR operation module, thereby realizing the test of the target EDT channel chain.

[0106] In some embodiments, each group of N first demultiplexers can be controlled by a control signal to achieve the gating of N paths. For example, the input end of the first first demultiplexer in the first demultiplexer group can be connected to the first port in each bus (or each group of universal input ports), and one of the multiple first ports is selected to be connected to the first output port in the output port group of the first demultiplexer group. Correspondingly, the other first demultiplexers in the first demultiplexer group are sequentially connected to the corresponding ports in each bus (or each group of universal input ports).

[0107] Furthermore, Figure 5 The first demultiplexer in the first demultiplexer group has an input terminal connected to dft_edt_in_0[0], and an output terminal connected to ports such as dft_edt_in_channel_0[0], dft_edt_in_channel_1[N], and dft_edt_in_channel_j[N·j], and one port is selected to be turned on. The same applies to other first demultiplexers.

[0108] In some embodiments, each OR operation module is composed of a plurality of OR gates, and each OR operation module may have i+1 groups of input ports and one group of output ports, which are respectively connected to i+1 first demultiplexer groups and one EDT channel chain group. In combination with the controller controlling the i+1 first demultiplexer groups, the OR operation module may transmit any input signal in the i+1 group of input ports to the corresponding EDT channel chain group, wherein each OR operation module can only receive one group of conduction signals at a time.

[0109] In this embodiment, the configure chain in the tap controller is connected to the selection end dft_edt_in_sel of each demultiplexer, so that only one path from dft_edt_in to dft_edt_in_channel in the demultiplexer is selected, thereby realizing dynamic allocation and time-division multiplexing of the scan io input end, and the bit width of the dft_edt_in_sel signal is related to the I / O granularity N.

[0110] In some embodiments, Figure 4 and Figure 5 Take the structure of the port multiplexing logic module as an example. Figure 4 The first multiplexer group is close to one side of the scan test logic module, and the number is equal to the number of groups in the EDT channel chain. Figure 5The first demultiplexer group in [ ] is close to the general input port side, and the number is the same as the number of groups of the general input port. Since the number of general input ports is small while the number of EDT channel chains inside the module is large, under the condition that other conditions are the same, Figure 5 the number of the first demultiplexer groups in [ ] is less than Figure 4 the number of the first multiplexer groups in [ ], and the internal gating logic of the first demultiplexer group is more complex.

[0111] Furthermore, since the width of the gating terminal of the multiplexer group / demultiplexer group and the number of its internal paths show an exponential correspondence relationship, selecting a multiplexer group / demultiplexer group with more complex internal logic is beneficial to the compression of the gating terminal width.

[0112] In some embodiments, Figure 4 、 Figure 5 the total number of bits N of the selection terminals required for the multiplexer group / demultiplexer group in [ ] bit1 、N bit2 are respectively:

[0113] N bit1 =(j + 1)log2(i + 1);

[0114] N bit2 =(i + 1)log2(j + 1);

[0115] Since usually i << j, so N bit1 >> N bit2 , that is, Figure 5 the chain length of the configure chain in [ ] will be shorter.

[0116] Figure 6 is a schematic diagram (III) of the circuit structure of a port multiplexing logic module according to an embodiment of the present application. As Figure 6 shown, the port multiplexing logic module may include the following structures:

[0117] A plurality of second multiplexer groups 440.

[0118] In this embodiment, the number of the plurality of second multiplexer groups is the same as the number of the plurality of EDT channel chain groups.

[0119] In this embodiment, each second multiplexer group includes multiple groups of input terminals and one group of output terminals, and can gate one group of input terminals and one group of output terminals under the control of a control instruction.

[0120] In some embodiments, when the granularity is N, the input ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_out_channel_0 to dft_edt_out_channel_j, each group of input ports is connected to a group of EDT channel chains, multiple EDT channel chains are divided into j+1 EDT channel chain groups, each EDT channel chain group contains N EDT channel chains, and the output ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_out_0 to dft_edt_out_i, each group of output ports is connected to a group of general output ports, multiple general output ports are divided into i+1 I / O groups, and each I / O group contains N general output ports. Correspondingly, the number of the second multiplexer groups is i+1, and i is less than j.

[0121] In some embodiments, the port multiplexing logic module may further include a plurality of output channel registers 420 and a plurality of output registers 460 .

[0122] In some embodiments, the preset granularity is N, the input / output port group (I / O group) includes N input / output ports, each second demultiplexer group includes N second demultiplexers, and each EDT channel chain group includes N EDT channel chains.

[0123] Furthermore, Figure 7 The circuit connections in the system are carried out in the form of buses, and each bus contains a group of N lines.

[0124] In this embodiment, each of the EDT channel chain groups is connected to the plurality of second multiplexer groups respectively through the output channel register, and each of the second multiplexer groups is connected to a group universal output port through the output register.

[0125] In this embodiment, the second multiplexer group is used to select a target EDT channel chain group among the multiple EDT channel chain groups and the corresponding target I / O group according to the control instruction, wherein the output ends of the N EDT channel chains in the target EDT channel chain group are connected to the N general output ports in the target I / O group.

[0126] In some embodiments, each second multiplexer group includes N second multiplexers. Each second multiplexer has j+1 input terminals and 1 output terminal, wherein the j+1 input terminals are respectively connected to one EDT channel chain in the j+1 EDT channel chain group, and the 1 output terminal is connected to a universal output port. The second multiplexer can select one of the j+1 EDT channel chains as the target EDT channel chain and connect it to the corresponding uniquely connected universal output port, thereby obtaining a test result for the target EDT channel chain.

[0127] In some embodiments, the logic of the I / O reuse logic module (scan io reuse) is controlled by a configuration chain in the tap controller, and the configuration chain can be used to control the conduction logic of the second multiplexer or the second multiplexer group, thereby achieving dynamic I / O reuse allocation.

[0128] In this embodiment, the configure chain in the tap controller is connected to the selection end dft_edt_out_sel of each multiplexer, so that only one path from dft_edt_out_channel to dft_edt_out in the multiplexer is selected, thereby realizing dynamic allocation and time-division multiplexing of the scan io input end, and the bit width of the dft_edt_out_sel signal is related to the I / O granularity N.

[0129] Figure 7 Schematic diagram (IV) of the circuit structure of a port multiplexing logic module of an embodiment of the present application, such as Figure 7 As shown, the port multiplexing logic module may include the following structure:

[0130] A plurality of second demultiplexer groups 430 and a plurality of OR operation modules 450 .

[0131] In this embodiment, the number of the plurality of second demultiplexer groups is the same as the number of the plurality of EDT channel chain groups.

[0132] In this embodiment, each second demultiplexer group includes a group of input terminals and multiple groups of output terminals. Under the control of the control instruction, one group of input terminals and one group of output terminals can be selected.

[0133] In some embodiments, according to a preset granularity, the input ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_out_channel_0 to dft_edt_out_channel_j, each group of input ports is connected to a group of EDT channel chains, and multiple EDT channel chains are divided into j+1 EDT channel chain groups, and the output ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_out_0 to dft_edt_out_i, each group of output ports is connected to a group of general output ports, and multiple general output ports are divided into i+1 I / O groups. Correspondingly, the number of the second demultiplexer group is j+1, and i is less than j.

[0134] In some embodiments, the port multiplexing logic module may further include a plurality of output channel registers 420 and a plurality of output registers 460 .

[0135] In this embodiment, each of the EDT channel chain groups is connected to one of the second demultiplexer groups through the output channel register, each of the multiple second demultiplexer groups is respectively connected to the multiple OR operation modules, and each of the OR operation modules is connected to a group of general output ports through the output register.

[0136] In this embodiment, the second demultiplexer group is used to select a target I / O group among the multiple I / O groups and the corresponding target EDT channel chain group according to the control instruction, wherein the output ends of the N EDT channel chains in the target EDT channel chain group are connected to the N general output ports in the target I / O group.

[0137] In some embodiments, when the granularity is N, each second demultiplexer group includes N second demultiplexers. Each second demultiplexer has 1 input terminal and i+1 output terminals, 1 input terminal is connected to 1 EDT channel chain, and each output terminal is respectively connected to multiple OR operation modules.

[0138] Furthermore, each second demultiplexer selects a target output end from i+1 output ends under the control of the control instruction, connects the input end with the target output end, and then transmits the signal of the target output end to the only connected universal output port through the OR operation module, thereby obtaining the test result of the EDT channel chain.

[0139] In some embodiments, the logic of the I / O reuse logic (scan io reuse) module is controlled by a configuration chain in the tap controller, and the configuration chain can be used to control the conduction logic of the second demultiplexer or the second demultiplexer group, thereby achieving dynamic I / O multiplexing allocation.

[0140] In this embodiment, the configure chain in the tap controller is connected to the selection terminal dft_edt_out_sel of each demultiplexer, so that only one path from dft_edt_out_channel to dft_edt_out in the demultiplexer is selected, thereby realizing dynamic allocation and time-division multiplexing of the scan io input terminal, and the bit width of the dft_edt_out_sel signal is related to the I / O granularity N.

[0141] In some embodiments, when the granularity is 1, the number of general input ports is i+1, the number of EDT channel chains is j+1, and without considering the selection end, the number of standard cells required for the I / O multiplexing logic is N cell It can be expressed as:

[0142] N cell=(2(i+1)-1)(j+1).

[0143] In some embodiments, when the granularity is N, assuming that the number of general input ports is N(i+1), the number of EDT channel chains is N(j+1), the number of I / O groups remains unchanged, the number of EDT channel chain groups remains unchanged, and correspondingly, the number of standard units N cell Under the condition that the internal logic complexity is the same, more I / O resources can be allocated through the embodiments of the present application.

[0144] In some embodiments, when the granularity is N, assuming that the number of general input ports is i+1 and the number of EDT channel chains is j+1, the corresponding number of I / O groups is (i+1) / N, and the number of EDT channel chain groups is (j+1) / N. At this time, the number of standard cells required for the I / O multiplexing logic module is N. cell for:

[0145]

[0146] That is, the number of standard cells in the I / O multiplexing logic module will be approximately equal to the square of the granularity N. 2 relationship decreased.

[0147] In some embodiments, it can be deduced that Figure 5 The number of standard cells N required for the I / O multiplexing logic module in cell for:

[0148]

[0149] Furthermore, Figure 6 , Figure 7 Describes the transmission process from the output end of the EDT channel chain to the general output port. Similar to the input transmission logic, the output signal is connected to the general output port through the output channel register, I / O multiplexing logic module, and output register. By configuring the configuration chain configure chain of the selector dft_edt_out_sel used to control the I / O multiplexing logic module in the tap controller, a certain I / O multiplexing logic can be dynamically selected to achieve dynamic allocation and time-sharing multiplexing of the general output port.

[0150] In an exemplary embodiment, the I / O multiplexing logic modules in the above embodiments can be combined arbitrarily to obtain a complete port multiplexing logic module.

[0151] The port reuse logic module in the embodiment of the present application is a dynamic scan io reallocation technology proposed for the scan test (scan) mode, which has a high degree of freedom grouping capability and can effectively solve the key problem that the I / O allocation in the related technology is fixed and cannot be reallocated. Through the embodiment of the present application, using the scan io reuse logic, I / O resources can be reallocated according to the optimal module grouping at any stage of chip design, even after chip tape-out. The entire process of scan io reallocation reflects a high degree of flexibility and configurability, and plays an important role in chip design and testing.

[0152] In some embodiments, the scan test logic module includes multiple scan test modules, and the multiple scan test modules can be divided into multiple test groups according to attribute parameters of the multiple scan test modules. Different test groups can be tested at different times through the scan test logic module.

[0153] Further, the attribute parameters include but are not limited to any of the following parameters or parameter combinations: number of EDT channels, crosstalk paths between scan test modules, test mode, number of test vector patterns, power consumption. The attribute parameters can be expanded and selected according to the grouping strategy of the test modules, for example, the number of test vector patterns is selected as the grouping basis in the shortest test time grouping strategy, and power consumption is selected as the grouping basis in the power consumption optimal grouping strategy.

[0154] In an exemplary embodiment, a high degree of freedom grouping can be implemented through a port multiplexing logic module, achieving a grouping strategy with the shortest test time and saving test costs.

[0155] In this embodiment, all modules are grouped for testing during the chip scan test. The optimal grouping strategy is to make the number of test vectors (patterns) of the test modules in each test group close, that is, the test time of each test module is close, to avoid only one test module being tested in a period of time, wasting test time.

[0156] In this embodiment, it is assumed that there are 8 test modules that need to be tested, the number of EDT channels of each test module is 4, the chip I / O resources are 16, and 4 test modules can be supported for testing at the same time, so the test needs to be divided into two groups.

[0157] Furthermore, Table 1 is an example of the number of patterns of 8 test modules in different test modes. As shown in Table 1, the optimal grouping strategy can be determined in different test modes. For example, in the stuck at mode, modules 0, 1, 2, and 3 are grouped together, and modules 4, 5, 6, and 7 are grouped together in another group; in the transition mode, modules 0, 2, 3, and 4 are grouped together, and modules 1, 5, 6, and 7 are grouped together in another group.

[0158] Table 1:

[0159]

[0160] In the embodiment of the present application, the port multiplexing logic module can realize the dynamic I / O resource redistribution, thereby realizing different groupings of test modules in different test modes. Through the embodiment of the present application, the time used for actual testing can also be effectively reduced, and the test efficiency can be improved.

[0161] In another exemplary embodiment, a high degree of freedom grouping can be achieved through a port multiplexing logic module, thereby realizing a power consumption optimal grouping strategy.

[0162] In this embodiment, the power consumption optimal grouping strategy during the test process is to avoid clustering between the test modules, which would cause the chip to heat up and bring about the problem of voltage drop (IR drop), thereby causing overkill during the test.

[0163] In this embodiment, when grouping, it is necessary to ensure that the power consumption of each test group is evenly distributed as much as possible to avoid excessive power consumption of a certain group.

[0164] In this embodiment, it is assumed that there are 8 test modules that need to be tested, the number of EDT channels of each test module is 4, the chip I / O resources are 16, and 4 test modules can be supported for testing at the same time, so the test needs to be divided into two groups.

[0165] Furthermore, Table 2 is an example of the power consumption and physical location distribution of 8 test modules. As shown in Table 2, according to the optimal power consumption grouping strategy, the test grouping should be adjusted to modules 0, 2, 5, and 7 as one group, and modules 1, 3, 4, and 6 as another group.

[0166] Table 2:

[0167] Module 0 (2W) Module 1(1W) Module 2 (2W) Module 3 (2W) Module 4 (2W) Module 5 (1W) Module 6 (1W) Module 7 (1W)

[0168] In the embodiment of the present application, the port multiplexing logic module can realize the dynamic I / O resource redistribution, thereby realizing the dynamic readjustment of the test module grouping strategy according to the power consumption. Through the embodiment of the present application, the grouping strategy can be dynamically adjusted according to the actual power consumption distribution, the real chip quality can be tested, and the yield rate can be improved.

[0169] In another exemplary embodiment, high-degree-of-freedom grouping can be achieved through a port multiplexing logic module, thereby achieving full coverage testing of cross-talk paths between test modules.

[0170] In this embodiment, in the scan test mode, it is assumed that the cross-talk relationship between the test modules is: modules 0, 1, 2, and 3 have cross-talks with each other; modules 4, 5, 6, and 7 have cross-talks with each other; there is cross-talk between modules 0 and 4; there is cross-talk between modules 1 and 5; there is cross-talk between modules 2 and 6, and there is cross-talk between modules 3 and 7. In order to fully cover all cross-talk paths, the scan test grouping should test the following four groups respectively, modules 0, 1, 2, and 3 are the first group; modules 4, 5, 6, and 7 are the second group; modules 0, 4, 1, and 5 are the third group; and modules 2, 6, 3, and 7 are the fourth group.

[0171] In the embodiment of the present application, the port multiplexing logic module can realize the redistribution of dynamic I / O resources, meet the needs of multiple module grouping, and then realize the full coverage test of cross-talk path crossing between test modules. Through the embodiment of the present application, all test paths can be covered, the accuracy of the test can be improved, and it is beneficial to the screening of chips.

[0172] An embodiment of the present application further provides an electronic device, which includes the chip in any one of the above embodiments.

[0173] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0174] The above is only an exemplary embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip, characterized in that: The chip includes a plurality of chip ports, a port multiplexing logic module and a scan test logic module, wherein: The port multiplexing logic module has multiple groups of first ports and multiple groups of second ports, and the multiple chip ports are divided into multiple groups according to a preset granularity; Each group of chip ports is connected to at least one of the multiple groups of first ports and the multiple groups of second ports of the port multiplexing logic module, and the multiple groups of first ports or the multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module; The port multiplexing logic module is used to control the gating of the path between the chip port and the scan test logic module in units of the preset granularity according to the control instruction.

2. The chip according to claim 1, characterized in that: The plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, wherein i is less than j, and i and j are positive integers; In the case where the chip port is a chip input port, the multiple groups of first ports of the port multiplexing logic module are multiple groups of input ports, and the multiple groups of second ports of the port multiplexing logic module are multiple groups of output ports, each group of chip ports is connected to at least one group of the multiple groups of first ports of the port multiplexing logic module, the multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is i+1, and the number of output port groups of the port multiplexing logic module is j+1.

3. The chip according to claim 2, characterized in that: The port multiplexing logic module comprises j+1 first multiplexer groups, wherein each of the first multiplexer groups is connected to i+1 input port groups of the port multiplexing logic module, and each of the first multiplexer groups is connected to one output port group of the port multiplexing logic module; The first multiplexer group is used to select a target input port group and a corresponding target output port group among the i+1 input port groups according to the control instruction.

4. The chip according to claim 3, characterized in that: When the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the first multiplexer groups includes N first multiplexers.

5. The chip according to claim 2, characterized in that: The port multiplexing logic module comprises i+1 first demultiplexer groups and j+1 OR operation modules, wherein each of the first demultiplexer groups is connected to one input port group of the port multiplexing logic module, each of the first demultiplexer groups is connected to the j+1 OR operation modules, and each of the OR operation modules is connected to one of the output port groups of the port multiplexing logic module; The first demultiplexer group is used to select a target output port group and a corresponding target input port group among the j+1 output port groups according to the control instruction.

6. The chip according to claim 5, characterized in that: When the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the first demultiplexer groups includes N first demultiplexers.

7. The chip according to claim 1, characterized in that: The plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, wherein i is less than j, and i and j are positive integers; In the case where the chip port is a chip output port, the multiple groups of second ports of the port multiplexing logic module are multiple groups of output ports, and the multiple groups of first ports of the port multiplexing logic module are multiple groups of input ports, each group of chip ports is connected to at least one group of the multiple groups of second ports of the port multiplexing logic module, the multiple groups of first ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is j+1, and the number of output port groups of the port multiplexing logic module is i+1.

8. The chip according to claim 7, characterized in that: The port multiplexing logic module includes i+1 second multiplexer groups, wherein each of the second multiplexer groups is connected to j+1 input port groups of the port multiplexing logic module, and each of the second multiplexer groups is connected to one output port group of the port multiplexing logic module; The second multiplexer group is used to select a target input port group and a corresponding target output port group among the j+1 input port groups according to the control instruction.

9. The chip according to claim 8, characterized in that: When the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the second multiplexer groups includes N second multiplexers.

10. The chip according to claim 7, characterized in that: The port multiplexing logic module comprises j+1 second demultiplexer groups and i+1 OR operation modules, wherein each of the second demultiplexer groups is connected to one input port group of the port multiplexing logic module, each of the second demultiplexer groups is connected to i+1 OR operation modules, and each of the OR operation modules is connected to one of the output port groups of the port multiplexing logic module; The second demultiplexer group is used to select a target output port group and a corresponding target input port group among the i+1 output port groups according to the control instruction.

11. The chip according to claim 10, characterized in that: When the preset granularity is N, each of the input port groups includes N input ports, each of the output port groups includes N output ports, and each of the second demultiplexer groups includes N second demultiplexers.

12. The chip according to any one of claims 1 to 11, characterized in that: The scan test logic module includes: multiple embedded deterministic test EDT channel chains, wherein the multiple EDT channel chains are divided into multiple groups according to the preset granularity; the scan test logic module is used to test the multiple groups of EDT channel chains that are connected to the chip port.

13. The chip according to claim 12, characterized in that: The scan test logic module includes multiple scan test modules, each of which contains at least one EDT channel chain; the scan test logic module is used to test each test group in a plurality of test groups at different times, each of which contains at least one EDT channel chain group, and the plurality of test groups are allocated according to the attribute parameters of the plurality of scan test modules.

14. The chip according to claim 13, characterized in that: The chip further comprises: The controller is used to send the control instruction to the port multiplexing logic module.

15. An electronic device, characterized in that: The electronic device comprises the chip described in any one of claims 1 to 14.

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