Hardware consistency screening method and device, equipment and medium

Abstract

The invention relates to the technical field of computers, and discloses a hardware consistency screening method, device and equipment and a medium, the method comprises the following steps: fixing the phase of a data strobe signal in a first double-rate synchronous dynamic random access memory DDR in a first-stage sub-cycle, and in each cycle round, determining the phase of the data strobe signal in the first-stage sub-cycle; selecting a delay value corresponding to each cycle round from a plurality of pre-configured delay values for a delay phase of a first data bit in the first DDR, and sequentially starting and executing a continuous write-in command to obtain a write data code stream; after the write data code stream is obtained each time, starting and executing a continuous reading command to obtain a read data code stream; further determining a minimum delay value and a maximum delay value; sequentially determining a first candidate delay value and a target delay value corresponding to each data bit of each DDR in the plurality of DDRs; and performing statistical analysis on the target delay value, and determining a screening threshold value. The method can improve the accuracy and reliability of data.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a hardware consistency screening method, device, equipment and medium. Background Art

[0002] Double Data Rate (DDR) has become an indispensable component in modern circuit design due to its fast access speed, small size, and relatively low price. DDR is divided into conventional DDR, Low Power Double Data Rate (LPDDR), and Graphics Double Data Rate (GDDR).

[0003] The data in DDR is transmitted on both edges. To ensure the object operation between the source synchronous clock and the data signal at the receiving end, it can be achieved by setting the DQS delay parameter. In the related art, the method of obtaining the DQS delay parameter has the characteristics of simple and fast implementation, but it also has certain defects. For example, for the same PCB board, when it is powered on multiple times, there may be different training results. The set delay step is relatively large, and it is easy to have a large gap between the delay values ​​obtained multiple times. No matter which delay value is selected, the impact on whether the data can be read correctly will be relatively large. In addition, when the hardware consistency problem is prominent, the delay parameter difference is large, such as the application-specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC), which has a long design iteration cycle and high development cost. It is a relatively complex electronic device. There are certain difficulties in production and manufacturing, and there are objective production consistency problems. In actual applications, consistency problems may cause DDR to work unstably. Summary of the invention

[0004] In view of this, the present invention provides a hardware consistency screening method, apparatus, device and medium to solve the problem that the consistency of devices cannot be accurately evaluated, and thus the qualified devices cannot be screened out, which may cause unstable DDR operation.

[0005] In a first aspect, the present invention provides a hardware consistency screening method, the method comprising:

[0006] In the first-level sub-cycle, the phase of the data selection signal in the first DDR is fixed, and in each cycle round, the delay phase of the first data bit in the first DDR is selected from a plurality of pre-configured delay values ​​corresponding to each cycle round, and continuous write commands are sequentially started and executed to obtain a write data code stream; and after each write data code stream is obtained, a continuous read command is started and executed to obtain a read data code stream;

[0007] Determine a minimum delay value corresponding to a first data bit according to a write data code stream and a read data code stream obtained in one or more cycles; and after determining the minimum delay value, determine a maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more cycles; wherein the first DDR is any one of the multiple DDRs, and the first data bit is any one of the multiple data bits included in the first DDR;

[0008] Determine a first candidate delay value corresponding to the first data bit according to the minimum delay value and the maximum delay value, and terminate the operation of the current level sub-cycle;

[0009] After continuously executing the same number of first-level sub-cycles as the number of data bits included in the first DDR and obtaining the first candidate delay value corresponding to each data bit in the first DDR, determining that the current second-level sub-cycle ends, wherein the second-level sub-cycle includes multiple first-level sub-cycles;

[0010] After executing multiple secondary sub-cycle operations, multiple candidate delay values ​​corresponding to each data bit included in the first DDR are respectively obtained;

[0011] According to a plurality of candidate delay values ​​corresponding to the respective data bits included in the first DDR, a target delay value corresponding to each data bit of the first DDR is selected respectively, and the current three-level sub-cycle ends the operation;

[0012] After executing the plurality of three-stage sub-cycle operations, obtaining target delay values ​​corresponding to respective data bits of each DDR in the plurality of DDRs;

[0013] Statistical analysis is performed on target delay values ​​corresponding to each data bit of each DDR in the multiple DDRs to determine a screening threshold, wherein the screening threshold is used to screen out hardware devices that meet hardware consistency.

[0014] The hardware consistency screening method provided by the present invention has the following advantages:

[0015] By fixing the phase of the data strobe signal and selecting different delay values ​​in each cycle, the write data code stream and the read data code stream are obtained. Then, the minimum delay value and the maximum delay value are determined according to these data code streams. Next, the first candidate delay value is determined according to the minimum delay value and the maximum delay value, and the first candidate delay value of each data bit is obtained after the first-level sub-cycle ends. In the second-level sub-cycle, the above process is repeated to obtain multiple candidate delay values. Finally, in the third-level sub-cycle, the target delay value of each data bit is selected according to the multiple candidate delay values, and the target delay value of each data bit of each DDR in multiple DDRs is statistically analyzed to determine the screening threshold. By accurately adjusting the phase and delay value of the data strobe signal, errors and interference in data transmission can be reduced, and the accuracy and reliability of data can be improved. Determine the optimal delay value for each data bit to make data transmission more efficient, thereby improving the performance of the entire system. By statistically analyzing the target delay value of each data bit in multiple DDRs and determining the screening threshold, hardware devices that meet hardware consistency can be quickly screened out, hardware consistency risks can be eliminated early, and product quality and stability can be improved. This solution can adapt to different DDR types and hardware configurations, and has strong versatility and scalability. Moreover, ensuring the stability and reliability of data transmission can also reduce system failures and performance degradation caused by hardware inconsistencies.

[0016] In an optional implementation manner, determining a minimum delay value corresponding to the first data bit according to the write data code stream and the read data code stream acquired in one or more cyclic rounds specifically includes:

[0017] Compare the write data code stream and the read data code stream obtained in each cycle round;

[0018] When it is first determined that the write data code stream and the read data code stream generated in the first cycle are the same, the delay value corresponding to the first cycle is determined to be the minimum delay value corresponding to the first data bit, wherein the first cycle is any cycle within the first-level sub-cycle.

[0019] Specifically, by comparing the write data code stream and the read data code stream obtained in each cycle, the cycle in which the write data code stream and the read data code stream are the same for the first time can be accurately found. Ensure that the determined minimum delay value is the minimum value actually corresponding to the first data bit, and improve the accuracy of the delay setting. The method is applicable to any cycle in the first-level sub-cycle and has high flexibility. Regardless of which cycle the write data code stream and the read data code stream first appear to be the same, the delay value corresponding to the cycle can be determined as the minimum delay value. This enables the method to adapt to different data transmission situations and system configurations. Determining the minimum delay value helps optimize system performance. By setting a suitable delay value, the delay and jitter in data transmission can be reduced, and the accuracy and reliability of data can be improved. Determining the minimum delay value can help the system reduce the delay as much as possible while meeting performance requirements. The method can be applied to multiple data bits or other similar scenarios. By performing similar cycle rounds and comparisons on each data bit, the minimum delay value of each data bit can be determined, thereby achieving delay optimization of the entire system. Since the method takes into account the actual data transmission situation of each cycle, it can adapt to changes in factors such as system load and data transmission rate. If system conditions change, re-execution of the loop rounds and comparisons can update the minimum delay value to maintain optimal performance of the system.

[0020] In an optional implementation, after determining the minimum delay value, determining the maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more cyclic rounds specifically includes:

[0021] After determining the minimum delay value, continue to sequentially execute the continuous write command to obtain the write data code stream, and after each write data code stream is obtained, start and execute the continuous read command to obtain the read data code stream;

[0022] After obtaining the write data code stream and the read data code stream in the second cycle round, the write data code stream and the read data code stream obtained in the second cycle round are compared, wherein the second cycle round is any cycle round after the minimum delay value is obtained in the first-level sub-cycle;

[0023] When the write data code stream and the read data code stream acquired in the second cycle are different, the delay value corresponding to the second cycle is determined to be the maximum delay value corresponding to the first data bit.

[0024] Specifically, by continuing to perform loop rounds after determining the minimum delay value, and comparing the write data code stream and the read data code stream of each round, the loop round in which the write data code stream and the read data code stream are different for the first time can be accurately found. Ensure that the determined maximum delay value is the maximum value actually corresponding to the first data bit, and improve the accuracy of the delay setting. The method is applicable to any loop round in the first-level sub-loop and has high flexibility. Regardless of which loop round the write data code stream and the read data code stream are different for the first time, the delay value corresponding to the round can be determined as the maximum delay value. The method can be adapted to different data transmission situations and system configurations. Determining the maximum delay value helps optimize system performance. By setting a suitable delay value, the efficiency of data transmission can be improved as much as possible while meeting data accuracy and reliability. Determining the maximum delay value can help the system minimize delay without affecting performance. The method can be applied to multiple data bits or other similar scenarios. By performing similar loop rounds and comparisons on each data bit, the maximum delay value of each data bit can be determined, thereby achieving delay optimization of the entire system. Since the method takes into account the actual data transmission situation of each loop round, it can adapt to changes in factors such as system load and data transmission rate. If system conditions change, re-execution of the loop rounds and comparisons can update the maximum delay value to maintain optimal performance of the system.

[0025] In an optional implementation manner, determining a first candidate delay value corresponding to the first data bit according to the minimum delay value and the maximum delay value specifically includes:

[0026] An average value is determined according to the minimum delay value and the maximum delay value as a first candidate delay value corresponding to the first data bit.

[0027] Specifically, by taking the average of the minimum delay value and the maximum delay value as the first candidate delay value, a balance can be achieved between delay and performance. This can avoid excessive delays that cause system performance degradation, while also ensuring a certain degree of delay tolerance. Using the average value can reduce the impact of extreme values ​​on delay settings. If only the minimum delay value or the maximum delay value is considered, it may be affected by abnormal conditions or instantaneous fluctuations, resulting in unstable delay settings. The average value can provide a more stable delay reference. This helps maintain good performance under different system environments and workloads.

[0028] In an optional implementation, according to a plurality of candidate delay values ​​corresponding to the respective data bits included in the first DDR, respectively selecting a target delay value corresponding to each data bit of the first DDR, specifically includes:

[0029] Counting the number of occurrences of each candidate delay value among multiple candidate delay values ​​corresponding to each data bit;

[0030] A candidate delay value whose occurrence times are greater than or equal to a preset threshold is selected from the multiple candidate delay values ​​corresponding to each data bit as the target delay value corresponding to the data bit.

[0031] Specifically, by counting the number of occurrences of the candidate delay value corresponding to each data bit, and selecting the candidate delay value whose number of occurrences is greater than or equal to the preset threshold as the target delay value, the reliability of the delay setting can be improved. Candidate delay values ​​with more occurrences are usually more representative of the actual delay requirements of the data bit, thereby reducing the impact of abnormal values ​​or noise on the delay setting. This helps to ensure the stability of the delay setting. By selecting candidate delay values ​​with more occurrences, it is possible to avoid excessive impact of individual abnormal or unstable delay values ​​on system performance. Improve the stability and consistency of the system under different working conditions. This method has certain adaptability to different data transmission situations. Even in different test or operating environments, candidate delay values ​​with more occurrences can still reflect the common delay requirements of the data bit. It helps the system maintain good performance in different situations. Ensure that the system can transmit data with the best delay setting in most cases, improve the accuracy and reliability of data, and thus improve the overall performance of the system.

[0032] In an optional implementation, the method further includes: storing the first candidate delay value in a preset storage device;

[0033] And, the target delay value corresponding to each data bit of the first DDR is stored in a preset storage device respectively.

[0034] In an optional implementation, in every two adjacent cycles, the delay value corresponding to the latter cycle is the sum of the delay value corresponding to the previous cycle and a preset delay step length;

[0035] In the first-level sub-cycle, the phase of the data strobe signal in the first DDR is fixed, and before selecting the delay value corresponding to each cycle round from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR in each cycle round, the method further includes:

[0036] Acquire an influencing factor corresponding to the delay value, wherein the influencing factor includes any one of a data transmission rate, a data type, and a system load, wherein the data type is determined based on the impact, real-timeness, and sensitivity of the data;

[0037] According to the influencing factors, a calculation formula corresponding to the preset delay step length is matched;

[0038] According to the calculation formula, determine the preset delay step length within the first-level sub-cycle;

[0039] The calculation formula corresponding to the preset delay step size includes the following:

[0040] Preset delay step = minimum delay step + (data transmission rate / maximum transmission rate) * (maximum delay step - minimum delay step);

[0041] or,

[0042] Preset delay step = standard delay step * data type weight;

[0043] Among them, the standard delay step is a preconfigured benchmark delay step, the preset delay step is applicable to all first-level sub-cycles, the minimum delay step, the maximum transmission rate, the maximum delay step, the standard delay step, and the data type weight corresponding to the data type are preconfigured data.

[0044] Specifically, by considering influencing factors such as data transmission rate and data type, the preset delay step can be dynamically adjusted according to actual conditions. This enables the delay setting to better adapt to different system operating conditions and data transmission requirements, thereby improving the adaptability and flexibility of the system. Determining the preset delay step based on influencing factors can optimize system performance. For example, when the data transmission rate is high, appropriately increasing the delay step can avoid data conflicts and errors; for different types of data, the delay step can be adjusted according to its importance and real-time requirements to ensure the accuracy and timeliness of the data. By using the same calculation formula and standard delay step, it can be ensured that a consistent preset delay step is used in all first-level sub-cycles. This helps to maintain the stability and consistency of the system in different stages and different operations.

[0045] In a second aspect, the present invention provides a hardware consistency screening device, the device comprising:

[0046] A selection module is used to fix the phase of the data selection signal in the first DDR in the first sub-cycle, and select a delay value corresponding to each cycle round from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR in each cycle round;

[0047] A start module is used to start and execute continuous write commands in sequence to obtain write data code streams; and after each write data code stream is obtained, start and execute continuous read commands to obtain read data code streams;

[0048] A processing module is used to determine a minimum delay value corresponding to a first data bit according to a write data code stream and a read data code stream obtained in one or more loop rounds; and after determining the minimum delay value, determine a maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more loop rounds; wherein the first DDR is any one of the multiple DDRs, and the first data bit is any one of the multiple data bits included in the first DDR; determine a first candidate delay value corresponding to the first data bit according to the minimum delay value and the maximum delay value, and end the operation of the current level sub-cycle; when the same number of multiple data bits as the first DDR is continuously executed The first-level sub-cycle is executed, and after obtaining the first candidate delay value corresponding to each data bit in the first DDR, the current second-level sub-cycle is determined to end the operation, wherein the second-level sub-cycle includes multiple first-level sub-cycles; after executing multiple second-level sub-cycle operations, multiple candidate delay values ​​corresponding to each data bit included in the first DDR are respectively obtained; according to the multiple candidate delay values ​​corresponding to each data bit included in the first DDR, the target delay value corresponding to each data bit of the first DDR is respectively selected, and the current third-level sub-cycle ends the operation; after executing multiple third-level sub-cycle operations, the target delay value corresponding to each data bit of each DDR in the multiple DDRs is obtained;

[0049] The analysis module is used to perform statistical analysis on the target delay values ​​corresponding to each data bit of each DDR in the multiple DDRs, and determine a screening threshold, wherein the screening threshold is used to screen out hardware devices that meet the hardware consistency.

[0050] The hardware consistency screening device provided by the present invention has the following advantages:

[0051] By fixing the phase of the data strobe signal and selecting different delay values ​​in each cycle, the write data code stream and the read data code stream are obtained. Then, the minimum delay value and the maximum delay value are determined according to these data code streams. Next, the first candidate delay value is determined according to the minimum delay value and the maximum delay value, and the first candidate delay value of each data bit is obtained after the first-level sub-cycle ends. In the second-level sub-cycle, the above process is repeated to obtain multiple candidate delay values. Finally, in the third-level sub-cycle, the target delay value of each data bit is selected according to the multiple candidate delay values, and the target delay value of each data bit of each DDR in multiple DDRs is statistically analyzed to determine the screening threshold. By accurately adjusting the phase and delay value of the data strobe signal, errors and interference in data transmission can be reduced, and the accuracy and reliability of data can be improved. Determine the optimal delay value for each data bit to make data transmission more efficient, thereby improving the performance of the entire system. By statistically analyzing the target delay value of each data bit in multiple DDRs and determining the screening threshold, hardware devices that meet hardware consistency can be quickly screened out, hardware consistency risks can be eliminated early, and product quality and stability can be improved. This solution can adapt to different DDR types and hardware configurations, and has strong versatility and scalability. Moreover, ensuring the stability and reliability of data transmission can also reduce system failures and performance degradation caused by hardware inconsistencies.

[0052] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the hardware consistency screening method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0053] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the hardware consistency screening method of the first aspect or any corresponding embodiment thereof.

[0054] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the hardware consistency screening method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 It is a flowchart of a hardware consistency screening method provided by an embodiment of the present invention;

[0057] Figure 2 is a flow chart of another hardware consistency screening method provided by an embodiment of the present invention;

[0058] Figure 3 It is a flowchart of another hardware consistency screening method provided by an embodiment of the present invention;

[0059] Figure 4 It is a schematic diagram of the overall architecture of the hardware consistency screening method provided by the present invention;

[0060] Figure 5 is a schematic diagram of an exemplary partial method flow of the hardware consistency screening method provided by the present invention;

[0061] Figure 6 It is a structural block diagram of a hardware consistency screening device provided by an embodiment of the present invention;

[0062] Figure 7 It is a schematic diagram of the hardware structure of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0064] DDR has become an indispensable component in modern circuit design due to its advantages such as fast access speed, small size and relatively low price. DDR is divided into conventional DDR, Low Power Double Data Rate SDRAM (LPDDR) and Graphics Double Data Rate DRAM (GDDR).

[0065] The data in DDR is transmitted on both edges, and the source synchronous clock DQS is used to sample the data signal DQ. When reading DDR, the DDR particle output DQS is aligned with the DQ edge, and the DDR controller or PHY as the data receiving end implements the operation of aligning the DQS edge with the DQ center.

[0066] Specifically, in DDR, data is transmitted in a dual-edge transmission mode, which means that data can be transmitted on both the rising edge and the falling edge of the clock signal, thereby increasing the data transmission rate.

[0067] In order to ensure accurate data sampling, the source synchronous clock DQS (Data Strobe) is used. DQS is a clock signal synchronized with the data signal DQ and is used to indicate the valid edge of the data. When reading DDR, the DDR particles (memory chips) will output the DQS signal, and the DQS and DQ edges are aligned.

[0068] However, the DDR controller or PHY (physical layer) as the data receiving end needs to implement the operation of aligning the DQS edge with the DQ center. This is because when receiving data, in order to improve the sampling accuracy, it is usually hoped to sample at the center of the data signal rather than at the edge. By aligning the DQS edge with the DQ center, data changes can be better captured and sampling errors can be reduced.

[0069] In the related art, the method of obtaining DQS delay parameters has the characteristics of simple and fast implementation, but it also has certain defects. For the same PCB board, there may be different training results when it is powered on multiple times; the set delay step is relatively large, and it is easy for the gap between the delay values ​​obtained multiple times to be large. No matter which delay value is selected, it will have a greater impact on whether the data can be read correctly. In addition, when the hardware consistency problem is prominent, the delay parameters vary greatly. For example, ASIC has a long design iteration cycle and high development cost. It is a relatively complex electronic device. There are certain difficulties in production and manufacturing, and there are objective production consistency problems. In actual applications, consistency problems may cause DDR to work unstable. Therefore, early troubleshooting of consistency risks has certain practical significance.

[0070] To solve the above problems, an embodiment of the present invention provides a hardware consistency screening embodiment. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system (computer device) including a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0071] In this embodiment, a hardware consistency screening method is provided, which can be used for the above-mentioned terminal devices, such as mobile phones, tablet computers, etc. Figure 1 is a flowchart of a hardware consistency screening method provided by an embodiment of the present invention, such as Figure 1 As shown, the process includes the following steps:

[0072] Step S101, within the first-level sub-cycle, fix the phase of the data selection signal in the first DDR, and in each cycle round, select the delay value corresponding to each cycle round from the pre-configured multiple delay values ​​for the delay phase of the first data bit in the first DDR, and start and execute continuous write commands in sequence to obtain the write data code stream.

[0073] Step S102, after each acquisition of the write data code stream, start and execute the continuous read command to acquire the read data code stream.

[0074] Specifically, in the process of obtaining the preset threshold during the entire training process, the DDR includes multiple, the first DDR is any one of the multiple DDRs, and each DDR includes multiple data bits. Therefore, the first data bit is any one of the multiple data bits included in the first DDR.

[0075] In the embodiment of the present application, the first data in the first DDR is used as an example to illustrate how to obtain the maximum delay value and the minimum delay value. In fact, each data bit in all DDRs needs to perform similar steps to obtain the maximum delay value and the minimum delay value, and then determine the target delay value corresponding to the data bit according to the maximum delay value and the minimum delay value. The specific implementation process will be described in detail one by one below. First, the phase of the data strobe signal (Data Strobe Signal, DQS for short) in the first DDR is fixed in the first-level sub-cycle. Then, in each cycle, the delay phase of the first data bit (that is, the first data queue, Data Queue, DQ for short) in the first DDR is selected from the pre-configured multiple delay values ​​corresponding to each cycle, and the continuous write command is started and executed in sequence to obtain the write data code stream.

[0076] Among them, the first data bit can first start with an initial delay value among multiple preconfigured delay values ​​in the cycle, and then start a continuous write command to obtain a write data code stream. After that, a continuous read command is executed to obtain a read data code stream. Subsequently, the delay value needs to be changed every time a cycle round passes. In an optional example, in each of two adjacent cycle rounds, the delay value corresponding to the next cycle round can be configured to be the sum of the delay value corresponding to the previous cycle round and the preset delay step.

[0077] Step S103: determining a minimum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more cycles.

[0078] Specifically, after obtaining the write data code stream and the read data code stream in each cycle, it is necessary to determine whether the current delay value is the minimum delay value corresponding to the first data bit according to the write data code stream and the read data code stream.

[0079] In an optional example, the write data code stream and the read data code stream can be compared to confirm whether the two are the same to determine whether the current cycle round is the target cycle round. When it is confirmed to be the target cycle round, it can be determined that the delay value corresponding to the target cycle round is the minimum delay value corresponding to the first data.

[0080] Step S104, after determining the minimum delay value, determine the maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more cycles.

[0081] Specifically, similar to the principle of determining the minimum delay value, after determining the minimum delay value, the write data code stream and the read data code stream obtained in one or more cycles can be compared, and the delay value corresponding to the different cycles of the write data stream and the read data stream can be selected as the maximum delay value.

[0082] Step S105, determining a first candidate delay value corresponding to the first data bit according to the minimum delay value and the maximum delay value, and the current level sub-cycle ends the operation.

[0083] Specifically, in order to avoid selecting a minimum delay value or a maximum delay value, in the subsequent operation process, the DDR operation may become unstable due to the selected delay value being too large or too small. Therefore, in the present application scheme, it is also necessary to determine the first candidate delay value corresponding to the first data bit based on the minimum delay value and the maximum delay value.

[0084] Step S106, after the first-level sub-cycles having the same number as the plurality of data bits included in the first DDR are continuously executed and the first candidate delay value corresponding to each data bit in the first DDR is obtained, it is determined that the current second-level sub-cycle ends.

[0085] Specifically, as described above, the first DDR includes multiple data bits, and each data bit needs to perform the above operation in a certain first-level sub-cycle, so as to obtain the candidate delay value corresponding to itself and then end the operation. That is, the current second-level sub-cycle ends the operation. Among them, the second-level sub-cycle includes multiple first-level sub-cycles, and the number of first-level sub-cycles included in the second-level sub-cycle is the same as the number of data bits in the first DDR.

[0086] Step S107, after executing multiple secondary sub-cycle operations, respectively obtain multiple candidate delay values ​​corresponding to each data bit included in the first DDR.

[0087] Specifically, in order to ensure that the preset threshold value determined subsequently is more accurate, after executing any of the aforementioned secondary sub-cycles to obtain candidate delay values ​​corresponding to the respective data bits included in the first DDR, the method may further include repeatedly executing the aforementioned secondary sub-cycle operation again. After executing the secondary sub-cycle operation multiple times, multiple candidate delay values ​​corresponding to the respective data bits included in the first DDR can be obtained.

[0088] Step S108 , according to a plurality of candidate delay values ​​corresponding to the respective data bits included in the first DDR, respectively select a target delay value corresponding to each data bit of the first DDR, and the current three-level sub-cycle ends the operation.

[0089] Specifically, after multiple candidate delay values ​​have been acquired for each data bit in the first DDR, one or more candidate delay values ​​may be selected from the multiple candidate delay values ​​as target delay values ​​corresponding to each data bit.

[0090] Step S109, after executing multiple three-stage sub-cycle operations, obtaining target delay values ​​corresponding to each data bit of each DDR in the multiple DDRs.

[0091] Specifically, as described above, the first DDR is actually any one of the multiple DDRs, and therefore, the aforementioned steps 101 to 108 are all exemplary operations described by taking the first DDR as an example. In fact, multiple DDRs need to perform operations similar to steps 101 to 108. Assuming that the operations of steps 101 to 108 are understood as a three-level sub-cycle, multiple three-level sub-cycles equal to the number of DDRs need to be performed in multiple DDRs. Then, the target delay values ​​corresponding to each data bit of each DDR in the multiple DDRs can be obtained.

[0092] Step S110 , statistically analyzing the target delay values ​​corresponding to each data bit of each DDR in the plurality of DDRs to determine a screening threshold.

[0093] The screening threshold is used to screen out hardware devices that meet the hardware consistency requirements.

[0094] Specifically, when performing statistical analysis on the target delay values ​​corresponding to each data bit of each DDR in multiple DDRs, the statistical analysis can be performed using the Three Sigma Rule. Finally, the analysis result is obtained, and the analysis result is the screening threshold. The specific process of performing statistical analysis using the Three Sigma Rule will not be described in detail here.

[0095] Subsequently, in the application process, the target delay value of a DDR to be confirmed can be obtained through steps similar to step 101 to step 109, and then the target delay value is compared with the screening threshold to determine whether the hardware device to which the DDR belongs meets the hardware consistency requirements.

[0096] The hardware consistency screening method provided in this embodiment obtains the write data code stream and the read data code stream by fixing the phase of the data selection signal and selecting different delay values ​​in each cycle round. Then, the minimum delay value and the maximum delay value are determined according to these data code streams. Next, the first candidate delay value is determined according to the minimum delay value and the maximum delay value, and the first candidate delay value of each data bit is obtained after the first-level sub-cycle ends. In the second-level sub-cycle, the above process is repeated to obtain multiple candidate delay values. Finally, in the third-level sub-cycle, the target delay value of each data bit is selected according to the multiple candidate delay values, and the target delay value of each data bit of each DDR in multiple DDRs is statistically analyzed to determine the screening threshold. By accurately adjusting the phase and delay value of the data selection signal, errors and interference in data transmission can be reduced, and the accuracy and reliability of data can be improved. Determine the optimal delay value for each data bit to make data transmission more efficient, thereby improving the performance of the entire system. By statistically analyzing the target delay value of each data bit in multiple DDRs and determining the screening threshold, hardware devices that meet hardware consistency can be quickly screened out, hardware consistency risks can be eliminated early, and product quality and stability can be improved. This solution can adapt to different DDR types and hardware configurations, and has strong versatility and scalability. Moreover, it ensures the stability and reliability of data transmission and can also reduce system failures and performance degradation caused by hardware inconsistencies.

[0097] In this embodiment, a hardware consistency screening method is provided, which can be used for the above-mentioned mobile terminals, such as mobile phones, tablet computers, etc. Figure 2 FIG. 1 is a flow chart of a hardware consistency screening method provided by an embodiment of the present invention. Figure 2 As shown, based on the foregoing embodiment, determining the minimum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more cycles may include the following steps:

[0098] Step S201, comparing the write data code stream and the read data code stream obtained in each cycle round.

[0099] Step S202: when it is determined for the first time that the write data code stream and the read data code stream generated in the first cycle are the same, determining that the delay value corresponding to the first cycle is the minimum delay value corresponding to the first data bit.

[0100] Specifically, if the write data code stream and the read data code stream generated in the first cycle are the same, then the delay value corresponding to the first cycle can be determined to be the minimum delay value corresponding to the first data bit. The first cycle can be any cycle in the first-level sub-cycle.

[0101] A hardware consistency screening method provided by an embodiment of the present invention can accurately find the first cycle round in which the write data code stream and the read data code stream are the same by comparing the write data code stream and the read data code stream obtained in each cycle round. Ensure that the determined minimum delay value is the minimum value actually corresponding to the first data bit, and improve the accuracy of the delay setting. The method is applicable to any cycle round in a primary sub-cycle and has high flexibility. Regardless of which cycle round the write data code stream and the read data code stream are the same for the first time, the delay value corresponding to the round can be determined as the minimum delay value. This enables the method to adapt to different data transmission situations and system configurations. Determining the minimum delay value helps to optimize system performance. By setting a suitable delay value, the delay and jitter in data transmission can be reduced, and the accuracy and reliability of data can be improved. Determination of the minimum delay value can help the system reduce the delay as much as possible while meeting performance requirements. The method can be applied to multiple data bits or other similar scenarios. By performing similar cycle rounds and comparisons on each data bit, the minimum delay value of each data bit can be determined, thereby achieving delay optimization of the entire system. Since the method takes into account the actual data transmission situation of each cycle round, it can adapt to changes in factors such as system load and data transmission rate. If system conditions change, re-execution of the loop rounds and comparisons can update the minimum delay value to maintain optimal performance of the system.

[0102] In this embodiment, a hardware consistency screening method is provided, which can be used for the above-mentioned mobile terminals, such as mobile phones, tablet computers, etc. Figure 3 is a flowchart of a hardware consistency screening method provided by an embodiment of the present invention, such as Figure 3 As shown, after determining the minimum delay value, determining the maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more cycles may include the following steps:

[0103] Step S301, after determining the minimum delay value, continue to sequentially execute continuous write commands to obtain write data code streams, and after each write data code stream is obtained, start and execute continuous read commands to obtain read data code streams.

[0104] Step S302: after obtaining the write data code stream and the read data code stream in the second cycle, the write data code stream and the read data code stream obtained in the second cycle are compared.

[0105] Step S303: when the write data code stream and the read data code stream acquired in the second cycle are different, determining the delay value corresponding to the second cycle as the maximum delay value corresponding to the first data bit.

[0106] Specifically, after determining the minimum delay value, further increase the delay value, and then enter the next cycle test to obtain the write data code stream and the read data code stream. Until it is determined that the write data code stream and the read data code stream are the same in the previous cycle, and become different in the current cycle, it is determined that the current cycle, that is, the delay value corresponding to the second cycle is the maximum delay value. The second cycle is any cycle after the minimum delay value is obtained in the first-level sub-cycle.

[0107] By continuing to perform loop rounds after determining the minimum delay value and comparing the write data code stream and the read data code stream of each round, the loop round in which the write data code stream and the read data code stream are different for the first time can be accurately found. It is ensured that the determined maximum delay value is the maximum value actually corresponding to the first data bit, and the accuracy of the delay setting is improved. The method is applicable to any loop round in the first-level sub-loop and has high flexibility. Regardless of which loop round the write data code stream and the read data code stream are different for the first time, the delay value corresponding to the round can be determined as the maximum delay value. The method can be adapted to different data transmission situations and system configurations. Determining the maximum delay value helps optimize system performance. By setting a suitable delay value, the efficiency of data transmission can be improved as much as possible while meeting data accuracy and reliability. Determining the maximum delay value can help the system minimize delay without affecting performance. The method can be applied to multiple data bits or other similar scenarios. By performing similar loop rounds and comparisons on each data bit, the maximum delay value of each data bit can be determined, thereby achieving delay optimization of the entire system. Since the method takes into account the actual data transmission situation of each loop round, it can adapt to changes in factors such as system load and data transmission rate. If system conditions change, re-execution of the loop rounds and comparisons can update the maximum delay value to maintain optimal performance of the system.

[0108] In an optional example, determining a first candidate delay value corresponding to the first data bit according to the minimum delay value and the maximum delay value specifically includes:

[0109] An average value is determined according to the minimum delay value and the maximum delay value as a first candidate delay value corresponding to the first data bit.

[0110] Specifically, by taking the average of the minimum delay value and the maximum delay value as the first candidate delay value, a balance can be achieved between delay and performance. This can avoid excessive delays that cause system performance degradation, while also ensuring a certain degree of delay tolerance. Using the average value can reduce the impact of extreme values ​​on delay settings. If only the minimum delay value or the maximum delay value is considered, it may be affected by abnormal conditions or instantaneous fluctuations, resulting in unstable delay settings. The average value can provide a more stable delay reference. This helps maintain good performance under different system environments and workloads.

[0111] In an optional example, according to a plurality of candidate delay values ​​corresponding to the respective data bits included in the first DDR, respectively selecting a target delay value corresponding to each data bit of the first DDR, specifically includes the following method steps:

[0112] Step a1, counting the number of occurrences of each candidate delay value among a plurality of candidate delay values ​​corresponding to each data bit.

[0113] Step a2: selecting a candidate delay value whose occurrence times are greater than or equal to a preset threshold from among the multiple candidate delay values ​​corresponding to each data bit as a target delay value corresponding to the data bit.

[0114] Specifically, by counting the number of occurrences of the candidate delay value corresponding to each data bit and selecting the candidate delay value whose number of occurrences is greater than or equal to a preset threshold as the target delay value, the reliability of the delay setting can be improved.

[0115] Among them, the candidate delay values ​​that appear more often are usually more representative of the actual delay requirements of the data bit, so selecting the candidate delay values ​​whose number of occurrences is greater than or equal to the preset threshold as the target delay value can reduce the impact of abnormal values ​​or noise on the delay setting, thereby helping to ensure the stability of the delay setting.

[0116] The preset number threshold value may be determined, for example, based on the total number of secondary sub-cycles, such as a value obtained by dividing the total number of secondary sub-cycles by 2.

[0117] By selecting candidate delay values ​​that appear more frequently, it is also possible to prevent individual abnormal or unstable delay values ​​from having too great an impact on system performance, thereby improving the stability and consistency of the system under different working conditions.

[0118] Moreover, the method is adaptable to different data transmission situations. Even in different test or operation environments, the candidate delay values ​​that appear more frequently can still reflect the common delay requirements of the data bits. This helps the system maintain good performance in different situations. It ensures that the system can transmit data with the optimal delay setting in most cases, improves the accuracy and reliability of data, and thus improves the overall performance of the system.

[0119] In an optional example, the method may further include:

[0120] Storing the first candidate delay value in a preset storage device;

[0121] And, the target delay value corresponding to each data bit of the first DDR is stored in a preset storage device respectively.

[0122] In an optional example, in each of two adjacent cycles, the delay value corresponding to the latter cycle is the sum of the delay value corresponding to the previous cycle and the preset delay step; in the first-level sub-cycle, the phase of the data strobe signal in the first DDR is fixed, and in each cycle, before the delay phase of the first data bit in the first DDR is selected from the preconfigured multiple delay values ​​to the delay value corresponding to each cycle, the method further includes the following method steps:

[0123] Step b1, obtaining an influencing factor corresponding to the delay value, wherein the influencing factor includes any one of a data transmission rate, a data type, and a system load.

[0124] Among them, the data type is determined based on the impact, real-time and sensitivity of the data.

[0125] Specifically, in addition to the write data stream and the read data stream, other factors may also have a certain impact on the delay value. For example, the preset delay step size. In addition to being determined based on a large amount of experimental data, the preset delay step size can also be determined based on factors such as the data transmission rate, the type of data, and the system load.

[0126] Step b2: matching a calculation formula corresponding to a preset delay step length according to the influencing factors.

[0127] Step b3, determining the preset delay step length within the first-level sub-cycle according to the calculation formula.

[0128] Specifically, the data transmission rate can be obtained by monitoring the actual rate of DDR data transmission and then obtaining it through hardware counters or software measurement tools. Data type: can be determined based on the impact, real-time and sensitivity of the data. For example, critical data can have a higher priority and lower latency requirements, while non-critical data can tolerate higher latency. The evaluation of the system load can include evaluation based on CPU utilization, memory usage, network bandwidth, etc.

[0129] When matching a calculation formula corresponding to a preset delay step length according to the influencing factors, the calculation formula matching the influencing factors may be selected.

[0130] The calculation formula corresponding to the preset delay step size includes the following:

[0131] Preset delay step length = minimum delay step length + (data transmission rate / maximum transmission rate) * (maximum delay step length - minimum delay step length) (Formula 1);

[0132] or,

[0133] Preset delay step length=standard delay step length*data type weight (Formula 2).

[0134] The standard delay step is a preconfigured reference delay step, and the preset delay step is applicable to all first-level sub-cycles.

[0135] Then, by substituting the specific value into the above formula, the preset delay step can be directly obtained. Among them, the minimum delay step, the maximum transmission rate, the maximum delay step, the standard delay step, the data type weight corresponding to the data type, etc. are pre-configured data.

[0136] Wherein, Formula 1 is a formula for determining a preset delay step length based on a data transmission rate, and its meaning includes:

[0137] If the data transmission rate is high, you can select a smaller preset delay step to adjust the delay value more finely to avoid data loss or errors. If the data transmission rate is low, you can select a larger preset delay step to find a suitable delay value more quickly.

[0138] Formula 2 is a formula for determining a preset delay step size based on a data type, and its meaning includes:

[0139] For critical data types (primary data types), a smaller preset delay step can be set to ensure timeliness and accuracy. For non-critical data types (secondary data types), a larger preset delay step can be used to balance system performance and resource utilization.

[0140] By considering influencing factors such as data transmission rate and data type, the preset delay step can be dynamically adjusted according to actual conditions. This enables the delay setting to better adapt to different system operating conditions and data transmission requirements, improving the adaptability and flexibility of the system. Determining the preset delay step based on influencing factors can optimize system performance. For example, when the data transmission rate is high, appropriately increasing the delay step can avoid data conflicts and errors; for different types of data, the delay step can be adjusted according to its importance and real-time requirements to ensure the accuracy and timeliness of the data. By using the same calculation formula and standard delay step, it can be ensured that a consistent preset delay step is used in all first-level sub-cycles. This helps to maintain the stability and consistency of the system in different stages and different operations.

[0141] In an optional example, in addition to determining the preset delay step length in the aforementioned manner, the method may also determine the preset delay step length in the following manner. For details, refer to the following formula:

[0142] Preset delay step size = load adjustment factor * (system load / maximum load) * standard delay step size (Formula 3)

[0143] Formula 3 is a formula for determining a preset delay step size based on the system load, and its meaning includes:

[0144] When the system load is high, a smaller preset delay step size can be selected to reduce the occupation of system resources.

[0145] Alternatively, when the load is low, a larger preset delay step size may be selected to improve the efficiency of the delay adjustment.

[0146] The load adjustment factor and the maximum load are pre-configured data.

[0147] By considering the impact of system load in the above way, we can avoid the problem of insufficient delay under high load conditions, thereby improving the reliability of the system. By adjusting the delay step size according to the load conditions, we can better cope with the situation of tight system resources.

[0148] The above method can be easily expanded and adapted to new influencing factors or requirements. If there are other factors to consider, corresponding calculation formulas can be added or the parameters of existing formulas can be adjusted to meet the continuous development and changes of the system.

[0149] In a specific example, the specific execution of the above method steps can refer to the following example:

[0150] The first step is to fix the DQS phase for DQ0 (the first data bit of the first DDR), confirm the adjustable range of the phase, start the DQ0 delay phase from the minimum delay value, start the continuous write and read commands, and after the write and read commands are completed, compare the DQ0 code stream of the read data with the DQ0 code stream of the write data; if they are the same, determine it as the minimum delay value, if they are different, gradually increase the DQ0 delay phase, and when the comparison result is that the read data DQ0 code stream and the write data DQ0 code stream change from being different in the previous cycle to being the same in this cycle, determine that the delay value of the current cycle is the minimum available delay value of DQ0;

[0151] Then continue to increase the DQ0 phase delay until the read data stream and the write data stream change from being the same to being different. The DQ0 delay at this time is recorded as the maximum available delay value of DQ0.

[0152] In the second step, the average of the available minimum delay value and the available maximum delay value is taken as the phase delay value of DQ0 and written into the RAM cache at address A00.

[0153] Step 3: loop through Step 1 and Step 2 until the delay training of DQ1, ...DQn is completed and written into the RAM cache respectively at addresses A01, ...A0n;

[0154] Step 4: loop through step 1, step 2, and step 3 m-1 times to obtain the training results of DQ0, DQ1, ...DQn for M times, and write the results into the RAM cache at addresses A10, A11, ...A1n, ...A(m-1)0, A(m-1)1, ...A(m-1)n;

[0155] Step 5: Read the RAM cache, count the training results of DQ0, find the value whose number of training results is greater than or equal to M / 2, and write it into the RAM cache as the final training result of DQ0, with the address of B00;

[0156] Step 6: Repeat step 5 to obtain the final training results of DQ1, ...DQn in turn, and write them into the RAM cache at addresses B01, ...B0n;

[0157] Step 7: Manually modify the phase delay of DQ0, DQ1, ...DQn to the result of step 5 and step 6;

[0158] Step 8. Export B00, B01, …B0n.

[0159] In the ninth step, execute the first to eighth steps above for multiple mass-produced boards, export the results in sequence, and perform statistical analysis to obtain the statistical results of the three sigma criterion.

[0160] The tenth step is to write the three-sigma statistical threshold into the mass production board screening test software, and execute the first to eighth steps on the remaining boards in production. If the phase adjustment results exceed the three-sigma criteria, they are regarded as gross errors. The board is considered to have hardware consistency problems and is eliminated for further location and analysis of specific consistency differences.

[0161] See Figure 4 As shown, Figure 4 A schematic diagram illustrating the overall architecture of the hardware consistency screening method.

[0162] Including: PC is connected to ASIC through serial port, ASIC includes DDR controller and PHY, DDR controller stores program code corresponding to specific execution process of hardware consistency screening method. DDR controller establishes communication connection with board through CTRL BUS bus, ADDRBUS bus, and DQ BUS bus to verify the stability of DDR particles, so as to further determine whether there is gross error in the board and whether it needs to be eliminated.

[0163] In a specific example, see Figure 5 As shown, Figure 5 The method flow of steps S001 to S008 below is shown in FIG. Figure 5 Based on this, the corresponding method flow is executed. Figure 5 The specific operation process of steps 9 to 15 is not reflected in the document. The overall method process includes the following implementation steps:

[0164] S001, DQ0 phase adjustment, determine the leftmost starting point P0 and the rightmost starting point P1 of the phase adjustment according to the adjustable phase range, and confirm the step length of each phase adjustment, recorded as T;

[0165] S002, first set the DQ0 phase to P0 for read and write training, write 8 groups of data continuously, DQ0 is 01010101 in sequence, and then read out 8 groups of data continuously.

[0166] S003, compare DQ0 of the 8 groups of data read out with DQ0 of the 8 groups of data written;

[0167] S004, if they are the same, record it as the available minimum delay value Q0, if they are different, increase the phase delay of DQ0 by T each time, repeat steps S002 and S003 until Q0 is found;

[0168] S005, set the phase delay of DQ0 to Q0+T, and repeat S002 and S003;

[0169] S006, compare DQ0 of the 8 groups of data read out with DQ0 of the 8 groups of data written;

[0170] S007, if they are different, do not record the current DQ0 phase delay, and record the last DQ0 phase delay value as the available maximum delay value Q1; if they are the same, increase the DQ0 phase delay setting by T each time, repeat S002 and S003 until they are different, and record the last DQ0 phase delay value as the available maximum delay value Q1;

[0171] S008, taking the average of the available minimum delay value Q0 and the available maximum delay value Q1 as the training result of DQ0 this time, and writing it into the RAM cache at the address A00.

[0172] S009, loop through S001, ..., S008 until the delay training of DQ1, ...DQ15 is completed and written into the RAM cache respectively at addresses A01, ...A015;

[0173] S010, loop through S001-S009 for 5 times, obtain the training results of DQ0, DQ1, ... DQ15 for 5 times, and write the results into RAM cache at addresses A10, A11, ... A115, ... A40, A41, ... A415;

[0174] S011, read the training results of DQ0 5 times, the RAM addresses are A00, A10, ..., A40 respectively, and count them to find the results that appear no less than 3 times, as the final training result of DQ0, write it into the RAM cache, the address is B00;

[0175] S012, read the five training results of DQ1, ..., DQ15 in sequence and make statistics, obtain the final training results of DQ1, ..., DQ15 respectively, and write them into the RAM cache at addresses B01, ...B0n;

[0176] S013, configuring the final training results of DQ0, DQ1, ..., DQ15 as the usage value of DDR phase delay for subsequent DDR reading and writing;

[0177] S014, exporting the final training results of DQ0, DQ1, ..., DQ15 to the host computer through the serial port;

[0178] S015, executing the above S001 to S014 on 100 mass-produced boards, exporting the results in sequence, and performing statistical analysis to obtain the three-sigma criterion statistical results of the final training results of DQ0, DQ1, ..., DQ15;

[0179] S016, write the statistical results of the three sigma criterion as the threshold into the mass production board test program, and execute S001 to S014 on the mass production version card to obtain the final training results of DQ0, DQ1, ..., DQ15 of each board, and use the statistical results of the three sigma criterion obtained in S015 as the mass production board screening conditions. For mass production boards DQ0, DQ1, ..., DQ15 whose final training results exceed the three sigma criterion, they are regarded as problem boards and are eliminated to further locate and analyze the causes of the abnormalities.

[0180] In this embodiment, a hardware consistency screening device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0181] This embodiment provides a hardware consistency screening device, such as Figure 6 , including: a selection module 601, a start module 602, a processing module 603 and an analysis module 604.

[0182] The selection module 601 is used to fix the phase of the data strobe signal in the first double rate synchronous dynamic random access memory DDR in the first sub-cycle, and select the delay value corresponding to each cycle round from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR in each cycle round;

[0183] The start module 602 is used to start and execute the continuous write command in sequence to obtain the write data code stream; and after each write data code stream is obtained, start and execute the continuous read command to obtain the read data code stream;

[0184] The processing module 603 is used to determine the minimum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more loop rounds; and after determining the minimum delay value, determine the maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more loop rounds; wherein the first DDR is any one of the multiple DDRs, and the first data bit is any one of the multiple data bits included in the first DDR; determine the first candidate delay value corresponding to the first data bit according to the minimum delay value and the maximum delay value, and end the operation of the current level sub-cycle; when the same number of multiple data bits as the first DDR are continuously executed After executing the first-level sub-cycle and obtaining the first candidate delay value corresponding to each data bit in the first DDR, determine that the current second-level sub-cycle ends, wherein the second-level sub-cycle includes multiple first-level sub-cycles; after executing multiple second-level sub-cycle operations, obtain multiple candidate delay values ​​corresponding to each data bit included in the first DDR; according to the multiple candidate delay values ​​corresponding to each data bit included in the first DDR, select the target delay value corresponding to each data bit of the first DDR, and the current third-level sub-cycle ends; after executing multiple third-level sub-cycle operations, obtain the target delay value corresponding to each data bit of each DDR in the multiple DDRs;

[0185] The analysis module 604 is used to perform statistical analysis on the target delay values ​​corresponding to each data bit of each DDR in the multiple DDRs, and determine a screening threshold, wherein the screening threshold is used to screen out hardware devices that meet the hardware consistency.

[0186] In an optional example, the processing module 603 is specifically configured to compare the write data code stream and the read data code stream respectively obtained in each cycle round;

[0187] When it is first determined that the write data code stream and the read data code stream generated in the first cycle are the same, the delay value corresponding to the first cycle is determined to be the minimum delay value corresponding to the first data bit, wherein the first cycle is any cycle within the first-level sub-cycle.

[0188] In an optional example, the processing module 603 is specifically used to continue to sequentially execute the continuous write command to obtain the write data code stream after determining the minimum delay value, and start and execute the continuous read command to obtain the read data code stream after each write data code stream is obtained;

[0189] After obtaining the write data code stream and the read data code stream in the second cycle round, the write data code stream and the read data code stream obtained in the second cycle round are compared, wherein the second cycle round is any cycle round after the minimum delay value is obtained in the first-level sub-cycle;

[0190] When the write data code stream and the read data code stream acquired in the second cycle are different, the delay value corresponding to the second cycle is determined to be the maximum delay value corresponding to the first data bit.

[0191] In an optional example, the processing module 603 is specifically configured to determine an average value according to the minimum delay value and the maximum delay value as a first candidate delay value corresponding to the first data bit.

[0192] In an optional example, the processing module 603 is specifically configured to count the number of occurrences of each candidate delay value among a plurality of candidate delay values ​​corresponding to each data bit;

[0193] A candidate delay value whose occurrence times are greater than or equal to a preset threshold is selected from the multiple candidate delay values ​​corresponding to each data bit as the target delay value corresponding to the data bit.

[0194] In an optional example, the processing module 603 is further configured to store the first candidate delay value in a preset storage device;

[0195] And, the target delay value corresponding to each data bit of the first DDR is stored in a preset storage device respectively.

[0196] In an optional example, in every two adjacent cycles, the delay value corresponding to the latter cycle is the sum of the delay value corresponding to the previous cycle and the preset delay step length;

[0197] The processing module 603 is further configured to obtain an influencing factor corresponding to the delay value, wherein the influencing factor includes any one of a data transmission rate, a data type, and a system load, wherein the data type is determined based on the impact, real-timeness, and sensitivity of the data;

[0198] According to the influencing factors, a calculation formula corresponding to the preset delay step length is matched;

[0199] According to the calculation formula, determine the preset delay step length within the first-level sub-cycle;

[0200] The calculation formula corresponding to the preset delay step size includes the following:

[0201] Preset delay step = minimum delay step + (data transmission rate / maximum transmission rate) * (maximum delay step - minimum delay step);

[0202] or,

[0203] Preset delay step = standard delay step * data type weight;

[0204] or,

[0205] Preset delay step length = load adjustment factor * (system load / maximum load) * standard delay step length;

[0206] Among them, the standard delay step is a preconfigured benchmark delay step. The preset delay step is applicable to all first-level sub-cycles. The minimum delay step, maximum transmission rate, maximum delay step, standard delay step, data type weight corresponding to the data type, load adjustment factor, and maximum load are all pre-configured data.

[0207] The hardware consistency screening device in this embodiment is presented in the form of a functional module, where the module refers to an application specific integrated circuit (ASIC), a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0208] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0209] A hardware consistency screening device provided by an embodiment of the present invention obtains a write data code stream and a read data code stream by fixing the phase of a data strobe signal and selecting different delay values ​​in each cycle. Then, the minimum delay value and the maximum delay value are determined according to these data code streams. Next, the first candidate delay value is determined according to the minimum delay value and the maximum delay value, and the first candidate delay value of each data bit is obtained after the first-level sub-cycle ends. In the second-level sub-cycle, the above process is repeated to obtain multiple candidate delay values. Finally, in the third-level sub-cycle, the target delay value of each data bit is selected according to the multiple candidate delay values, and the target delay value of each data bit of each DDR in multiple DDRs is statistically analyzed to determine the screening threshold. By accurately adjusting the phase and delay value of the data strobe signal, errors and interference in data transmission can be reduced, and the accuracy and reliability of data can be improved. The optimal delay value of each data bit is determined to make data transmission more efficient, thereby improving the performance of the entire system. By statistically analyzing the target delay value of each data bit in multiple DDRs and determining the screening threshold, hardware devices that meet hardware consistency can be quickly screened out, hardware consistency risks can be eliminated early, and product quality and stability can be improved. This solution can adapt to different DDR types and hardware configurations, and has strong versatility and scalability. Moreover, it ensures the stability and reliability of data transmission and can also reduce system failures and performance degradation caused by hardware inconsistencies.

[0210] The embodiment of the present invention also provides a computer device having the above Figure 6 The hardware consistency filter device is shown.

[0211] See also Figure 7 , Figure 7 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0212] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include an integrated circuit. The integrated circuit may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0213] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0214] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of a computer device based on the presentation of a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0215] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0216] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0217] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0218] The embodiment of the present invention also provides a computer-readable storage medium. The method provided in the above embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or is implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium and downloaded through a network, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0219] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0220] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A hardware consistency screening method, characterized in that: The method comprises: In a first-level sub-cycle, a phase of a data strobe signal in a first double data rate synchronous dynamic random access memory DDR is fixed, and in each cycle round, a delay phase of a first data bit in the first DDR is selected from a plurality of pre-configured delay values ​​corresponding to each cycle round, and continuous write commands are sequentially started and executed to obtain a write data code stream; and after each acquisition of the write data code stream, a continuous read command is started and executed to obtain a read data code stream; Determine a minimum delay value corresponding to the first data bit according to a write data code stream and a read data code stream obtained in one or more cyclic rounds; and after determining the minimum delay value, determine a maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more cyclic rounds; wherein the first DDR is any one of a plurality of DDRs, and the first data bit is any one of a plurality of data bits included in the first DDR; Determine a first candidate delay value corresponding to the first data bit according to the minimum delay value and the maximum delay value, and terminate the operation of the current level sub-cycle; After continuously executing the same number of first-level sub-cycles as the number of the plurality of data bits included in the first DDR, and obtaining the first candidate delay value corresponding to each data bit in the first DDR, determining that the current second-level sub-cycle ends operation, wherein the second-level sub-cycle includes a plurality of the first-level sub-cycles; After executing the plurality of secondary sub-cycle operations, respectively obtaining a plurality of candidate delay values ​​corresponding to the respective data bits included in the first DDR; According to a plurality of candidate delay values ​​corresponding to the respective data bits included in the first DDR, a target delay value corresponding to each data bit of the first DDR is selected respectively, and the current three-level sub-cycle ends the operation; After executing a plurality of the three-stage sub-cycle operations, obtaining a target delay value corresponding to each data bit of each of the plurality of DDRs; Statistical analysis is performed on target delay values ​​corresponding to respective data bits of each of the multiple DDRs to determine a screening threshold, wherein the screening threshold is used to screen out hardware devices that meet hardware consistency.

2. The method according to claim 1, characterized in that The determining, according to the write data code stream and the read data code stream obtained in one or more cycles, a minimum delay value corresponding to the first data bit specifically includes: Compare the write data code stream and the read data code stream obtained in each cycle round; When it is first determined that the write data code stream and the read data code stream generated in the first cycle round are the same, the delay value corresponding to the first cycle round is determined to be the minimum delay value corresponding to the first data bit, wherein the first cycle round is any cycle round within the first-level sub-cycle.

3. The method according to claim 1 or 2, characterized in that: After determining the minimum delay value, determining a maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more cycles specifically includes: After determining the minimum delay value, continuously executing the continuous write command in sequence to obtain the write data code stream, and after each acquisition of the write data code stream, starting and executing the continuous read command to obtain the read data code stream; After obtaining the write data code stream and the read data code stream in the second cycle round, the write data code stream and the read data code stream obtained in the second cycle round are compared, wherein the second cycle round is any cycle round after the minimum delay value is obtained in the first-level sub-cycle; When the write data code stream and the read data code stream acquired in the second cycle are different, the delay value corresponding to the second cycle is determined to be the maximum delay value corresponding to the first data bit.

4. The method according to claim 1 or 2, characterized in that: The determining, according to the minimum delay value and the maximum delay value, a first candidate delay value corresponding to the first data bit specifically includes: An average value is determined according to the minimum delay value and the maximum delay value as a first candidate delay value corresponding to the first data bit.

5. The method according to claim 4, characterized in that The selecting, according to a plurality of candidate delay values ​​corresponding to each data bit included in the first DDR, a target delay value corresponding to each data bit of the first DDR, specifically includes: Counting the number of occurrences of each candidate delay value among the multiple candidate delay values ​​corresponding to each of the data bits; A candidate delay value whose occurrence number is greater than or equal to a preset threshold is selected from the multiple candidate delay values ​​corresponding to each of the data bits as the target delay value corresponding to the data bit.

6. The method according to claim 5, characterized in that The method further comprises: Storing the first candidate delay value in a preset storage device; And, the target delay value corresponding to each of the data bits of the first DDR is stored in the preset storage device respectively.

7. The method according to claim 1 or 2, characterized in that: In every two adjacent cycles, the delay value corresponding to the latter cycle is the sum of the delay value corresponding to the former cycle and the preset delay step length; In the first-level sub-cycle, the phase of the data strobe signal in the first DDR is fixed, and before selecting the delay value corresponding to each cycle round from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR in each cycle round, the method further includes: Acquire an influencing factor corresponding to the delay value, wherein the influencing factor includes any one of a data transmission rate, a data type, and a system load, wherein the data type is determined based on the impact, real-timeness, and sensitivity of the data; According to the influencing factors, matching a calculation formula corresponding to the preset delay step length; Determining the preset delay step length within the primary sub-cycle according to the calculation formula; The calculation formula corresponding to the preset delay step size includes the following: Preset delay step = minimum delay step + (data transmission rate / maximum transmission rate) * (maximum delay step - minimum delay step); or, The preset delay step length = standard delay step length * data type weight; Among them, the standard delay step is a preconfigured benchmark delay step, the preset delay step is applicable to all the first-level sub-cycles, the minimum delay step, the maximum transmission rate, the maximum delay step, the standard delay step, and the data type weight corresponding to the data type are preconfigured data.

8. A hardware consistency screening device, characterized in that: The device comprises: A selection module is used to fix the phase of the data selection signal in the first double rate synchronous dynamic random access memory DDR in a first sub-cycle, and select a delay value corresponding to each cycle round from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR in each cycle round; A start module, used to start and execute continuous write commands in sequence to obtain write data code streams; and after each acquisition of the write data code stream, start and execute continuous read commands to obtain read data code streams; A processing module, configured to determine a minimum delay value corresponding to the first data bit according to a write data code stream and a read data code stream obtained in one or more loop rounds; and after determining the minimum delay value, determine a maximum delay value corresponding to the first data bit according to the write data code stream and the read data code stream obtained in one or more loop rounds; wherein the first DDR is any one of a plurality of DDRs, and the first data bit is any one of a plurality of data bits included in the first DDR; determine a first candidate delay value corresponding to the first data bit according to the minimum delay value and the maximum delay value, and terminate the operation of the current level sub-cycle; when a number of the same number of data bits as the first DDR is continuously executed, After executing the first level sub-cycle and obtaining the first candidate delay value corresponding to each data bit in the first DDR, determine that the current second-level sub-cycle ends, wherein the second-level sub-cycle includes multiple first-level sub-cycles; after executing multiple second-level sub-cycle operations, obtain multiple candidate delay values ​​corresponding to each data bit included in the first DDR respectively; according to the multiple candidate delay values ​​corresponding to each data bit included in the first DDR, select the target delay value corresponding to each data bit of the first DDR respectively, and the current third-level sub-cycle ends; after executing multiple third-level sub-cycle operations, obtain the target delay value corresponding to each data bit of each DDR in the multiple DDRs; The analysis module is used to perform statistical analysis on the target delay values ​​corresponding to each data bit of each of the multiple DDRs to determine a screening threshold, wherein the screening threshold is used to screen out hardware devices that meet the hardware consistency.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the hardware consistency screening method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the hardware consistency screening method according to any one of claims 1 to 7.

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