Vector processor, data processing method, device and equipment
By using multi-page vector registers in the vector processor, the calculation intermediate data is written from the activation page to the inactive page, which solves the problem of low efficiency of vector registers and achieves more efficient memory access operations.
Patent Information
- Application Number
- CN202411290936.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2025-01-07
AI Technical Summary
The amount of calculation intermediate data generated by vector registers in a vector processor during read or write operations is greater than the storage capacity, resulting in need of writing back to memory and re-reading, which is not efficient.
Using vector registers of at least two pages, through the shared read and write ports of the activated and inactivated pages, the calculation intermediate data is written from the activated page to the inactivated page, shortening the memory access distance and reducing the memory access time.
The efficiency of the intermediary result of the vector register is improved, and the access time for calculating the intermediate data is reduced.
Smart Images
Figure CN119271272A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of instruction control, and in particular to a vector processor, a data processing method, a device, a equipment and a computer program product. Background Art
[0002] Currently, after obtaining a vector instruction, a vector arithmetic logic processing unit, a vector loading unit, and a vector saving unit in a vector processor perform a read operation or a write operation on a vector register in the vector processor according to the vector instruction.
[0003] During the process of reading or writing vector registers, intermediate calculation data will be generated inside the vector registers. When the amount of generated intermediate calculation data is greater than the storage capacity of the vector register, part of the intermediate calculation data in the vector register needs to be written back to the vector memory in the vector processor, and this part of the intermediate calculation data is read from the vector memory in the subsequent calculation process. However, the efficiency of vector registers in accessing intermediate calculation data is not high. Summary of the invention
[0004] The embodiments of the present disclosure provide a vector processor, a data processing method, an apparatus, a device, and a computer program product, which can improve the efficiency of vector register access to calculate intermediate results.
[0005] In a first aspect, an embodiment of the present disclosure provides a vector processor, including:
[0006] Scalar processing unit, used to parse and dispatch vector instructions;
[0007] The vector processing unit is connected to the scalar processing unit. The vector processing unit includes a vector instruction emission module, a target processing unit module, at least two pages and a status register. The page includes an active page and an inactive page. The page includes a vector register based on a two-port random static memory 2P SRAM. The vector processing unit is used to obtain a page pointer from the status register through the target processing unit module, and execute the vector instruction emitted by the vector instruction emission module. Based on the vector instruction, a read operation or a write operation is performed on the vector register based on the 2P SRAM in the active page indicated by the page pointer. When the amount of calculation intermediate data generated by the vector register of the 2P SRAM is greater than a preset threshold, part of the calculation intermediate data is written into the register of the inactive page.
[0008] In an achievable implementation, each of the at least two pages is connected to a read data bus or a write data bus in the vector processing unit through the same read / write port.
[0009] In an achievable implementation, the vector processor further includes a vector memory, and the vector memory is used to store data required to be saved when the target processing unit module performs a read operation or a write operation.
[0010] In an achievable implementation, the target processing unit module includes at least one of a vector arithmetic logic processing unit module, a vector loading unit module, and a vector saving unit module.
[0011] In a second aspect, an embodiment of the present disclosure provides a method for data processing, the method comprising:
[0012] Acquire a vector instruction emitted by a vector instruction emission module in a vector processing unit, where the vector instruction includes a target register number;
[0013] Obtaining a page pointer from a status register of the vector processing unit, the page pointer being used to indicate an active page number;
[0014] According to the target vector register address obtained by combining the activation page number and the target register number, a read operation or a write operation is performed on the target vector register in the activation page based on the vector instruction by the target processing unit module;
[0015] When it is detected that the amount of calculation intermediate data generated by the target vector register during the read operation or write operation is greater than a preset threshold, the calculation intermediate data of the target amount in the target vector register is written into a non-target vector register in an inactive page.
[0016] In an achievable implementation, writing the calculated intermediate data of the target data amount in the target vector register into the non-target vector register in the inactive page includes:
[0017] The calculated intermediate data of the target data amount in the target vector register is written into the non-target vector register in the inactive page through the read / write port commonly used by the active page and the inactive page.
[0018] In an achievable implementation, the target processing unit module includes at least one of a vector arithmetic logic processing unit module, a vector loading unit module, and a vector saving unit module.
[0019] In one practicable implementation, when the target processing unit module includes at least one of a vector save unit and a vector load unit, the method further includes:
[0020] Acquire a target vector instruction emitted by a vector instruction emission module in a vector processing unit, wherein the target vector instruction includes an inactive page number and a target register number;
[0021] According to the non-target vector register address obtained by combining the non-activated page number and the target register number, a corresponding read operation or write operation is performed on the non-target vector register in the non-activated page based on the target vector instruction through the vector save unit or the vector load unit, and when the amount of calculated intermediate data generated by the vector register of the 2P SRAM is greater than a preset threshold, part of the calculated intermediate data is written to the register of the target non-activated page.
[0022] In a third aspect, an embodiment of the present disclosure provides a device, comprising any equipment of the first aspect.
[0023] In a fourth aspect, an embodiment of the present disclosure provides a device, comprising a processor and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement a data processing method as described in any one of the second aspects.
[0024] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, including a computer program, which implements a data processing method as described in any one of the second aspects when the computer program is executed by a processor.
[0025] The disclosed embodiments provide a vector processor, a method, an apparatus, a device and a computer program product for data processing. The method obtains a vector instruction emitted by a vector instruction emission module in a vector processing unit; obtains a page pointer from a status register of the vector processing unit; performs a read operation or a write operation on a target vector register in an activated page based on the vector instruction through a target processing unit module according to a target vector register address obtained by combining an activated page number and a target register number; when it is detected that the amount of calculated intermediate data generated by the target vector register during the read operation or the write operation is greater than a preset threshold, the calculated intermediate data of the target data amount in the target vector register is written into a non-target vector register in an inactive page. It can be seen that the disclosed embodiments shorten the distance required for accessing the calculated intermediate data by writing the calculated intermediate data of the vector register in the activated page into the non-target register in the inactive page, thereby reducing the time for accessing the calculated intermediate data, and ultimately improving the efficiency of the vector register accessing the calculated intermediate results. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the following is a brief introduction to the drawings required for use in the embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0027] Figure 1It is a schematic diagram of connecting a target processing unit module and a vector register based on 2P SRAM provided by an embodiment of the present disclosure;
[0028] Figure 2 is a schematic diagram of a vector processor provided by an embodiment of the present disclosure;
[0029] Figure 3 It is a schematic diagram of a target processing unit module provided by an embodiment of the present disclosure and connected to at least two pages including a vector register based on 2PSRAM;
[0030] Figure 4 is a flowchart of a data processing method provided by an embodiment of the present disclosure;
[0031] Figure 5 is a flowchart of another data processing method provided by an embodiment of the present disclosure;
[0032] Figure 6 It is a structural diagram of a data processing device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0033] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present invention, rather than to limit the present invention. For those skilled in the art, the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention.
[0034] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0035] Before describing the technical solutions provided by the embodiments of the present disclosure, in order to facilitate understanding of the embodiments of the present disclosure, the present disclosure specifically describes the problems existing in the related technologies:
[0036] Currently, after obtaining a vector instruction, a vector arithmetic logic processing unit, a vector loading unit, and a vector saving unit in a vector processing unit of a vector processor perform a read operation or a write operation on a vector register in the vector processor according to the vector instruction.
[0037] In one embodiment, the schematic diagram of the connection between the target processing unit module and the vector register based on 2P SRAM is as follows Figure 1 As shown, the 32 vector registers VR0-VR31 based on 2P SRAM include a read port and a write port, supporting parallel reading and writing. The vector registers VR0-VR31 are respectively connected to the vector storage module (VST), the first vector arithmetic logic unit module (VALU1) and the second vector arithmetic logic unit module (VALU2) through the read data bus (RD BUS). The vector registers VR0-VR31 are respectively connected to the vector loading module (VLD), the first vector arithmetic logic unit module (VALU1) and the second vector arithmetic logic unit module (VALU2) through the write data bus (WT BUS).
[0038] During the process of reading or writing vector registers, intermediate calculation data will be generated inside the vector registers. When the amount of generated intermediate calculation data is greater than the storage capacity of the vector register, part of the intermediate calculation data in the vector register needs to be written back to the vector memory in the vector processor, and this part of the intermediate calculation data is read from the vector memory in the subsequent calculation process. However, the efficiency of vector registers in accessing intermediate calculation data is not high.
[0039] The embodiments of the present disclosure provide a vector processor, a data processing method, an apparatus, a device, and a computer program product, which can solve the above-mentioned technical problems existing in the related technologies.
[0040] The disclosed embodiment shortens the distance required for accessing the intermediate data for calculation by writing the intermediate data calculated by the vector register in the activated page into the non-target register in the inactive page, thereby reducing the time for accessing the intermediate data for calculation, and ultimately improving the efficiency of the vector register accessing the intermediate results for calculation.
[0041] The scheme of the embodiment of the present disclosure is described below with reference to the accompanying drawings.
[0042] Figure 2 Schematic diagram of a vector processor provided by an embodiment of the present disclosure. Figure 2As shown, vector processor 101 includes scalar processing unit 102 and vector processing unit 103. Vector processing unit 103 is connected to scalar processing unit 102 and includes vector instruction issuing module 104, target processing unit module 105, at least two pages 106 of vector registers based on 2P SRAM, and status register 107.
[0043] Among them, the page includes an activated page and an inactivated page, the page includes a vector register based on a two-port random static memory 2PSRAM, the vector processing unit is used to obtain a page pointer from a status register through a target processing unit module, and execute a vector instruction emitted by a vector instruction emission module, based on the vector instruction, perform a read operation or a write operation on a vector register based on a 2P SRAM in an activated page indicated by a page pointer, and when the amount of calculated intermediate data generated by the vector register of the 2P SRAM is greater than a preset threshold, write part of the calculated intermediate data into the register of the inactivated page.
[0044] In one example, each of the at least two pages is connected to a read data bus or a write data bus in the vector processing unit through the same read / write port.
[0045] In one example, the vector processor 101 further includes a vector memory 108, and the vector memory 108 is used to store data required to be saved when the target processing unit module performs a read operation or a write operation.
[0046] In one example, the target processing unit module 105 includes at least one of a vector arithmetic logic processing unit module 1051 , a vector loading unit module 1052 , and a vector saving unit module 1053 .
[0047] In one example, a schematic diagram of a target processing unit module connected to at least two pages of vector registers based on 2P SRAM is shown in FIG. Figure 3As shown, each of the four pages "Way0", "Way1", "Way2" and "Way3" includes 32 vector registers based on 2P SRAM, VR0-VR31. These four pages use shared read and write ports to connect to the vector storage module (VST), the first vector arithmetic logic unit module (VALU1) and the second vector arithmetic logic unit module (VALU2) through the read data bus (RD BUS). These four pages use shared read and write ports to connect to the vector loading module (VLD), the first vector arithmetic logic unit module (VALU1) and the second vector arithmetic logic unit module (VALU2) through the write data bus (WT BUS). The vector loading module, the vector storage module, the first vector arithmetic logic unit module and the second vector arithmetic logic unit module are connected to the status register through the port, and can obtain the page pointer (CurrWay) in the status register (Vector Control Status Register, VCSR), which is used to indicate the active page in "Way0", "Way1", "Way2" and "Way3".
[0048] In another example, if the page pointer in the status register currently indicates that the "Way0" page is the active page, then after receiving the vector instruction emitted by the vector instruction emission module, any one of the vector loading module, the vector saving module, the first vector arithmetic logic unit module, and the second vector arithmetic logic unit module performs a corresponding read operation or write operation on the 15th vector register in the "Way0" page according to the page number 0 corresponding to the page pointer and the register number 15 in the vector instruction, which is spliced into the address "015" of the target register. And when the intermediate calculation result generated by the 15th vector register in the "Way0" page is greater than the preset threshold, part of the intermediate calculation result is stored in the vector register under any one of the pages "Way1" or "Way2" or "Way3" through the shared read-write port. When the 15th vector register in the "Way0" page needs to use this part of the intermediate calculation result, it is read from the corresponding vector register through the shared read-write port.
[0049] Figure 4 An embodiment of the present disclosure provides an application Figure 2 FIG. 1 is a flow chart of a method for data processing by a vector processor. Figure 4 , the method may include steps S210-S240.
[0050] S210: Acquire a vector instruction issued by a vector instruction issuing module in a vector processing unit.
[0051] The target processing unit module in the vector processing unit uses the receiving component to obtain the vector instruction transmitted by the vector instruction transmitting module in the vector processing unit.
[0052] The vector processor where the vector processing unit is located may include a vector processor of a vector register based on a 2P SRAM. The vector instruction may include a target register number.
[0053] In the process of the embodiment of the present disclosure, the target processing unit module obtains a vector instruction and can determine a corresponding vector register from a plurality of vector registers to perform a read operation or a write operation according to data information included in the vector instruction.
[0054] S220: Obtain a page pointer from a status register of the vector processing unit.
[0055] The target processing unit module exchanges information with the status register of the vector processing unit through a port to obtain a page pointer in the status register.
[0056] The page pointer is used to indicate the activated page number.
[0057] In the process of the embodiment of the present disclosure, the vector processing unit obtains the page pointer in the status register, and can determine the corresponding vector register from the multiple vector registers of the activated page in the multiple pages to perform a read operation or a write operation.
[0058] S230: According to the target vector register address obtained by combining the activation page number and the target register number, a read operation or a write operation is performed on the target vector register in the activation page based on the vector instruction by the target processing unit module.
[0059] After obtaining the activation page number corresponding to the page pointer and the target register number corresponding to the vector instruction, the target unit module concatenates the activation page number and the target register number according to a preset concatenation order to obtain the address of the target vector register, and performs a read operation or a write operation on the target vector register in the activation page based on the vector instruction.
[0060] The target processing unit module may include at least one of a vector arithmetic logic processing unit module, a vector loading unit module and a vector saving unit module.
[0061] In one example, the address of the target vector register may consist of a 3-bit page number plus a 5-bit target register number, wherein the bit size of the page number is determined according to the number of pages.
[0062] In another example, the address of the target vector register is "216", indicating that the target vector register is the 16th vector register of the 2nd page.
[0063] In the process of the embodiment of the present disclosure, the vector processing unit obtains the page pointer in the status register, and can determine the corresponding vector register from the multiple vector registers of the activated page in the multiple pages to perform a read operation or a write operation.
[0064] S240: When it is detected that the amount of calculation intermediate data generated by the target vector register during the read operation or the write operation is greater than a preset threshold, write the calculation intermediate data of the target amount in the target vector register into a non-target vector register in the inactive page.
[0065] The target vector register generates calculated intermediate data during a read operation or a write operation. If it is detected that the amount of the generated calculated intermediate data is greater than a preset threshold, the calculated intermediate data of the target data amount in the target vector register is written into a non-target vector register in an inactive page.
[0066] The preset threshold represents the threshold of the amount of data for calculating the intermediate data. The size of the target data amount is not fixed. The inactive page represents the page that the page pointer does not currently point to. The non-target register represents the vector register other than the target vector register.
[0067] The disclosed embodiment shortens the distance required for vector registers to access intermediate data for calculation by writing the calculated intermediate data of the vector registers in the activated page into non-target registers in the inactive page, thereby reducing the time for accessing the intermediate data for calculation, and ultimately improving the efficiency of vector registers in accessing the intermediate results for calculation.
[0068] In one embodiment, writing the calculated intermediate data of the target data amount in the target vector register into the non-target vector register in the inactive page may include step S241 .
[0069] S241: Writing the calculated intermediate data of the target data amount in the target vector register into the non-target vector register in the inactive page through the read / write port used by the active page and the inactive page.
[0070] When the target vector register in the activated page detects that the amount of generated calculation intermediate data is greater than a preset threshold, the calculation intermediate data of the target data amount in the target vector register is written into the non-target vector register in the inactive page through the read and write port used by the activated page and the inactive page.
[0071] The disclosed embodiment uses a read / write port that is used jointly by an activated page and an inactivated page, so that the intermediate data of the calculation of the target data amount in the target vector register can be written into a non-target vector register of any inactivated page among multiple inactivated pages, thereby improving the flexibility of the vector register in accessing the intermediate data of the calculation.
[0072] In one embodiment, when the target processing unit module includes at least one of a vector save unit and a vector load unit, Figure 5 As shown, the data processing method further includes step S250 and step S260.
[0073] S250: Acquire a target vector instruction emitted by a vector instruction emission module in a vector processing unit.
[0074] The target processing unit module uses the receiving component to obtain the target vector instruction transmitted by the vector instruction transmitting module in the vector processing unit.
[0075] The target vector instruction may include a non-activated page number and a target register number.
[0076] In the process of the embodiment of the present disclosure, the target processing unit module obtains the target vector instruction and can perform a read operation or a write operation on the target register in the inactive page according to the inactive page number and the target register number in the target vector instruction when the page pointer indicates the active page.
[0077] S260: According to the non-target vector register address obtained by combining the non-activated page number and the target register number, a corresponding read operation or write operation is performed on the non-target vector register in the non-activated page based on the target vector instruction through the vector save unit or the vector load unit, and when the amount of calculated intermediate data generated by the vector register of the 2PSRAM is greater than a preset threshold, part of the calculated intermediate data is written to the register of the target non-activated page.
[0078] After obtaining the inactive page number and the target register number in the target vector instruction, at least one of the vector saving unit and the vector loading unit splices the inactive page number and the target register number in a preset splicing order to obtain the address of the non-target vector register. A read operation or a write operation is performed on the non-target vector register in the inactive page based on the target vector instruction. When the amount of the calculated intermediate data generated by the vector register of the 2P SRAM is greater than a preset threshold, part of the calculated intermediate data is written into the register of the target inactive page.
[0079] In the disclosed embodiment, after obtaining the target vector instruction, the vector saving unit or the vector loading unit performs a corresponding read operation or write operation on the non-target vector register in the inactive page according to the inactive page number and the target register number of the target vector instruction, thereby improving the operability of the vector saving unit or the vector loading unit in performing read operations or write operations on different types of pages.
[0080] Figure 6 A schematic diagram of the hardware structure of data processing provided by an embodiment of the present disclosure is shown.
[0081] The data processing device may include a processor 601 and a memory 602 storing computer program instructions.
[0082] Specifically, the processor 601 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.
[0083] The memory 602 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 602 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 602 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 602 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 602 is a non-volatile solid-state memory.
[0084] The memory 602 may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Therefore, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to one aspect of the present disclosure.
[0085] The processor 601 implements any one of the data processing methods in the above embodiments by reading and executing computer program instructions stored in the memory 602 .
[0086] In one example, the data processing device may further include a communication interface 603 and a bus 604. Figure 6 As shown, the processor 601, the memory 602, and the communication interface 603 are connected via a bus 604 and communicate with each other.
[0087] The communication interface 603 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.
[0088] Bus 604 includes hardware, software or both, and couples the components of online data flow billing equipment to each other. For example, but not limitation, the bus may include Accelerated Graphics Port (AGP) or other graphics bus, Enhanced Industry Standard Architecture (EISA) bus, Front Side Bus (FSB), Hyper Transport (HT) interconnection, Industry Standard Architecture (ISA) bus, InfiniBand interconnection, Low Pin Count (LPC) bus, Memory bus, Micro Channel Architecture (MCA) bus, Peripheral Component Interconnect (PCI) bus, PCI-Express (PCI-X) bus, Serial Advanced Technology Attachment (SATA) bus, Video Electronics Standards Association Local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 604 may include one or more buses. Although the embodiment of the present invention describes and shows a specific bus, the present invention considers any suitable bus or interconnection. In addition, in conjunction with the method for data processing in the above-mentioned embodiment, the embodiment of the present application also provides a computer storage medium to realize. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any one of the data processing methods in the above embodiments is implemented.
[0089] An embodiment of the present application also provides a computer program product, including a computer program, which implements any one of the data processing methods in the above embodiments when the computer program is executed by a processor.
[0090] It should be clear that the present invention is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present invention.
[0091] The functional blocks shown in the above structural block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), appropriate firmware, plug-in, function card, etc. When implemented in software, the elements of the present invention are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or communication link by a data signal carried in a carrier. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, read-only memory (Read-Only Memory, ROM), flash memory, erasable read-only memory (Erasable ReadOnly Memory, EROM), floppy disks, compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical discs, hard disks, optical fiber media, radio frequency (Radio Frequency, RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.
[0092] It should also be noted that the exemplary embodiments mentioned in the present invention describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiments, or in a different order from the embodiments, or several steps can be performed simultaneously.
[0093] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.
[0094] The above is only a specific implementation of the present invention. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system, module and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be covered within the protection scope of the present invention.
Claims
1. A vector processor, characterized in that: include: Scalar processing unit, used to parse and dispatch vector instructions; A vector processing unit is connected to the scalar processing unit, the vector processing unit includes a vector instruction emission module, a target processing unit module, at least two pages and a status register, the page includes an active page and an inactive page, the page includes a vector register based on a two-port random static memory 2P SRAM, the vector processing unit is used to obtain a page pointer from the status register through the target processing unit module, and execute the vector instruction emitted by the vector instruction emission module, perform a read operation or a write operation on the vector register based on the 2PSRAM in the active page indicated by the page pointer based on the vector instruction, and write part of the calculated intermediate data into the register of the inactive page when the amount of the calculated intermediate data generated by the vector register of the 2PSRAM is greater than a preset threshold.
2. The vector processor according to claim 1, characterized in that Each of the at least two pages is connected to a read data bus or a write data bus in the vector processing unit through the same read / write port.
3. The vector processor according to claim 1, characterized in that The vector processor further includes a vector memory, and the vector memory is used to store data required to be saved when the target processing unit module performs a read operation or a write operation.
4. The vector processor according to any one of claims 1 to 3, characterized in that: The target processing unit module includes at least one of a vector arithmetic logic processing unit module, a vector loading unit module and a vector saving unit module.
5. A data processing method applied to the vector processor of claim 1, characterized in that: include: Acquire a vector instruction emitted by a vector instruction emission module in a vector processing unit, wherein the vector instruction includes a target register number; Obtaining a page pointer from a status register of the vector processing unit, the page pointer being used to indicate an activated page number; According to the target vector register address obtained by combining the activation page number and the target register number, a target processing unit module performs a read operation or a write operation on the target vector register in the activation page based on the vector instruction; When it is detected that the amount of calculated intermediate data generated by the target vector register during the read operation or the write operation is greater than a preset threshold, the calculated intermediate data of the target data amount in the target vector register is written into a non-target vector register in an inactive page.
6. The method according to claim 5, characterized in that The step of writing the calculated intermediate data of the target data amount in the target vector register into the non-target vector register in the inactive page comprises: The calculated intermediate data of the target data amount in the target vector register is written into the non-target vector register in the inactive page through the read / write port commonly used by the active page and the inactive page.
7. The method according to any one of claim 5 or claim 6, characterized in that: The target processing unit module includes at least one of a vector arithmetic logic processing unit module, a vector loading unit module and a vector saving unit module.
8. The method according to claim 5, characterized in that In the case where the target processing unit module includes at least one of a vector save unit and a vector load unit, the method further comprises: Acquire a target vector instruction emitted by a vector instruction emission module in the vector processing unit, wherein the target vector instruction includes an inactive page number and a target register number; According to the non-target vector register address obtained by combining the inactive page number and the target register number, the vector save unit or the vector load unit performs a corresponding read operation or a write operation on the non-target vector register in the inactive page based on the target vector instruction, and when the amount of the calculated intermediate data generated by the vector register of the 2P SRAM is greater than a preset threshold, part of the calculated intermediate data is written into the register of the target inactive page.
9. A device, characterized in that: The device comprises the vector processor according to any one of claims 1 to 4.
10. A device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the data processing method according to any one of claims 5 to 8.
11. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the data processing method according to any one of claims 5 to 8.