Embedded chip system and program execution method thereof, and embedded device

Abstract

The present invention proposes an embedded chip system and a program execution method thereof, as well as an embedded device. The embedded chip system includes: a main control module; an extended program memory, the storage space is divided into a plurality of CPU address accessible spaces, and the high-order address is selected by extending the parallel port unit; an extended data memory, the storage space is divided into a plurality of CPU address accessible spaces, and the high-order address is selected by extending the parallel port unit; a first CPLD unit, which can generate a chip select signal of an external extended chip according to the address signal of the main control module; a second CPLD unit, which can complete the state conversion of the program memory and the high-order access address control of the program memory and the data memory according to the control signal of the main control module. The present invention breaks through the limitation of the 64Kbytes access address of the single-chip CPU itself, and the maximum of the program memory and the data memory are expanded to 512Kbytes, which is suitable for the needs of complex application systems with large program and data storage volumes.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded chip systems, and relates to an expansion method of a program memory and a data memory, a program execution method thereof, and an embedded device. Background Art

[0002] The MCS51 series of 8-bit microcontrollers are the most widely used series. Due to their low cost, they are widely used in household appliances, automobiles, industrial measurement and control, and communication equipment. However, the resources of this series of microcontrollers are limited. The address space of the data storage and data storage is only 64Kbytes. In particular, the use of C language under the KEIL C51 compiler facilitates programming, but the amount of code also increases a lot, and the storage space is also dwarfed. How to expand the storage space and no longer be limited by 64Kbytes has become very important and urgent. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an expansion method for the program memory and data memory of an embedded chip system, which breaks through the limitation of the CPU's own access address space. The program memory is expanded, and the storage space is divided into multiple CPU-address accessible spaces, which are selected by the high-order address through the expansion parallel port unit; the data memory is expanded, and the storage space is divided into multiple CPU-address accessible spaces, which are selected by the high-order address through the expansion parallel port unit; the first CPLD unit can generate an external expansion chip chip select signal according to the address signal of the main control module; the second CPLD unit can complete the state conversion of the program memory and control the high-order access address of the program memory and data memory according to the control signal of the main control module. The on-chip program memory of the CPU can also be used to complete the download of the application program, which meets the needs of replacing and upgrading the application program on site.

[0004] In a first aspect, an embodiment of the present invention provides an embedded chip system, including:

[0005] A main control module, including an on-chip program memory;

[0006] An extended program memory, wherein the extended program memory is used to store application programs of the embedded chip system, and the storage space is divided into a plurality of program spaces accessible by the CPU's own addresses;

[0007] An extended data memory, wherein the extended data memory is used to store data of the embedded chip system, and the storage space is divided into a plurality of data spaces accessible by the CPU itself;

[0008] A first parallel port expansion unit, the first parallel port expansion unit comprising a first expansion port and a second expansion port, the first expansion port being used for high-order address expansion of the expansion program memory, and the second expansion port being used for high-order address expansion of the expansion data memory;

[0009] a first CPLD unit, the first CPLD unit being used to generate a chip select signal of an external expansion interface according to an address signal of the main control module, the external expansion interface comprising the first parallel port expansion unit;

[0010] The second CPLD unit is used to control the state conversion of the extended program memory, perform access control on the high address extension port of the extended program memory and perform access control on the high address extension port of the extended data memory according to the control signal of the main control module.

[0011] In some embodiments of the present invention, the embedded chip system also includes an extended external device unit, which is connected to the chip of the extended device through a data bus and a control signal, and the extended external device unit includes an extended clock module, an extended MCM read-write module and an extended liquid crystal module.

[0012] In some embodiments of the present invention, the embedded chip system further includes an address latch, through which the lower 8 bits of the system address are latched.

[0013] In some embodiments of the present invention, the embedded chip system further includes a bus driving unit for enhancing bus driving capability, and the bus driving unit can also be controlled by the second CPLD unit so that the data bus is isolated from the external device unit.

[0014] In some embodiments of the present invention, the embedded chip system also includes a power-off protection unit, by which the extended data storage device is protected from power-off, and the power-off protection unit is connected to a battery unit, and the battery unit is used to continuously supply power to the power-off protection unit; when the embedded chip system loses power, the power-off protection unit generates a high-level chip select signal so that the internal data of the extended data storage device is not lost.

[0015] In some embodiments of the present invention, the embedded chip system further includes a space restriction unit, the area size of the extended program memory when used is determined according to the number of BANK spaces, and the space restriction unit is used to connect the used area and shield the unused area.

[0016] In some embodiments of the present invention, the external expansion interface includes a second parallel port expansion unit, and the second parallel port expansion unit is used to externally connect an interface device required by the embedded chip system.

[0017] In a second aspect, an embodiment of the present invention provides a method for executing a downloaded program in an embedded chip system, which is applied to the embedded chip system in the first aspect, and the method for executing a downloaded program includes:

[0018] When the program memory control pin of the main control module is set to a high level, the embedded chip system executes a CPU on-chip download program, and the CPU on-chip download program is used to download the application program to the corresponding target BANK space of the extended program memory;

[0019] The target BANK space is determined through the output of the first parallel port expansion unit and the cooperation of the second CPLD unit, and then the corresponding BANK program is written into the target BANK space. After the BANK program is written into the target BANK space, another target BANK space is determined, and the corresponding BANK program continues to be written into another target BANK space until all BANK spaces are written.

[0020] In a third aspect, an embodiment of the present invention provides an application program execution method for an embedded chip system, which is applied to the embedded chip system of the first aspect, and the application program execution method includes:

[0021] When the program memory control pin of the main control module is at a low level, the embedded chip system executes the program of the CPU off-chip extended program memory. During the execution of the program of the CPU off-chip extended program memory, the BANK programs automatically complete the jump switching according to the program modules compiled in different BANK spaces.

[0022] In a fourth aspect, an embodiment of the present invention provides an embedded device, wherein the embedded chip system described in the embodiment of the first aspect is provided in the embedded device.

[0023] The embedded chip system according to the embodiment of the present invention has at least the following beneficial effects: the embodiment of the present invention expands the program storage space and data storage space of the embedded system, and is no longer limited to the 64Kbyte limit of the single-chip computer, and through the BANK technology of the program memory and the paging technology of the data memory, the storage space is expanded to 512Kbytes, meeting the needs of large-scale application programs and record data storage space, and through the state switching control of the program memory, the application program can be downloaded on-site, and it is no longer necessary to use a burner to burn the program, meeting the need for updating the application program on-site. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of the overall structure of an embedded chip system provided by an embodiment of the present invention;

[0025] Figure 2 It is a circuit schematic diagram of a main control module of an embedded chip system provided by an embodiment of the present invention;

[0026] Figure 3 It is a circuit schematic diagram of a first CPLD unit of an embedded chip system provided by an embodiment of the present invention;

[0027] Figure 4 A chip selection signal address allocation diagram generated by a first CPLD of an embedded chip system provided by an embodiment of the present invention;

[0028] Figure 5 is a circuit schematic diagram of a second CPLD unit of an embedded chip system provided by an embodiment of the present invention;

[0029] Figure 6 It is a schematic diagram of an extended program memory circuit of an embedded chip system provided by an embodiment of the present invention;

[0030] Figure 7 It is a schematic diagram of BNAK partition of an extended program memory of an embedded chip system provided by an embodiment of the present invention;

[0031] Figure 8 It is a schematic diagram of an extended data memory circuit of an embedded chip system provided by an embodiment of the present invention;

[0032] Fig. 9 It is a schematic diagram of paging of an extended data memory of an embedded chip system provided by an embodiment of the present invention;

[0033] Fig.10 It is a circuit schematic diagram of a power-off protection unit of an embedded chip system provided by an embodiment of the present invention;

[0034] Fig.11 It is a circuit schematic diagram of a first parallel port expansion unit of an embedded chip system provided by an embodiment of the present invention;

[0035] Fig.12 It is a circuit schematic diagram of a second parallel port expansion unit of an embedded chip system provided by an embodiment of the present invention;

[0036] Fig.13 It is a schematic diagram of an address latch circuit of an embedded chip system provided by an embodiment of the present invention;

[0037] Fig.14is a schematic diagram of a data bus driver circuit of an embedded chip system provided by an embodiment of the present invention;

[0038] Fig.15 is a schematic diagram of a space restriction unit circuit of an embedded chip system provided by an embodiment of the present invention;

[0039] Fig.16 The figure is a schematic diagram of the download program and application program operation of the embedded chip system provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0040] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0041] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0042] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0043] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0044] The concepts involved in the present invention are explained below:

[0045] BANK partitioning technology: usually used for memory management, it allows physical memory to be divided into multiple independent areas, each area is called a BANK. This technology can improve memory utilization and access efficiency, and make memory management more flexible;

[0046] CPLD: Complex Programmable Logic Device, a digital integrated circuit that allows users to construct logic functions according to their needs. CPLD is mainly composed of programmable logic macrocells (MacroCell) and programmable interconnection matrices, and is suitable for implementing various digital circuit designs. CPLD programming is usually completed through an integrated development software platform. Schematics, hardware description languages ​​and other methods can be used to generate target files, and then the code is transferred to the target chip through a download cable;

[0047] SRAM: Static Random Access Memory, a high-speed memory that can save internal storage data without a refresh circuit.

[0048] The control method of the embodiment of the present invention is further described below based on the accompanying drawings.

[0049] Reference Figure 1 , Figure 1 The present invention provides an overall structural schematic diagram of an embedded chip system provided in an embodiment of the present invention. In a first aspect, the present invention provides an embedded chip system in an embodiment, and the embedded chip system includes: a main control module 100, an extended program memory 200 connected to the main control module 100, an extended data memory 300, a power-off protection unit 400, a first CPLD unit 500, a second CPLD unit 600, a first parallel port extension unit 700, a second parallel port extension unit 800, an extended clock module 900, an extended MCU read-write module 1000, an extended liquid crystal interface 1100, an address latch 1200, a bus driver 1300 and a program memory limiting unit 1400.

[0050] In some optional embodiments, the embedded chip system includes: a main control module 100, an extended program memory 200, an extended data memory 300, a first CPLD unit 500, a second CPLD unit 600 and a first parallel port expansion unit 700, wherein the main control module 100 includes an on-chip program memory, the extended program memory 200 is used to store the application program of the embedded chip system, and the storage space of the extended program memory 200 is divided into a plurality of program spaces accessible by the CPU itself; the extended data memory 300 is used to store the data of the embedded chip system, and the storage space of the extended data memory 300 is divided into a plurality of data spaces accessible by the CPU itself space; the first parallel port expansion unit 700 includes a first expansion port and a second expansion port, the first expansion port is used for the high address expansion of the expansion program memory, and the second expansion port is used for the high address expansion of the expansion data memory; the first CPLD unit 500 is used to generate a chip select signal of the external expansion interface according to the address signal of the main control module, and the external expansion interface includes the first parallel port expansion unit; the second CPLD unit 600 is used to control the state conversion of the expansion program memory 200 according to the control signal of the main control module 100, to control the access to the high address expansion port of the expansion program memory 200, and to control the access to the high address expansion port of the expansion data memory 300. In the technical solution of the present embodiment, the storage space of the embedded system program and the data storage space are expanded by expanding the program memory 200 and the data storage memory 300, and are no longer limited to the 64Kbytes limitation of the single-chip microcomputer. The storage space is expanded to 512Kbytes through the BANK technology of the program memory and the paging technology of the data memory, which meets the needs of large-scale applications and record data storage space. In addition, by controlling the state switching of the program memory, the application can be downloaded on-site, and there is no need to use a burner to burn the program, which meets the need for updating the application on-site.

[0051] In some optional embodiments, based on the above embodiments, the embedded chip system also includes an extended external device unit, which is connected to the chip of the extended device through a data bus and a control signal, and the extended external device unit includes an extended clock module 900, an extended MCU read-write module 1000 and an extended liquid crystal interface 1100.

[0052] In some optional embodiments, the embedded chip system may further include an address latch 1200 , and the address latch 1200 is used to latch the lower 8 bits of the system address.

[0053] In some optional embodiments, the embedded chip system further includes a bus driver unit for enhancing the bus driving capability, and the bus driver unit is controlled by the second CPLD unit so that the data bus is isolated from the external device unit. Through the design of the bus driver unit, on the one hand, the driving capability of the bus is enhanced, and on the other hand, it can be controlled by the second CPLD unit so that the data bus is isolated from the external device unit.

[0054] In some optional embodiments, the embedded chip system further includes a power-off protection unit, through which the extended data memory is protected from power failure, the power-off protection unit is connected to a battery unit, and the battery unit is used to continuously supply power to the power-off protection unit; when the embedded chip system loses power, the power-off protection unit generates a high-level chip select signal so that the internal data of the extended data memory is not lost. That is, the extended data memory of the embedded chip system has a power-off protection function, so when the embedded chip system loses power, the power-off protection unit can generate a high-level chip select signal to ensure that the extended data memory will not be rewritten and its internal data will not be lost.

[0055] In some optional embodiments, the embedded chip system also includes a space restriction unit, and the space restriction unit is used to expand the size of the program memory when it is used, and the size is determined according to the number of BANK spaces. The used area needs to be connected, and the unused area needs to be shielded. The technical solution of this embodiment can be understood as that, since the size of the area when the program memory is expanded is determined according to the number of BANK areas, the area to be used needs to be connected, and the unused area needs to be shielded. The method of using it is to connect the high address signal through a jumper cap to make it conductive, or to ground and shield.

[0056] In some optional embodiments, the external expansion interface includes a second parallel port expansion unit 800, which is used to connect an interface device required by the embedded chip system. The second parallel port expansion unit 800 can enable the embedded chip system to connect to more types of external devices.

[0057] Specifically, the main control module 100, the schematic diagram is as follows Figure 2 As shown, the main control module 100 includes an on-chip program memory, and the main external connection signals include data bus AD0-AD7, high address bus A8-A15, read and write signals RD and WR, address latch signal ALE, program memory read signal PSEN, etc. The present invention takes the high-speed single-chip microcomputer represented by DS87C520 as an example, and its one machine cycle is 4 clocks, while the ordinary single-chip microcomputer is 12 clocks, plus the clock frequency of 33MHZ supported by itself, which is equivalent to the ordinary single-chip microcomputer running at a frequency of 99MHZ, and also provides a dual data pointer function.

[0058] Specifically, the expansion program memory 200, the schematic diagram is as follows Figure 6 As shown, U4 uses 29F040 FLASH chip with a capacity of 512Kbytes and an erase and burn number of 100,000 times. The main connection signals are data bus AD0-AD7, connected to the CPU; address bus A0-A7 low address connected to address latch U8, A8-A14 address connected to the CPU, read and write RD, WR and chip select signal OE connected to U17, and high address A15 (ROM)-A18 (ROM) connected to the ROM space limit unit.

[0059] The specific BANK partition diagram is as follows Figure 7 shown.

[0060] The second CPLD logic relationship of U17-MACH111 is:

[0061] A15_ROM = A15;ROM

[0062] A16_ROM = PA0;

[0063] A17_ROM = PA1;

[0064] A18_ROM = PA2;

[0065] The correspondence with the extended parallel port can be obtained.

[0066] Among them, A15_ROM = A15. This connection method indicates that the full address space of a bank is (0000H-FFFFH):

[0067] The corresponding relationship is as follows:

[0068] PA2PA1PA0

[0069] 000 points to BANK0

[0070] 001 points to BANK1

[0071] 010 points to BANK2

[0072] 011 points to BANK3

[0073] 100 points to BANK4

[0074] 101 points to BANK5

[0075] 110 points to BANK6

[0076] 111 points to BANK7

[0077] The address 7F80H for accessing the parallel port can point to the 8255-1 PA port, and BANK switching can be achieved through changes in the PA port, that is, changes in A16_ROM, A17_RMM, and A18_ROM.

[0078] The use of 2BANK, 4BANK or 8BANK is determined based on the size of the total application.

[0079] Specifically, the extended data storage device 300, the schematic diagram is as follows Figure 8 As shown, the U6 chip uses M5M5408, and the SRAM has a capacity of 512Kbytes. The specific paging diagram is as follows Fig. 9 As shown. The main connection signals are data bus D0-D7, connected to bus driver U7; address bus A0-A7 low address connected to address latch U8, A8-A14 high address connected to CPU; read and write RD, WR connected to CPU, chip select signal CS0 (1) 'connected to power-off protection unit U10, high address A15 (RAM) - A18 (RAM) connected to U17-MACH111.

[0080] According to the U17-MACH111 CPLD logic relationship:

[0081] A15_RAM = A15*PC0;SRAM

[0082] A16_RAM = A15*PC1;

[0083] A17_RAM = A15*PC2;

[0084] A18_RAM = A15*PC3

[0085] The correspondence with the extended parallel port can be obtained.

[0086] When A15=1 (high level), address space (8000H-FFFFH):

[0087] Get: PC3PC2PC1PC0

[0088] 0001 points to page 1

[0089] 0010 points to page 2

[0090] …………

[0091] 1111 points to page 15

[0092] By accessing the parallel port address 7F82H, the change of the 8255-1 PC port causes the change of A15_RAM, A16_RAM, A17_RAM, and A18_RAM to achieve paging.

[0093] When A15=0 (low level), the address space is (0000H-7EFFH), at this time A15_RAM=0; A16_RAM=0; A17=0; RAM_A18_RAM=0, ensuring that the SRAM 0000H-7EFFH space is accessed. This part of the area is Fig. 9 The middle page is 0, which can be used to store various variables used in C-51 programming.

[0094] Specifically, the power-off protection unit 400, the schematic diagram is as follows: Fig.10 As shown, U10 uses MAX691 chip, and MAX691 is connected to BAT-CR2032 lithium battery. Through pin 2 VOUT, the 32nd pin of M5M5408 is powered. When VCC is greater than the battery voltage and reset level, VOUT is connected to VCC. When VCC is lower than the battery voltage and reset level, VOUT is connected to VBAT, and the lithium battery continues to supply power.

[0095] You can see Figure 8 The CS chip select CS0(1)' signal of pin 22 of U6-M5M5408 is received Fig.10 In the U10-MAX691, the CEO pin 12 is not directly connected to the chip select CS0(1) pin because when the power is turned off, the CS0(1) pin will become low level, which is equivalent to chip selection. CS0(1) is connected to the CEI input of U10 pin 13 and the CEO output of pin 12 because the MAX691 has a power-off protection mechanism. Only when CS0(1) is low and the power supply voltage is above the reset level and the power is normally supplied, the CS0(1)' signal will output a low level to select the SRAM chip.

[0096] MAX691 also has a watchdog function. The level is flipped by T1 input. If it does not flip within about 1.6S, the circuit is reset and the system restarts.

[0097] The first CPLD unit 500, schematic diagram is as follows Figure 3 As shown, the model of U15 is MACH111, which is mainly used to generate chip select signals for expansion chips. The signal input on the left side mainly includes address signals A4-A15 and control signal T0, which are connected to the CPU; the signal output on the right side, the chip select signal is connected to various expansion devices.

[0098] The address allocation diagram is as follows Figure 4 As shown, each address space is obtained by decoding the A4-A15 address of input U15.

[0099] In MCS-51, the external I / O interface address is uniformly addressed together with the address of the external data memory, that is, the I / O address is part of the external data memory address space, and is allocated to the expansion chip occupying the data memory 7F00H-7FFFH range space. Access to the expansion chip is achieved by accessing this space, realizing the chip select function.

[0100] The chip select signal of the above external expansion chip is also controlled by the input pin T0 of CPLD U15. The chip select signal is valid only when T0=1 (high level). When T0=0 (low level), the chip select signal is invalid and the peripheral expansion chip will not be selected.

[0101] Specifically, the second CPLD unit 600, the schematic diagram is as follows Figure 5 As shown, the model of U17 is MACH111, which mainly completes the control of the read and write state of the extended program memory 200 and the access control of the high-order address extension port of the extended program memory 200 and the access control of the high-order address extension port of the extended data memory 300. The left signal input, the control signals mainly include PSEN, RD, WR, T0, connected to the CPU, the high-order address signals include PA0-PA3, PC0-PC3, connected to the U5 extended parallel port unit, and A15 connected to the CPU; the right signal output, mainly includes control signals CE (ROM), RD (ROM), WR (ROM), connected to the program memory U4, the data bus enable signal EN (245) is connected to the data bus driver U7, the data memory high-order address A15 (RAM)-A18 (RAM) is connected to the data memory U6, and A15' (ROM)-A18' (ROM) is connected to the ROM space limiting unit. The control of the high-order address of the program memory and the data memory has been given above. The implementation method of the read and write state and the running state conversion of the program memory is detailed in the download program execution steps.

[0102] Reference Figure 1 In some embodiments of the present invention, the embedded chip system further includes a parallel port expansion unit (external expansion interface), and the parallel port expansion unit mainly includes:

[0103] The first parallel port expansion unit 700, such as Fig.11 As shown, the main connection signals are data bus D0-D7, connected to bus driver U7; address bus A0-A1 low address connected to CPU; read and write RD, WR connected to CPU, chip select signal CS4 connected to U15, PA0-PA3, PC0-PC3 connected to U17. U5 uses 82C55 to complete the program memory state conversion and the high address selection of program memory and data memory, among which port A is responsible for the high selection of extended program memory U4, and port C is responsible for the high selection of extended data memory U6.

[0104] The second parallel port expansion unit 800, such as Fig.12 As shown, the main connection signals are data bus D0-D7, connected to bus driver U7; address bus A0-A1 low address connected to CPU; read and write RD, WR connected to CPU, chip select signal CS5 connected to U15. U23 uses 82C55, some external expansion interfaces, control signals PA0'-PA7', PB0'-PB7', PC0'-PC7', to complete the control function of other external devices of the system;

[0105] It should be noted that the system also has some extended external device units, such as: extended clock 900, using DS12887, occupying chip select CS3, used as the system real-time clock; extended MCM read-write module 1000, occupying chip select CS1, completing the reading and writing of contactless cards; extended LCD interface 1100, which can be used to connect LCD or other LCD devices, occupying chip selects CS2 and CS8, respectively controlling the left and right halves of the dot matrix LCD screen, completing the display of the dot matrix LCD.

[0106] Reference Figure 1 In some embodiments of the present invention, the embedded chip system further includes an address latch 1200, and the address latch U8 is a 74HC573. Fig.13 As shown, the connection signals include AD0-AD7 data bus connected to the CPU, and address signals A0-A7 connected to U4, U6, U5, and U23, which mainly complete the latching of the lower 8-bit address A0-A7 in the system;

[0107] Reference Figure 1 In some embodiments of the present invention, the embedded chip system further includes a data bus driver 1300 (bus driver unit), such as Fig.14 As shown, the model is 74F245, the connection signals are AD0-AD7 data bus connected to the CPU, the driven bus signals D0-D7 are connected to U6, U5, U23, the control data direction signal is connected to the CPU's read signal RD, and the enable signal OE is connected to U17. The data bus driver, on the one hand, enhances the driving ability of the bus, and on the other hand, can control the connection or isolation of the data bus and the external expansion device unit through the second CPLD unit U17;

[0108] The space limiting unit 1400 selects the maximum number of BANK spaces through jumpers, such as Fig.15 As shown, the 1,2 connection and 2,3 connection of ROM1, ROM2, ROM3, and ROM4 are all realized through jumper caps.

[0109] ROM1---1,2 and 2,3 are connected in the same way, both are connected to A15, indicating that the size of a BANK area is 64Kbytes;

[0110] ROM2---2BANK, 4BANK, 8BANK all require 1-2 connection;

[0111] ROM3---2BANK requires 2-3 connection; 4BANK and 8BANK require 1-2 connection;

[0112] ROM4---2BANK and 4BANK, 2-3 connection; 8BANK, 1-2 connection.

[0113] The specific principle is to decide whether to use 2BANK, 4BANK or 8BANK according to the total compiled code size of the program. The unused BANK should be shielded because there is no program. The specific description is as follows:

[0114] When 2BNAK, PA0 is valid, PA2 and PA1 must be grounded to 0, shielding the BANK space behind, and only BANK0 and BANK1 have programs;

[0115] When 4BNAK, PA1 and PA0 are valid, PA2 should be grounded to 0, shielding the BANK space behind, and only BANK0, BANK1, BANK2, and BANK3 have programs;

[0116] When 8BNAK, PA2, PA1, and PA0 are all valid, and BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 all have programs.

[0117] Reference Fig.16 The embodiment of the present invention provides a program execution method for an embedded chip system, which is applied to the embedded chip system of the above-mentioned embodiment. The specific process of downloading the download program and running the application program includes:

[0118] When the program memory control pin of the main control module is set to a high level, the embedded chip system executes the CPU on-chip download program, and the CPU on-chip download program is used to download the application program to the target BANK space of the corresponding extended program memory; through the output of the first parallel port expansion unit and the cooperation of the second CPLD unit, the target BANK space is determined, and then the corresponding BANK program is written to the target BANK space. After completing the writing of the BANK program to the target BANK space, another target BANK space is determined, and the corresponding BANK program continues to be written to another target BANK space until all BANK spaces are written.

[0119] Specifically, first generate the burning file of the entire application. According to the program capacity, allocate the BANK area. After the compilation is completed, the program binary execution code of the BANK area will be generated. Taking 4BANK as an example, the HEX code of the four BANK areas *.B00, *.B01, *.B02, *.B03 will be generated. Use the tool software HEX2BIN.EXE to convert it into a burnable BIN file, *.BIA, *.BIB, *.BIC, *.BID, binary code. Correspond to BANK0, BANK1, BANK2, BANK3 respectively, the order cannot be wrong, one to one correspondence.

[0120] First set up Fig.15 The jumpers correspond to the number of BANK areas selected.

[0121] Figure 2 When the J1-1,2 pins of the main control module are short-circuited through jumper caps, EA=1, and the microcontroller runs the CPU on-chip program. The program space is 0000H-0FFFH, which is mainly used to download the program to the program memory.

[0122] Step S100: After the main control module 100 is powered on, the port is initialized first, and the working state of each expansion port is set;

[0123] Step S200: Set T0=1 and enter state 2, which is the extended interface working state;

[0124] Through the following U17-MACH111 CPLD logical relationship:

[0125] / RD_ROM = / PSEN*T0+ / RD* / T0; Program memory ROM read signal

[0126] / WR_ROM = / WR* / T0; Program memory ROM write signal

[0127] / EN_245 = T0; 74F245 bus driver enable

[0128] / CE_ROM = VCC

[0129] Since T0=1, the above expression will be simplified to:

[0130] RD_ROM = PSEN;

[0131] WR_ROM = 1;

[0132] EN_245 =0;

[0133] CE_ROM = 0;

[0134] It can be seen that at this time, the read and write signals of the program memory U4 are connected to the CPU's PSEN, the write signal is high (WR_ROM=1 cannot write to the chip), and the chip select CE is in the selected state. The data bus driver chip U7 is in working state, connected to the external interface I / O, and can operate the output port of U5 82C55-1.

[0135] Step S300: Set the BANK area to be written. Take the total BANK area as 4BANK as an example. When the PA port is 000, it points to BANK0. After writing, the A port state of U5 will be maintained, and the program storage area will also be maintained in the corresponding BANK area.

[0136] Step S400: Set T0=0 and enter state 1, which is the program storage area read-write state;

[0137] Through the following U17-MACH111 CPLD logical relationship:

[0138] / RD_ROM = / PSEN*T0+ / RD* / T0; Program memory ROM read signal

[0139] / WR_ROM = / WR* / T0; Program memory ROM write signal

[0140] / EN_245 = T0; 74F245 bus driver enable

[0141] / CE_ROM = VCC

[0142] Since T0=0, the above expression can be simplified to:

[0143] RD_ROM = RD;

[0144] WR_ROM = WR;

[0145] EN_245 =1;

[0146] CE_ROM =0;

[0147] It can be seen that at this time, the read and write signals of the program memory U4 are connected to the read and write signals of the CPU, and the chip select CE is in the selected state. The data bus driver chip U7 is in a non-working state, and all chip select signals generated by CPLD-U15 are also invalid and isolated from the external interface I / O.

[0148] At this time, the program memory becomes a FLASH memory that can be read and written by the CPU, and can be read and written according to the read and write timing requirements of the FLASH.

[0149] Step S500: read the BANK area program binary file to be written into the BANK area of ​​the corresponding program memory through the external serial port or the downloaded SPI chip interface;

[0150] Step S600: Determine whether it is the last BANK area. If not, start looping from step S200 until all BANKs are written, and then the download is completed.

[0151] Step S700: When the J1-2,3 pins of the main control module are short-circuited through the jumper cap, EA=0, and the single-chip microcomputer runs the CPU off-chip program memory program. After the system is powered on, T0, that is, P3.4 pin, is in the input state, and the pull-up resistor makes T0=1, and the system is in state 2. When the port is initialized, T0 must also be set to the output state, and the output is set to T0=1 high level. The BANK port is also initialized here.

[0152] Step S800: When executing the corresponding BANK area module according to the BANK set by the module during compilation, the application program will automatically complete the jump switch.

[0153] For example, when the program memory control pin of the main control module is at a low level, the embedded chip system executes the program in the CPU off-chip extended program memory. During the execution of the program in the CPU off-chip extended program memory, the BANK programs automatically jump and switch according to the program modules compiled in different BANK spaces.

[0154] The extended program memory of the embodiment of the present invention adopts BANK technology to partition the storage space. The hardware design has a maximum of 8 BANKs, each BANK is 64Kbytes. Since the KEIL C51 compiler can support a maximum of 32 BANKs, as long as the storage chip is large enough, such as Fujitsu MBM29F080A, which can reach 1Mbytes, it can be divided into 16 BANKs to meet the needs of large and more complex applications.

[0155] An embodiment of the present invention provides an embedded device, in which the above-mentioned embedded chip system is provided, which can at least realize the functions realized by the above-mentioned embedded chip system and achieve the beneficial effects of the above-mentioned embedded chip system, which will not be described in detail here.

[0156] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0157] Some aspects of the present disclosure are described above with reference to the block diagram and flow chart of the system, method, system and / or computer program product according to the exemplary embodiments.It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively.Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full.In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0158] Therefore, the blocks in the block diagrams and flow charts support the combination of devices for performing the specified functions, the combination of elements or steps for performing the specified functions, and the program instruction devices for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts and the combination of blocks in the block diagrams and flow charts can be implemented by a special-purpose hardware computer system or a combination of special-purpose hardware and computer instructions that performs a specific function, element or step.

[0159] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0160] Software components can be encoded with any of various programming languages. An exemplary programming language can be a low-level programming language, such as an assembly language associated with a specific hardware architecture and / or an operating system platform. The software component comprising assembly language instructions may need to be converted to executable machine code by an assembler before being executed by hardware architecture and / or platform. Another exemplary programming language can be a higher-level programming language, which can be transplanted across multiple architectures. The software component comprising a higher-level programming language may need to be converted to an intermediate representation by an interpreter or a compiler before execution. Other examples of programming languages ​​include but are not limited to macro languages, shells or command languages, job control languages, scripting languages, database queries or search languages ​​or report writing languages. In one or more exemplary embodiments, the software component comprising the instruction of one of the above-mentioned programming language examples can be directly executed by an operating system or other software components, without first being converted into another form.

[0161] Software components may be stored as files or other data storage structures. Software components of similar type or related functions may be stored together, such as in a specific directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0162] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. An embedded chip system, characterized in that: include: A main control module, including an on-chip program memory; An extended program memory, wherein the extended program memory is used to store application programs of the embedded chip system, and the storage space is divided into a plurality of program spaces accessible by the CPU's own addresses; An extended data memory, wherein the extended data memory is used to store data of the embedded chip system, and the storage space is divided into a plurality of data spaces accessible by the CPU itself; A first parallel port expansion unit, the first parallel port expansion unit comprising a first expansion port and a second expansion port, the first expansion port being used for high-order address expansion of the expansion program memory, and the second expansion port being used for high-order address expansion of the expansion data memory; a first CPLD unit, the first CPLD unit being used to generate a chip select signal of an external expansion interface according to an address signal of the main control module, the external expansion interface comprising the first parallel port expansion unit; A second CPLD unit, the second CPLD unit is used to control the state conversion of the extended program memory, perform access control on the high address extension port of the extended program memory, and perform access control on the high address extension port of the extended data memory according to the control signal of the main control module; In the case where the program memory control pin of the main control module is set to a high level, the embedded chip system executes a CPU on-chip download program, and the CPU on-chip download program is used to download the application program to the corresponding target BANK space of the extended program memory, and through the output of the first parallel port expansion unit and the cooperation of the second CPLD unit, the target BANK space is determined, and then the corresponding BANK program is written into the target BANK space. After the BANK program is written into the target BANK space, another target BANK space is determined, and the corresponding BANK program is continued to be written into another target BANK space until all BANK spaces are written; When the program memory control pin of the main control module is at a low level, the embedded chip system executes the program of the CPU off-chip extended program memory. During the execution of the program of the CPU off-chip extended program memory, jump switching is automatically completed between BANK programs according to program modules compiled in different BANK spaces.

2. The embedded chip system according to claim 1, characterized in that: The embedded chip system also includes an extended external device unit, which is connected to the chip of the extended device through a data bus and a control signal. The extended external device unit includes an extended clock module, an extended MCM read-write module and an extended liquid crystal module.

3. The embedded chip system according to claim 1, characterized in that: The embedded chip system also includes an address latch, through which the lower 8 bits of the system address are latched.

4. The embedded chip system according to claim 1, characterized in that: The embedded chip system further comprises a bus driving unit for enhancing the bus driving capability. The bus driving unit can also be controlled by the second CPLD unit so that the data bus is isolated from the external device unit.

5. The embedded chip system according to claim 1, characterized in that: The embedded chip system further comprises a power-off protection unit, through which the extended data memory is protected from power-off, the power-off protection unit is connected to a battery unit, and the battery unit is used to continuously supply power to the power-off protection unit; When the embedded chip system loses power, the power-off protection unit generates a high-level chip selection signal so that the internal data of the extended data memory is not lost.

6. The embedded chip system according to claim 1, characterized in that: The embedded chip system further comprises a space limiting unit. The area size of the extended program memory when in use is determined according to the number of BANK spaces. The space limiting unit is used to connect the used area and shield the unused area.

7. The embedded chip system according to claim 1, characterized in that: The external expansion interface includes a second parallel port expansion unit, and the second parallel port expansion unit is used for externally connecting an interface device required by the embedded chip system.

8. An embedded device, characterized in that: The embedded device is provided with the embedded chip system according to any one of claims 1 to 7.

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