System, method and device for realizing signal up-sampling rate and maintaining full power output, processor and computer readable storage medium thereof

Abstract

The invention relates to a system for realizing signal up-sampling rate and keeping full power output, which comprises a data input unit for receiving input original data; the data interpolation unit is used for interpolating different multiples according to the original data with different bandwidths and different sampling rates; the data power adjusting unit is used for adjusting the data to a full scale by utilizing linear calculation; a data storage unit; and the data sending unit is used for connecting the data in the DDR chip in parallel. The invention also relates to a method and a device for realizing signal up-sampling rate and keeping full power output processing, a processor and a readable storage medium thereof. By adopting the system, the method, the device, the processor and the computer readable storage medium for realizing the signal up-sampling rate and keeping the full-power output, resources occupied by software operation of an upper computer are reduced, mirror images caused by a radio frequency front-end filter are eliminated, the sampling rate and the bandwidth upper limit of the signal are improved, the signal can be output in a full-scale manner, and the full-power output of the signal is ensured. The signal-to-noise ratio of signals is improved, and the signal sampling rate and the transmission efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the field of communications, in particular to the fields of radar and audio, and specifically refers to a system, method, device, processor and computer-readable storage medium thereof for achieving signal upsampling rate and maintaining full power output. Background Art

[0002] Signal upsampling refers to increasing the sampling rate of a signal to a higher level for further processing or transmission. There are many ways to upsample, such as interpolation, resampling, digital upconversion, etc. FPGA is a programmable logic device that can implement various digital signal processing functions, such as filtering, modulation, demodulation, encoding, decoding, etc. FPGA has the advantages of parallel processing capability, high flexibility, low cost, and low power consumption, and is suitable for high-speed, high-performance signal processing applications. The power of a signal refers to the energy transmitted by the signal per unit time, usually expressed in decibels (dB) or decibel milliwatts (dBm). The power of a signal is related to factors such as the amplitude, frequency, and phase of the signal, and is also affected by the noise, distortion, and attenuation of the channel. The power of a signal is an important indicator of signal quality and an important goal of signal processing. Therefore, the FPGA algorithm that upsamples the signal and maintains full power output is a technology that improves the signal sampling rate and transmission efficiency without reducing the signal quality, and has important research value and application prospects. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a system, method, device, processor and computer-readable storage medium thereof that can achieve high signal sampling rate, high transmission efficiency and a wide range of applications while achieving signal upsampling rate and maintaining full power output.

[0004] In order to achieve the above-mentioned object, the system, method, device, processor and computer-readable storage medium thereof for realizing signal upsampling rate and maintaining full power output of the present invention are as follows:

[0005] The main feature of the system for achieving signal up-sampling rate and maintaining full power output is that the system comprises:

[0006] A data input unit, the output end of which is connected to the data storage unit, and is used to receive input raw data;

[0007] A data interpolation unit is connected to the data storage unit and is used to interpolate the input raw data using a CIC interpolation filter with a programmable interpolation multiple, and interpolate different multiples according to the raw data with different bandwidths and different sampling rates;

[0008] A data power adjustment unit is connected to the data storage unit, and the input end is also connected to the data interpolation unit, and is used to calculate the maximum absolute value of the data after interpolation, and adjust the data to full scale by linear calculation;

[0009] The data storage unit, whose output end is connected to the data sending unit, is used to store the input original data, the interpolated data, and the data with adjusted amplitude into the DDR chip, and continuously send the data to the output end as a source;

[0010] The data sending unit is used to parallel and serialize the data in the DDR chip.

[0011] Preferably, the data sending unit performs parallel and serial processing of the data in the DDR chip, so that the sampling rate of the data transmitted to the DAC is twice the working clock transmitted from the DDR chip to the data sending unit.

[0012] The method for realizing signal up-sampling rate and maintaining full power output processing by using the above system is mainly characterized in that the method comprises the following steps:

[0013] (1) Using the SDRAM protocol, the data is received from the host computer into the FPGA chip, and the signal is input into the DDR memory chip by using an asynchronous FIFO and controlling the internal reading and writing of the DDR;

[0014] (2) Control the internal reading and writing of DDR, output the stored data, and input it into the interpolation filter through the synchronous FIFO;

[0015] (3) interpolating the original input data using a CIC interpolation filter with a programmable interpolation multiple;

[0016] (4) Calculate the absolute maximum value of the entire segment of data after interpolation, and pass the interpolated data through the synchronous FIFO, and control the internal reading and writing of DDR to input into the DDR memory chip;

[0017] (5) Control the internal reading and writing of DDR, output the stored data, and input it into the power adjustment module through the synchronous FIFO;

[0018] (6) Normalizing the data by calculating the maximum absolute value of the data, calculating and adjusting the maximum value of the overall amplitude of the data to the full scale, and occupying all valid digits;

[0019] (7) The data after amplitude adjustment is input into the DDR memory chip through the synchronous FIFO and the internal reading and writing of the DDR is controlled;

[0020] (8) By controlling the internal reading and writing of DDR, the stored data is output and input into the data sending unit through the asynchronous FIFO;

[0021] (9) The data is converted from parallel to serial through the OSERDESE2 primitive and sent to the DAC for digital-to-analog conversion.

[0022] Preferably, in step (6), the maximum value of the overall amplitude of the data is calculated and adjusted to full scale, specifically:

[0023] Calculate and adjust the maximum value of the overall amplitude of the data to full scale according to the following formula:

[0024] Data fina =Data ever ×(Data full / Data abs_MAX );

[0025] Among them, Data fina For the final adjusted data, Data ever For each data, Data full is the maximum value of full-scale data, Data abs_MAX is the maximum value of the interpolated data.

[0026] The main feature of the device for realizing signal up-sampling rate and maintaining full power output processing is that the device comprises:

[0027] a processor configured to execute computer executable instructions;

[0028] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for increasing the sampling rate of the signal and maintaining full power output processing are implemented.

[0029] The processor for realizing signal upsampling rate and maintaining full power output processing has the main feature that the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the various steps of the above-mentioned method for realizing signal upsampling rate and maintaining full power output processing are implemented.

[0030] The main feature of the computer-readable storage medium is that a computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for achieving signal upsampling rate and maintaining full power output processing.

[0031] The system, method, device, processor and computer-readable storage medium for realizing signal up-sampling rate and maintaining full power output of the present invention are adopted. When the initial sampling rate of the original data is low, the sampling rate is increased by using filter convolution interpolation to avoid the occurrence of mirror images due to the inability of the RF end filter to completely filter; by transplanting the interpolation link on the host computer software to the FPGA chip, the resources occupied by the host computer software operation are greatly reduced, and the operation speed of the entire system is improved; by using the normalization algorithm to adjust the signal amplitude, the amplitude can be output at full scale after data interpolation. The sampling rate upper limit of the output signal is greatly improved by using OSERDESE2 resources. The present invention performs interpolation processing of different bandwidth data with different interpolation multiples, which not only reduces the resources occupied by the host computer software operation, but also eliminates the mirror images caused by the RF front-end filter, improves the sampling rate and bandwidth upper limit of the signal, and enables the signal to be output at full scale, significantly improving the signal-to-noise ratio, and improving the performance of the signal transmitter from all angles. The technology of improving the signal sampling rate and transmission efficiency without reducing the signal quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The present invention is a flow chart of a method for realizing signal up-sampling rate and maintaining full power output processing.

[0033] Figure 2 The figure is a schematic diagram of the DDR internal read and write control of the system for realizing signal up-sampling rate and maintaining full power output of the present invention. DETAILED DESCRIPTION

[0034] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0035] The system of the present invention for achieving signal up-sampling rate and maintaining full power output comprises:

[0036] A data input unit, the output end of which is connected to the data storage unit, and is used to receive input raw data;

[0037] A data interpolation unit is connected to the data storage unit and is used to interpolate the input raw data using a CIC interpolation filter with a programmable interpolation multiple, and interpolate different multiples according to the raw data with different bandwidths and different sampling rates;

[0038] A data power adjustment unit is connected to the data storage unit, and the input end is also connected to the data interpolation unit, and is used to calculate the maximum absolute value of the data after interpolation, and adjust the data to full scale by linear calculation;

[0039] The data storage unit, whose output end is connected to the data sending unit, is used to store the input original data, the interpolated data, and the data with adjusted amplitude into the DDR chip, and continuously send the data to the output end as a source;

[0040] The data sending unit is used to parallel and serialize the data in the DDR chip.

[0041] As a preferred embodiment of the present invention, the data sending unit serializes the data in the DDR chip in parallel, so that the sampling rate of the data transmitted to the DAC is twice the working clock transmitted from the DDR chip to the data sending unit.

[0042] The method for realizing signal up-sampling rate and maintaining full power output processing by using the above system is mainly characterized in that the method comprises the following steps:

[0043] (1) Using the SDRAM protocol, the data is received from the host computer into the FPGA chip, and the signal is input into the DDR memory chip by using an asynchronous FIFO and controlling the internal reading and writing of the DDR;

[0044] (2) Control the internal reading and writing of DDR, output the stored data, and input it into the interpolation filter through the synchronous FIFO;

[0045] (3) interpolating the original input data using a CIC interpolation filter with a programmable interpolation multiple;

[0046] (4) Calculate the absolute maximum value of the entire segment of data after interpolation, and pass the interpolated data through the synchronous FIFO, and control the internal reading and writing of DDR to input into the DDR memory chip;

[0047] (5) Control the internal reading and writing of DDR, output the stored data, and input it into the power adjustment module through the synchronous FIFO;

[0048] (6) Normalizing the data by calculating the maximum absolute value of the data, calculating and adjusting the maximum value of the overall amplitude of the data to the full scale, and occupying all valid digits;

[0049] (7) The data after amplitude adjustment is input into the DDR memory chip through the synchronous FIFO and the internal reading and writing of the DDR is controlled;

[0050] (8) By controlling the internal reading and writing of DDR, the stored data is output and input into the data sending unit through the asynchronous FIFO;

[0051] (9) The data is converted from parallel to serial through the OSERDESE2 primitive and sent to the DAC for digital-to-analog conversion.

[0052] As a preferred embodiment of the present invention, the step (6) of calculating and adjusting the maximum value of the overall amplitude of the data to the full scale is specifically as follows:

[0053] Calculate and adjust the maximum value of the overall amplitude of the data to full scale according to the following formula:

[0054] Data fina =Data ever ×(Data full / Data abs_MAX );

[0055] Among them, Data fina For the final adjusted data, Data ever For each data, Data full is the maximum value of full-scale data, Data abs_MAX is the maximum value of the interpolated data.

[0056] The main feature of the device for realizing signal up-sampling rate and maintaining full power output processing of the present invention is that the device comprises:

[0057] a processor configured to execute computer executable instructions;

[0058] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for increasing the sampling rate of the signal and maintaining full power output processing are implemented.

[0059] The processor for realizing signal upsampling rate and maintaining full power output processing of the present invention has the main feature that the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the various steps of the above-mentioned method for realizing signal upsampling rate and maintaining full power output processing are implemented.

[0060] The computer-readable storage medium of the present invention has the main feature of storing a computer program thereon, which can be executed by a processor to implement the various steps of the above-mentioned method for achieving signal upsampling rate and maintaining full power output processing.

[0061] In a specific embodiment of the present invention, it involves an FPGA algorithm for increasing the sampling rate of a signal and maintaining full power output, which is applied to the fields of communication, radar, and audio, and can improve the signal sampling rate and transmission efficiency without reducing the signal quality.

[0062] The device comprises a data input unit, a data storage unit, a data interpolation unit, a data power adjustment unit, and a data sending unit;

[0063] The data input unit, as the chip input, communicates with the host computer and is responsible for receiving the input raw data.

[0064] The data storage unit stores the input original data, interpolated data, and amplitude-adjusted data into the DDR chip, and continuously sends data to the output end as a source.

[0065] The data interpolation unit uses a CIC interpolation filter with a programmable interpolation multiple to interpolate the input raw data, and interpolates different multiples according to the raw data with different bandwidths and different sampling rates.

[0066] The data power adjustment unit first calculates the maximum absolute value of the data after interpolation, and then uses linear calculation to adjust the data to full scale, which effectively improves the signal-to-noise ratio and increases the final signal power.

[0067] The data sending unit parallels and serializes the final data in the DDR chip so that the sampling rate of the data transmitted to the DAC is twice the working clock transmitted from the DDR chip to the data sending unit.

[0068] Implementing this method includes the following steps:

[0069] (1) Using the SDRAM protocol, the data is received from the host computer into the FPGA chip, and the signal is input into the DDR memory chip by using an asynchronous FIFO and controlling the internal reading and writing of the DDR;

[0070] (2) Control the internal reading and writing of DDR, output the stored data, and input it into the interpolation filter through the synchronous FIFO;

[0071] (3) Using a CIC interpolation filter with a programmable interpolation multiple to interpolate the original input data to increase the sampling rate, so that it can eliminate the image caused by the filter width being too high;

[0072] (4) Calculate the maximum absolute value of the entire segment of interpolated data, and input the interpolated data into the DDR memory chip through the synchronous FIFO and control the internal reading and writing of DDR;

[0073] (5) Control the internal reading and writing of DDR, output the stored data, and input it into the power adjustment module through the synchronous FIFO;

[0074] (6) The data is normalized by calculating the maximum absolute value of the data, and then the maximum value of the overall amplitude of the data is adjusted to the full scale to occupy all valid digits;

[0075] The calculation formula is as follows:

[0076] Data fina =Data ever×(Data full / Data abs_MAX );

[0077] Among them, Data fina For the final adjusted data, Data ever For each data, Data full is the maximum value of full-scale data, Data abs_MAX is the maximum value of the interpolated data.

[0078] (7) The data after amplitude adjustment is input into the DDR memory chip through the synchronous FIFO and the internal reading and writing of the DDR is controlled;

[0079] (8) By controlling the internal reading and writing of DDR, the stored data is output and input into the data sending unit through the asynchronous FIFO;

[0080] (9) By converting the data into parallel and serial form through the OSERDESE2 primitive, the upper limit of the final signal sampling rate can be increased while ensuring the stability of the clock operation of the FPGA internal chip, and then the data is sent to the DAC for digital-to-analog conversion.

[0081] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0082] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0083] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0084] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0085] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0086] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0087] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0088] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0089] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0090] The system, method, device, processor and computer-readable storage medium for realizing signal up-sampling rate and maintaining full power output of the present invention are adopted. When the initial sampling rate of the original data is low, the sampling rate is increased by using filter convolution interpolation to avoid the occurrence of mirror images due to the inability of the RF end filter to completely filter; by transplanting the interpolation link on the host computer software to the FPGA chip, the resources occupied by the host computer software operation are greatly reduced, and the operation speed of the entire system is improved; by using the normalization algorithm to adjust the signal amplitude, the amplitude can be output at full scale after data interpolation. The sampling rate upper limit of the output signal is greatly improved by using OSERDESE2 resources. The present invention performs interpolation processing of different bandwidth data with different interpolation multiples, which not only reduces the resources occupied by the host computer software operation, but also eliminates the mirror images caused by the RF front-end filter, improves the sampling rate and bandwidth upper limit of the signal, and enables the signal to be output at full scale, significantly improving the signal-to-noise ratio, and improving the performance of the signal transmitter from all angles. The technology of improving the signal sampling rate and transmission efficiency without reducing the signal quality.

[0091] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system for achieving signal upsampling rate and maintaining full power output, characterized in that: The system comprises: A data input unit, the output end of which is connected to the data storage unit, and is used to receive input raw data; A data interpolation unit is connected to the data storage unit and is used to interpolate the input raw data using a CIC interpolation filter with a programmable interpolation multiple, and interpolate different multiples according to the raw data with different bandwidths and different sampling rates; A data power adjustment unit is connected to the data storage unit, and the input end is also connected to the data interpolation unit, and is used to calculate the maximum absolute value of the data after interpolation, and adjust the data to full scale by linear calculation; The data storage unit, whose output end is connected to the data sending unit, is used to store the input original data, the interpolated data, and the data with adjusted amplitude into the DDR chip, and continuously send the data to the output end as a source; The data sending unit is used to parallel and serialize the data in the DDR chip.

2. The system for achieving signal upsampling rate and maintaining full power output according to claim 1, characterized in that: The data sending unit performs parallel and serial processing of the data in the DDR chip, so that the sampling rate of the data transmitted to the DAC is twice the working clock transmitted from the DDR chip to the data sending unit.

3. A method for realizing signal upsampling rate and maintaining full power output processing based on the system of claim 1, characterized in that: The method comprises the following steps: (1) Using the SDRAM protocol, the data is received from the host computer into the FPGA chip, and the signal is input into the DDR memory chip by using an asynchronous FIFO and controlling the internal reading and writing of the DDR; (2) Control the internal reading and writing of DDR, output the stored data, and input it into the interpolation filter through the synchronous FIFO; (3) interpolating the original input data using a CIC interpolation filter with a programmable interpolation multiple; (4) Calculate the absolute maximum value of the entire segment of data after interpolation, and pass the interpolated data through the synchronous FIFO, and control the internal reading and writing of DDR to input into the DDR memory chip; (5) Control the internal reading and writing of DDR, output the stored data, and input it into the power adjustment module through the synchronous FIFO; (6) Normalizing the data by calculating the maximum absolute value of the data, calculating and adjusting the maximum value of the overall amplitude of the data to the full scale, and occupying all valid digits; (7) The data after amplitude adjustment is input into the DDR memory chip through the synchronous FIFO and the internal reading and writing of the DDR is controlled; (8) By controlling the internal reading and writing of DDR, the stored data is output and input into the data sending unit through the asynchronous FIFO; (9) The data is converted from parallel to serial through the OSERDESE2 primitive and sent to the DAC for digital-to-analog conversion.

4. The method for realizing signal upsampling rate and maintaining full power output processing according to claim 3, characterized in that: In step (6), the maximum value of the overall amplitude of the data is calculated and adjusted to the full scale, specifically: Calculate and adjust the overall amplitude maximum value of the data to full scale according to the following formula: Date fina =Date ever ×(Date full / Date abs_MAX ); Among them, Data fina For the final adjusted data, Data ever For each data, Data full is the maximum value of full-scale data, Data abs_MAX is the maximum value of the interpolated data.

5. A device for achieving signal upsampling rate and maintaining full power output processing, characterized in that: The device comprises: a processor configured to execute computer executable instructions; A memory storing one or more computer executable instructions, wherein when the computer executable instructions are executed by the processor, the steps of the method for realizing signal upsampling rate and maintaining full power output processing as described in any one of claims 3 to 4 are implemented.

6. A processor for achieving signal upsampling rate and maintaining full power output processing, characterized in that: The processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for realizing signal upsampling rate and maintaining full power output processing described in any one of claims 3 to 4 are implemented.

7. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for realizing signal upsampling rate and maintaining full power output processing as described in any one of claims 3 to 4.

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