Bus signal processing method and device of server, equipment and storage medium

Abstract

The invention provides a bus signal processing method and device of a server, equipment and a storage medium, and relates to the technical field of servers. According to the specific implementation scheme, multiple paths of first signals, based on a first protocol, of a CPU are transmitted to a CPLD of a mainboard; converting the first signal into a second signal based on a second protocol by using a CPLD (Complex Programmable Logic Device) of the mainboard; transmitting the second signal to a CPLD (Complex Programmable Logic Device) of the SCM through a communication interface; and converting the second signal into a third signal based on the first protocol by using the CPLD of the SCM, and transmitting the third signal to the BMC chip. According to the scheme, when the number of certain standard signal interfaces cannot meet the design requirement of the server, another signal interface can be reused for signal transmission, so that the cost of the server is reduced, and the convenience of assembly, operation and maintenance is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of servers, and in particular to a bus signal processing method, device, equipment and storage medium of a server. Background Art

[0002] In the DC-SCM Association standard technical specifications, the DC-SCM interface only contains 2 serial busses. Summary of the invention

[0003] The present disclosure provides a bus signal processing method, apparatus, device and storage medium for a server.

[0004] According to one aspect of the present disclosure, a bus signal processing method of a server is provided, comprising:

[0005] Transmitting multiple first signals of the CPU based on the first protocol to the CPLD of the mainboard;

[0006] Using the CPLD of the mainboard to convert the first signal into a second signal based on a second protocol;

[0007] transmitting the second signal to the CPLD of the SCM through the communication interface;

[0008] The second signal is converted into a third signal based on the first protocol by using the CPLD of the SCM and then transmitted to the BMC chip.

[0009] According to another aspect of the present disclosure, a bus signal processing device of a server is provided, comprising:

[0010] A first transmission module, used for transmitting multiple first signals based on a first protocol from the CPU to the CPLD of the mainboard;

[0011] A first conversion module, used for converting the first signal into a second signal based on a second protocol by using the CPLD of the mainboard;

[0012] A second transmission module, used for transmitting the second signal to the CPLD of the SCM through the communication interface;

[0013] The second conversion module is used to convert the second signal into a third signal based on the first protocol by using the CPLD of the SCM and then transmit the third signal to the BMC chip.

[0014] According to another aspect of the present disclosure, there is provided an electronic device, comprising:

[0015] at least one processor; and

[0016] a memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute any method in the embodiments of the present disclosure.

[0018] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute any method according to the embodiments of the present disclosure.

[0019] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, which implements any method according to the embodiments of the present disclosure when executed by a processor.

[0020] According to the solution of the embodiment of the present disclosure, when the number of a certain standard signal interface cannot meet the server design requirements, another signal interface can be reused for signal transmission, thereby reducing server costs and improving the convenience of assembly and operation and maintenance.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0023] Figure 1 is a flow chart of a bus signal processing method of a server provided according to an embodiment of the present disclosure;

[0024] Figure 2 It is a structural diagram of a server provided according to an embodiment of the present disclosure connected with an external module based on a DC-SCM specification;

[0025] Figure 3 is a structural diagram of a bus signal processing device of a server provided according to an embodiment of the present disclosure;

[0026] Figure 4 is a block diagram of an electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0028] In the related art, ARM (Advanced RISC Machines) servers require multiple serial busses. For example, Ampere One series processors based on ARM architecture launched by Ampere Computing require four serial ports for a single-socket server with one processor, and six for a dual-socket server with two processors. Obviously, the standard definition of the DC-SCM protocol cannot meet the serial port requirements of ARM servers.

[0029] In order to at least partially solve one or more of the above-mentioned problems and other potential problems, an embodiment of the present invention provides a bus signal processing method for a server. By utilizing the technical solution of the embodiment of the present invention, a certain type of standard signal interface can be converted into a signal of another protocol, and the latter interface can be multiplexed to realize the transmission of the former signal, thereby meeting the multi-interface requirements of the server.

[0030] Terminology explanation:

[0031] DC-SCM (Data Center Secure Control Module): DC-SCM is a standard interface for data centers that aims to simplify the management and control of servers. DC-SCM usually includes interfaces such as power management, hardware monitoring, security modules, and serial ports.

[0032] DC-SCI (Data Center Secure Control Interface): is an interface standard for data center servers, usually used to transmit control signals and data between the server motherboard and external modules (such as BMC modules, management modules). DC-SCI is part of the DC-SCM (Data Center Secure Control Module) standard, which aims to provide a secure and reliable communication path to help manage and monitor various hardware functions of the server.

[0033] CPLD (Complex Programmable Logic Device): CPLD is a programmable logic device widely used in hardware design to implement simple logic control functions. In this solution, CPLD is used to convert serial port protocol to SGPIO protocol and vice versa.

[0034] BMC (Baseboard Management Controller) is a dedicated microcontroller on the server motherboard, responsible for managing and monitoring the hardware status of the server.

[0035] SGPIO (Serial General Purpose Input / Output): SGPIO is a serial interface standard used to transmit status information between multiple devices. It is often used to connect storage devices, indicator lights, and other status signals on the motherboard.

[0036] LVDS (Low-Voltage Differential Signaling): Suitable for high-speed, low-power signal transmission, commonly used in video data, data transmission buses, etc.

[0037] LTPI (Low-Power Transmission Protocol Interface): Suitable for low-power, high-speed communication scenarios such as mobile devices and embedded systems.

[0038] UART (Universal Asynchronous Receiver / Transmitter): used for serial communication, commonly used in debugging interfaces and low-speed device communications.

[0039] SPI (Serial Peripheral Interface): used for high-speed communication between devices, such as memory and sensor interfaces.

[0040] I2C (Inter-Integrated Circuit): Used for multi-master and multi-slave communication of low-speed peripheral devices, such as sensors, EEPROM, etc.

[0041] I3C (Improved Inter-Integrated Circuit): An upgraded version of I2C, supporting higher data rates and more complex device topologies.

[0042] GPIO (General Purpose Input / Output): used for simple control and status signals.

[0043] PCIe (Peripheral Component Interconnect Express): used for high-speed data transmission.

[0044] SMBus (System Management Bus): SMBus is often used for system management, such as power management, temperature monitoring, etc.

[0045] CAN Bus (Controller Area Network): CAN bus is used in control systems in the fields of industrial automation, automotive electronics, etc.

[0046] JTAG (Joint Test Action Group): JTAG is used for hardware debugging and programming.

[0047] Ethernet: In scenarios where long-distance transmission or network connection is required, you can consider converting the signal into Ethernet protocol for transmission.

[0048] Figure 1 FIG. 1 is a flow chart of a bus signal processing method of a server provided by an embodiment of the present disclosure. Figure 1 As shown, the method comprises at least the following steps:

[0049] S101, transmitting multiple first signals based on a first protocol from a CPU to a CPLD of a mainboard.

[0050] In the disclosed embodiment, when the number of a certain type of interface of the target device or board (such as a security management board) connected to the mainboard is insufficient, the multi-channel signals generated by the CPU (such as UART signals, I2C signals or SPI signals) cannot be transmitted. The multi-channel signals of the CPU can be connected to the CPLD of the mainboard on the mainboard.

[0051] S102: Use the CPLD of the mainboard to convert the first signal into a second signal based on a second protocol.

[0052] In the disclosed embodiment, the CPLD of the mainboard is used to perform protocol conversion, converting the first protocol into the second protocol to obtain the second signal.

[0053] The first agreement includes any of the following:

[0054] UART protocol, SPI protocol, I2C protocol, SMBus protocol, CAN Bus protocol or JTAG protocol.

[0055] The second agreement includes any of the following:

[0056] SGPIO protocol, LVDS protocol, I3C protocol, LTPI protocol, PCIe protocol or Ethernet protocol.

[0057] S103, transmitting the second signal to the CPLD of the SCM through the communication interface.

[0058] In the disclosed embodiment, multiple first signals are converted into one second signal, and then the second signal is transmitted to the CPLD of the SCM using a communication interface based on the second protocol.

[0059] S104: Use the CPLD of the SCM to convert the second signal into a third signal based on the first protocol and transmit the third signal to the BMC chip.

[0060] In the disclosed embodiment, the CPLD of the SCM is used to perform protocol conversion again to convert the second signal into a third signal, and the third signal can be completely the same as the first signal. Subsequently, the CPLD of the SCM transmits the third signal to the BMC chip.

[0061] According to the solution of the embodiment of the present disclosure, when the number of a certain standard signal interface cannot meet the server design requirements, signal transmission can be performed by multiplexing another signal interface without the need for additional hardware cable design, thereby reducing server costs and improving the convenience of assembly and operation and maintenance.

[0062] In a possible implementation, step S102 uses the CPLD of the mainboard to convert the first signal into a second signal based on the second protocol, including the steps of:

[0063] S1021. Extract first data information from the first signal using the CPLD of the mainboard.

[0064] S1022: Map the first data information to a signal format of a second protocol to obtain first converted data.

[0065] S1023 , serially integrate the first conversion data corresponding to the multiple first signals to obtain intermediate data.

[0066] S1024. Pack and encapsulate the intermediate data according to the second protocol to obtain a second signal.

[0067] In the disclosed embodiment, the CPLD of the mainboard parses the protocol of each input first signal, extracts the required data and control information, such as the start and stop bits of the UART, the clock and data line status of the SPI, etc., to obtain the first data information.

[0068] According to preset requirements, the CPLD of the mainboard maps the parsed first data information into the signal format of the second protocol. This step involves converting the data frame, address information, etc. in the first protocol into a format that adapts to the second protocol, such as converting a UART data stream into a bit stream of SGPIO or a differential signal of LVDS.

[0069] The CPLD of the mainboard integrates the first conversion data corresponding to the multiple first signals according to the requirements of the second protocol to obtain intermediate data. For example, multiple UART signals are serialized to form one SGPIO signal, or multiple SPI signals are packaged into one LVDS signal.

[0070] The CPLD of the mainboard encapsulates the integrated signal according to the specification of the second protocol, generates a data frame or signal format that conforms to the second protocol, and obtains a second signal. For example, the intermediate data is packaged into a bit frame of SGPIO, or an LVDS data stream is generated through a differential signal.

[0071] According to the solution of the embodiment of the present disclosure, the CPLD of the mainboard is used to perform protocol conversion, thereby facilitating the reuse of the communication interface.

[0072] In a possible implementation, step S1023 serializes and integrates the first conversion data corresponding to the multiple first signals to obtain intermediate data, including the steps of:

[0073] The CPLD of the mainboard is used to synchronize the multiple first signals through the internal clock management unit to obtain the timing information of the multiple first signals.

[0074] According to the timing information and / or priority information of the multiple channels of first signals, the first conversion data corresponding to the multiple channels of first signals are serially integrated to obtain intermediate data.

[0075] In the disclosed embodiment, the CPLD of the mainboard synchronizes the input signals through the internal clock management unit to ensure that all signals are processed within a unified clock cycle. If there are differences in priority among the multiple first signals, the CPLD of the mainboard will select the transmission order of the first signals or perform bandwidth allocation according to the preset priority rules.

[0076] According to the solution of the embodiment of the present disclosure, when integrating multiple signals, it is ensured that all signals are processed within a unified clock cycle, thereby avoiding timing conflicts in signal transmission, and at the same time giving priority to the transmission of the first signal with a high priority.

[0077] In a possible implementation, step S1024 packages and encapsulates the intermediate data according to the second protocol to obtain a second signal, including the steps of:

[0078] According to the second protocol, the intermediate data, the error detection code and the frame header and frame tail information are packaged and encapsulated to obtain a second signal.

[0079] In the disclosed embodiment, the CPLD of the mainboard encapsulates the integrated signal according to the specification of the second protocol, generates a data frame or signal format that conforms to the second protocol, and obtains a second signal. For example, the processed data is packaged into a bit frame of SGPIO, or an LVDS data stream is generated through a differential signal. When generating the second signal, the CPLD of the mainboard adds an error detection code, such as a cyclic redundancy check (CRC) and frame header and frame tail information.

[0080] The solution according to the embodiment of the present disclosure helps to ensure the integrity and reliability of signals during transmission.

[0081] In a possible implementation, step S103 transmits the second signal to the CPLD of the SCM through the communication interface, including:

[0082] The second signal is transmitted to the CPLD of the SCM through a designated communication interface of the DC-SCM.

[0083] In such Figure 2 In the example shown, the server motherboard is connected to the external module based on the DC-SCI interface standard, where some interfaces are connected to the BMC chip and some interfaces are connected to the DC-SCM board, including SGPIO#0 and SGPIO#1, and the second signal can be transmitted to the CPLD of the SCM through one of the two. SGPIO uses a set of serial signal lines to transmit more complex status information between multiple devices.

[0084] According to the solution of the embodiment of the present disclosure, multiple first signals can be serialized and then transmitted through one communication interface.

[0085] In a possible implementation, step S104 uses the CPLD of the SCM to convert the second signal into a third signal based on the first protocol and transmits the third signal to the BMC chip, including the steps of:

[0086] S1041. Utilize the CPLD of the SCM to extract second data information from the second signal, and reformat it into the format of the first protocol to obtain second converted data.

[0087] S1042. According to the definition of the first protocol, re-encapsulate the second converted data into multiple frames or data packets to obtain multiple third signals.

[0088] S1043: Transmit multiple third signals from designated pins to the BMC chip.

[0089] In the disclosed embodiment, the CPLD of the SCM receives a second signal from the mainboard CPLD through the DC-SCM interface. The CPLD of the SCM first performs synchronization processing on the received second signal to ensure that the data has a unified clock reference when entering the CPLD. The CPLD identifies the protocol type used by the second signal, such as SGPIO, LVDS, etc. According to the predetermined format of the protocol, the CPLD begins to parse the data in the signal. If the second signal is encapsulated into a frame, the CPLD first parses the frame header information to understand the starting position of the frame, the signal type, and other control information. The CPLD extracts the actual data content from the received second signal according to the protocol specification. This step usually involves unpacking the data from the serial stream and storing it in the internal register or FIFO of the CPLD. Subsequently, the CPLD reformats the data extracted from the second protocol format into the format of the first protocol. For example, the bit stream of SGPIO is converted to the byte stream of UART, or the serial data of LVDS is converted to the signal format of I2C.

[0090] The CPLD of the SCM repackages the converted data into a frame or data packet of the first protocol according to the definition of the first protocol, for example, generating a start bit, data bit, check bit and stop bit according to the provisions of UART, or generating a data word according to the requirements of SPI.

[0091] The CPLD of the SCM generates a signal output that complies with the first protocol to obtain a third signal. The third signal may include a generated clock signal (such as the clock of SPI), a data line state (such as the SDA line of I2C), and a control signal (such as the high and low levels of GPIO).

[0092] The CPLD of the SCM outputs the packaged first protocol signal from the designated pin to the BMC. At this point, the signal has been converted back to the original protocol format, such as UART, SPI, I2C, etc., for BMC processing or communication.

[0093] According to the solution of the embodiment of the present disclosure, two CPLDs are used to convert multiple signals twice, thereby realizing interface multiplexing and completing the transmission of multiple first signals.

[0094] In a possible implementation, step S1041 uses the CPLD of the SCM to extract the second data information from the second signal and reformat it into the format of the first protocol to obtain the second converted data, including the steps of:

[0095] The second data information is extracted from the second signal using the CPLD of the SCM.

[0096] The error detection code included in the second data information is verified.

[0097] When the verification is successful, the second data information is reformatted into the format of the first protocol to obtain second converted data.

[0098] In the disclosed embodiment, the CPLD of the SCM verifies the error detection code (such as CRC check) in the received second signal to ensure that no error occurs in the signal during transmission. If the check fails, the CPLD may need to send an error signal or request retransmission. If the check succeeds, the second data information is reformatted into the format of the first protocol to obtain the second converted data.

[0099] After parsing the data, the SCM's CPLD can perform further checks on the data's integrity to ensure there are no missing or distorted data bits.

[0100] According to the solution of the embodiment of the present disclosure, not only the transmission of multiple first signals in the absence of corresponding interfaces is achieved, but also the integrity and reliability of the first signals in transmission are improved.

[0101] In a possible implementation, the first protocol includes any one of the following:

[0102] UART protocol, SPI protocol, I2C protocol, SMBus protocol, CAN Bus protocol or JTAG protocol.

[0103] In a possible implementation, the second protocol includes any one of the following:

[0104] SGPIO protocol, LVDS protocol, I3C protocol, LTPI protocol, PCIe protocol or Ethernet protocol.

[0105] In the disclosed embodiment, the first protocol is usually a low-speed protocol, and the second protocol is usually a high-speed protocol. Therefore, when the first signal is transmitted through the interface of the second protocol, it usually does not affect the transmission of related signal data of the second protocol. In one example, the bandwidth of the multiplexed second protocol can be controlled, for example, only 10% of the bandwidth can be allowed to be multiplexed by the signal of the first protocol in each time window.

[0106] In another possible implementation, Figure 2 As shown, the two serial ports (UART) of the server motherboard are directly connected to the corresponding serial ports of the BMC chip to transmit serial port signals, but at least two serial port signals are still not obtained by the BMC. The bus signal processing method of the server of the embodiment of the present disclosure includes at least the following steps:

[0107] The first step is that the CPLD on the motherboard needs to convert multiple serial port signals from the CPU into SGPIO signals, including:

[0108] CPLD receives data from multiple serial ports and encodes each serial port data into SGPIO signals. Because SGPIO is serial, multiple serial port data can be combined into one SGPIO signal line through multiplexing.

[0109] Each serial port data can be assigned to the SGPIO time slot according to a certain timing to ensure integrity and sequence.

[0110] Finally, the SGPIO signal generated by the CPLD is sent to the DC-SCM interface, ready to be transmitted to the SCM module.

[0111] The second step is to transmit SGPIO signals through the DC-SCM interface.

[0112] The third step is to restore the SGPIO signal to the serial port signal.

[0113] In the SCM module, the CPLD needs to convert the received SGPIO signal back to the serial port signal and pass it to the BMC, including:

[0114] The CPLD receives the SGPIO signal from the DC-SCM interface and decodes it into the original serial port data stream according to the timing information.

[0115] Using the same logic previously coded in the mainboard CPLD, the data in the time slot is extracted and assigned to the corresponding serial port.

[0116] Reconstruct the decoded data into a standard UART signal, including the start bit, data bit, parity bit, and stop bit. Ensure that the reconstructed UART signal conforms to the format and baud rate of the original serial port data.

[0117] The reconstructed serial port signal is sent to the BMC. The BMC receives the data through its GPIO or UART interface and performs corresponding management and control operations.

[0118] Throughout the process, timing and synchronization are critical. The mainboard CPLD and SCM module CPLD need to maintain clock synchronization to ensure that the decoding and encoding of the SGPIO signal remain consistent. Synchronization can be achieved using the clock signal provided by the DC-SCM interface or through internal clock management.

[0119] Through the above steps, the CPU's multi-channel serial port data can be transmitted between the mainboard and the SCM module through the SGPIO signal, and finally restored to the serial port signal on the BMC side, realizing efficient transmission and management of multi-serial port data.

[0120] It should be noted that when the number of serial ports cannot meet the server requirements, for example, Ampere One's single-channel server requires 4 serial interfaces, and a dual-channel server requires 6 serial ports, but the DC-SCM specification only has 2 serial ports, so 2 or 4 serial port information cannot be transmitted. In this regard, the practice in related technologies is usually to select 2 CPU serial ports to connect to the BMC chip on the DC-SCM module, but this solution will result in the lack of monitoring of some information, which greatly increases the difficulty of operation and maintenance.

[0121] Another method is to design a pair of connectors and cables separately, and connect the remaining four serial ports of the CPU on the motherboard to the BMC of the DC-SCM through jumper connection. This will increase the cost and assembly complexity, and make it impossible to operate and maintain the DC-SCM without opening the cover. Specifically, if a standard DC-SCM connector is used, the DC-SCM can be directly unplugged from the back of the chassis like an OCP (Open Compute Project) network card without opening the chassis cover. However, after adding this jumper cable, the DC-SCM module can only be unplugged from the back of the chassis by opening the chassis cover and unplugging the jumper cable, which causes inconvenience to operation and maintenance.

[0122] Figure 3 FIG. 1 is a schematic diagram of the structure of a bus signal processing device of a server provided by an embodiment of the present disclosure. Figure 3 As shown, the device at least includes:

[0123] The first transmission module 301 is used to transmit multiple first signals based on the first protocol of the CPU to the CPLD of the mainboard.

[0124] The first conversion module is used to convert the first signal into a second signal based on a second protocol by using the CPLD of the mainboard.

[0125] The second transmission module is used to transmit the second signal to the CPLD of the SCM through the communication interface.

[0126] The second conversion module is used to convert the second signal into a third signal based on the first protocol by using the CPLD of the SCM and then transmit the third signal to the BMC chip.

[0127] In a possible implementation manner, the first conversion module is used to:

[0128] The first data information is extracted from the first signal using the CPLD of the mainboard.

[0129] The first data information is mapped to a signal format of a second protocol to obtain first converted data.

[0130] The first conversion data corresponding to the multiple first signals are serially integrated to obtain intermediate data.

[0131] According to the second protocol, the intermediate data is packaged and encapsulated to obtain a second signal.

[0132] In a possible implementation manner, the first conversion module is used to:

[0133] The CPLD of the mainboard is used to synchronize the multiple first signals through the internal clock management unit to obtain the timing information of the multiple first signals.

[0134] According to the timing information and / or priority information of the multiple channels of first signals, the first conversion data corresponding to the multiple channels of first signals are serially integrated to obtain intermediate data.

[0135] In a possible implementation manner, the first conversion module is used to:

[0136] According to the second protocol, the intermediate data, the error detection code and the frame header and frame tail information are packaged and encapsulated to obtain a second signal.

[0137] In a possible implementation manner, the second transmission module is used to:

[0138] The second signal is transmitted to the CPLD of the SCM through a designated communication interface of the DC-SCM.

[0139] In a possible implementation manner, the second conversion module is used to:

[0140] The second data information is extracted from the second signal by using the CPLD of the SCM, and reformatted into the format of the first protocol to obtain second converted data.

[0141] According to the definition of the first protocol, the second converted data is repackaged into a plurality of frames or data packets to obtain a plurality of third signals.

[0142] Transmit multiple third signals from designated pins to the BMC chip.

[0143] In a possible implementation manner, the second conversion module is used to:

[0144] The second data information is extracted from the second signal using the CPLD of the SCM.

[0145] The error detection code included in the second data information is verified.

[0146] When the verification is successful, the second data information is reformatted into the format of the first protocol to obtain second converted data.

[0147] In a possible implementation, the first protocol includes any one of the following:

[0148] UART protocol, SPI protocol, I2C protocol, SMBus protocol, CAN Bus protocol or JTAG protocol.

[0149] In a possible implementation, the second protocol includes any one of the following:

[0150] SGPIO protocol, LVDS protocol, I3C protocol, LTPI protocol, PCIe protocol or Ethernet protocol.

[0151] For the description of specific functions and examples of each module and submodule of the device in the embodiment of the present disclosure, reference can be made to the relevant description of the corresponding steps in the above method embodiment, which will not be repeated here.

[0152] In the technical solution disclosed herein, the acquisition, storage and application of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0153] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0154] Figure 4 A schematic block diagram of an example electronic device 400 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0155] like Figure 4 As shown, the device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the device 400 can also be stored. The computing unit 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0156] A number of components in the device 400 are connected to the I / O interface 405, including: an input unit 406, such as a keyboard, a mouse, etc.; an output unit 407, such as various types of displays, speakers, etc.; a storage unit 408, such as a disk, an optical disk, etc.; and a communication unit 409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 409 allows the device 400 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0157] The computing unit 401 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 401 performs the various methods and processes described above, such as the bus signal processing method of the server. For example, in some embodiments, the bus signal processing method of the server may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded into the RAM 403 and executed by the computing unit 401, one or more steps of the bus signal processing method of the server described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to execute the bus signal processing method of the method server in any other appropriate manner (eg, by means of firmware).

[0158] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0159] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0160] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0161] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0162] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0163] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0164] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0165] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A bus signal processing method for a server, comprising: Transmitting multiple first signals of the CPU based on the first protocol to the CPLD of the mainboard; Using the CPLD of the mainboard to convert the first signal into a second signal based on a second protocol; Transmitting the second signal to the CPLD of the SCM through the communication interface; The second signal is converted into a third signal based on the first protocol by using the CPLD of the SCM and then transmitted to the BMC chip.

2. The method according to claim 1, wherein: Converting the first signal into a second signal based on a second protocol using the CPLD of the mainboard includes: Extracting first data information from the first signal using the CPLD of the mainboard; Mapping the first data information to a signal format of a second protocol to obtain first converted data; Serializing and integrating the first conversion data corresponding to the multiple first signals to obtain intermediate data; The intermediate data is packaged and encapsulated according to the second protocol to obtain a second signal.

3. The method according to claim 2, wherein: Serializing and integrating the first conversion data corresponding to the multiple first signals to obtain intermediate data, including: Using the CPLD of the mainboard to synchronize the multiple first signals through an internal clock management unit to obtain timing information of the multiple first signals; According to the timing information and / or priority information of the multiple channels of the first signals, the first conversion data corresponding to the multiple channels of the first signals are serially integrated to obtain intermediate data.

4. The method according to claim 2, wherein: Packaging and encapsulating the intermediate data according to the second protocol to obtain a second signal includes: According to the second protocol, the intermediate data, the error detection code and the frame header and frame tail information are packaged and encapsulated to obtain a second signal.

5. The method according to claim 1, wherein: Transmitting the second signal to the CPLD of the SCM through the communication interface includes: The second signal is transmitted to the CPLD of the SCM through a designated communication interface of the DC-SCM.

6. The method according to claim 1, wherein: The method of converting the second signal into a third signal based on the first protocol by using the CPLD of the SCM and transmitting the third signal to the BMC chip includes: Extracting second data information from the second signal using the CPLD of the SCM, and reformatting the second data information into the format of the first protocol to obtain second converted data; According to the definition of the first protocol, re-encapsulate the second converted data into a plurality of frames or data packets to obtain a plurality of third signals; The multiple third signals are transmitted from the designated pins to the BMC chip.

7. The method according to claim 6, wherein: Utilizing the CPLD of the SCM to extract second data information from the second signal and reformat it into the format of the first protocol to obtain second converted data, including: extracting second data information from the second signal using the CPLD of the SCM; verifying the error detection code included in the second data information; If the verification is successful, the second data information is reformatted into the format of the first protocol to obtain second converted data.

8. The method according to claim 1, wherein: The first protocol includes any one of the following: UART protocol, SPI protocol, I2C protocol, SMBus protocol, CAN Bus protocol or JTAG protocol.

9. The method according to claim 1, wherein: The second protocol includes any one of the following: SGPIO protocol, LVDS protocol, I3C protocol, LTPI protocol, PCIe protocol or Ethernet protocol.

10. A bus signal processing device for a server, comprising: A first transmission module, used for transmitting multiple first signals based on a first protocol from the CPU to the CPLD of the mainboard; A first conversion module, used for converting the first signal into a second signal based on a second protocol by using the CPLD of the mainboard; A second transmission module, used for transmitting the second signal to the CPLD of the SCM through the communication interface; The second conversion module is used to use the CPLD of the SCM to convert the second signal into a third signal based on the first protocol and then transmit the third signal to the BMC chip.

11. The device according to claim 10, wherein: The first conversion module is used for: Extracting first data information from the first signal using the CPLD of the mainboard; Mapping the first data information to a signal format of a second protocol to obtain first converted data; Serializing and integrating the first conversion data corresponding to the multiple first signals to obtain intermediate data; The intermediate data is packaged and encapsulated according to the second protocol to obtain a second signal.

12. The device according to claim 11, wherein The first conversion module is used for: Using the CPLD of the mainboard to synchronize the multiple first signals through an internal clock management unit to obtain timing information of the multiple first signals; According to the timing information and / or priority information of the multiple channels of the first signals, the first conversion data corresponding to the multiple channels of the first signals are serially integrated to obtain intermediate data.

13. The device according to claim 11, wherein: The first conversion module is used for: According to the second protocol, the intermediate data, the error detection code and the frame header and frame tail information are packaged and encapsulated to obtain a second signal.

14. The device according to claim 10, wherein: The second transmission module is used for: The second signal is transmitted to the CPLD of the SCM through a designated communication interface of the DC-SCM.

15. The device according to claim 10, wherein: The second conversion module is used for: Extracting second data information from the second signal using the CPLD of the SCM, and reformatting the second data information into the format of the first protocol to obtain second converted data; According to the definition of the first protocol, re-encapsulate the second converted data into a plurality of frames or data packets to obtain a plurality of third signals; The multiple third signals are transmitted from the designated pins to the BMC chip.

16. The device according to claim 16, wherein: The second conversion module is used for: extracting second data information from the second signal using the CPLD of the SCM; verifying the error detection code included in the second data information; If the verification is successful, the second data information is reformatted into the format of the first protocol to obtain second converted data.

17. The device according to claim 10, wherein: The first protocol includes any one of the following: UART protocol, SPI protocol, I2C protocol, SMBus protocol, CAN Bus protocol or JTAG protocol.

18. The device according to claim 10, wherein: The second protocol includes any one of the following: SGPIO protocol, LVDS protocol, I3C protocol, LTPI protocol, PCIe protocol or Ethernet protocol.

19. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9.

20. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-9.

21. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 9.

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