In-memory computing device based on weight updating
By introducing a weight update module into the in-memory computing device, the delay and power consumption problems caused by frequent read and write in traditional in-memory computing are solved, and more efficient computing performance and energy efficiency are achieved.
Patent Information
- Application Number
- CN202411382355.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-01-07
AI Technical Summary
Traditional in-memory computing devices require frequent read and write during frequent data update operations, resulting in large delay and power consumption overhead. Especially when rewriting to the memory unit after simple logic operations, there is redundant operation, resulting in waste of performance and energy efficiency. .
A in-memory computing device based on weight update is designed, including an external control module, a 6TSRAM module and a weight update module. Through the weight update module, the calculation results are directly written to the 6TSRAM module to avoid redundant read and write operations.
It effectively improves the performance and energy efficiency of in-memory computing, reduces the delay and power consumption overhead of weight updates, and improves computing efficiency.
Smart Images
Figure CN119271620A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to an in-memory computing device based on weight updating, belonging to the technical field of in-memory computing. Background Art
[0002] In order to effectively solve the bottlenecks of "storage wall" and "power consumption wall" caused by frequent data movement in the von Neumann architecture, in-memory computing technology came into being. After the traditional in-memory computing device completes the logical operation inside the memory, if the calculation result needs to be rewritten to the storage array, it is necessary to read the calculation result first, and then write the read data to the storage array through a write operation. For operations involving frequent data updates, in-memory computing technology will cause large delays and power consumption overhead due to the need for frequent reading and writing. In particular, for operations that need to rewrite the calculation results to the storage unit after performing simple logical operations, the current in-memory computing devices perform a large number of redundant operations, resulting in delays and waste of power consumption. Summary of the invention
[0003] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide an in-memory computing device based on weight updating, which can directly write the calculation results into the 6TSRAM module after the calculation is completed, thereby effectively avoiding redundant read and write operations, thereby improving the performance and energy efficiency of in-memory computing.
[0004] To achieve the above object, the present invention is implemented by adopting the following technical solutions: The present invention discloses an in-memory computing device based on weight updating, comprising an external control module, a 6TSRAM module, a computing module and a weight updating module; The external control module is connected to the control terminals of the calculation module and the weight update module respectively to realize the control of the calculation process and the weight update process; The 6TSRAM module is used to store weight data; The calculation module is used to obtain external real-time data; and calculate corresponding calculation data according to the external real-time data and the weight data; The weight updating module is used to convert the calculated data into weight data and store it in the 6TSRAM module to achieve weight updating.
[0005] Further, the 6TSRAM module includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4; the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 together form a back-to-back inverter to store weight data; The gate of the first transistor M1 is connected to the gate of the second transistor M2 and the QB terminal of the back-to-back inverter; the drain of the first transistor M1 is connected to the drain of the second transistor M2 and the Q terminal of the back-to-back inverter; the source of the first transistor M1 is connected to the power supply voltage; the source of the second transistor M2 is grounded; The gate of the third transistor M3 is connected to the gate of the fourth transistor M4 and the Q end of the back-to-back inverter; the drain of the third transistor M3 is connected to the drain of the fourth transistor M4 and the QB end of the back-to-back inverter; the source of the third transistor M3 is connected to the power supply voltage; the source of the fourth transistor M4 is grounded; Further, the 6TSRAM module further includes a fifth transistor M5 and a sixth transistor M6; One end of the fifth transistor M5 is connected to the QB end of the back-to-back inverter, and the other end of the fifth transistor M5 is connected to the first bit line BLB; One end of the sixth transistor M6 is connected to the Q end of the back-to-back inverter, and the other end of the sixth transistor M6 is connected to the second bit line BL.
[0006] Further, the weight updating module includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14; The drain of the seventh transistor M7 is connected to the drain of the eighth transistor M8; the drain of the ninth transistor M9 is connected to the drain of the tenth transistor M10; the drain of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12; the drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14; The source of the seventh transistor M7 is connected to the power supply voltage; the QB end of the back-to-back inverter is respectively connected to the source of the eighth transistor M8 and the source of the ninth transistor M9; the source of the eleventh transistor M11 is connected to the power supply voltage; The source of the tenth transistor M10 is grounded; the Q end of the back-to-back inverter is connected to the source of the twelfth transistor M12 and the source of the thirteenth transistor M13 respectively; the source of the fourteenth transistor M14 is grounded; The calculation result Z output by the calculation module is respectively connected to the gate of the seventh transistor M7 and the gate of the tenth transistor M10; the reverse calculation result ZN output by the calculation module is respectively connected to the gate of the eleventh transistor M11 and the gate of the fourteenth transistor M14; The control signal CTRL output by the external control module is connected to the gate of the ninth transistor M9 and the gate of the thirteenth transistor M13 respectively; the reverse control signal CTRLN output by the external control module is connected to the gate of the eighth transistor M8 and the gate of the twelfth transistor M12 respectively.
[0007] Further, the calculation module includes a latch, a logic calculation unit and a calculation inverter D1, and the calculation data includes a calculation result Z and a reverse calculation result ZN; The input end of the Latch latch is connected to the Q end of the back-to-back inverter and the output end of the external control module respectively, and the output end of the Latch latch is connected to the input end of the logic calculation unit; The input end of the logic calculation unit is also connected to the output end of the external data module; the output end of the logic calculation unit is respectively connected to the input end of the weight update module and the calculation inverter D1; The output end of the calculation inverter is connected to the input end of the weight update module; The external data module is used to output external real-time data; The Latch latch is used to obtain weight data of the back-to-back inverters; The logic calculation unit is used to calculate and obtain a corresponding calculation result Z according to the external real-time data and the weight data; The calculation inverter D1 is used to obtain a reverse calculation result ZN according to the calculation result Z.
[0008] Further, the logic calculation unit includes an AND gate logic state and; In response to the logic calculation unit being in the AND gate logic state and, if the output signal of the Latch latch and the output signal of the external data module are both high level, the output result of the logic calculation unit is high level; otherwise, the output result of the logic calculation unit is low level.
[0009] Further, in response to the in-memory computing device being in a computing state, the control signal CTRL output by the external control module is controlled to be at a low level, and the reverse control signal CTRLN is at a high level, so that the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12 and the thirteenth transistor M13 are turned off, and the Latch latch is turned on.
[0010] Further, in response to the in-memory computing device being in a weight update state, the control signal CTRL output by the external control module is controlled to be high, and the reverse control signal CTRLN is low, so that the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, the Latch latch is turned off, and the weight update operation starts, including: When the calculation result Z is a high level, the tenth transistor M10 and the eleventh transistor M11 are turned on, the Q end of the back-to-back inverter is charged to a high level, and the QB end of the back-to-back inverter is discharged to a low level to perform a data storage operation; When the calculation result Z is low level, the seventh transistor M7 and the fourteenth transistor M14 are turned on, the Q end of the back-to-back inverter is discharged to low level, and the QB end of the back-to-back inverter is charged to high level to perform data storage operation.
[0011] Compared with the prior art, the present invention has the following beneficial effects: The in-memory computing device based on weight update of the present invention, through the cooperation of the external control module, the 6TSRAM module, the computing module and the weight update module, can directly write the calculation result into the 6TSRAM module via the weight update module after the computing module completes the calculation, thereby effectively avoiding redundant read and write operations, thereby improving the performance and energy efficiency of in-memory computing. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 It is a schematic diagram of the structure of an in-memory computing device based on weight updating. DETAILED DESCRIPTION
[0013] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.
[0014] This embodiment provides an in-memory computing device based on weight update, such as Figure 1 As shown, it includes an external control module, a 6TSRAM module, a calculation module and a weight update module; The external control module is connected to the control terminals of the calculation module and the weight update module respectively to realize the control of the calculation process and the weight update process; 6TSRAM module, used to store weight data; A calculation module, used to obtain external real-time data; and calculate corresponding calculation data according to the external real-time data and the weight data; The weight update module is used to convert the calculated data into weight data and store it in the 6TSRAM module to achieve weight update.
[0015] The technical concept of the present invention is: through the cooperation of the external control module, the 6TSRAM module, the calculation module and the weight update module, after the calculation module completes the calculation, the calculation result Z can be directly written into the 6TSRAM module via the weight update module, effectively avoiding redundant read and write operations, thereby improving the performance and energy efficiency of in-memory calculations.
[0016] Specifically, the in-memory computing device based on weight update of the present invention mainly includes the following modules: 1. 6TSRAM module.
[0017] The 6TSRAM module includes a back-to-back inverter for storing data and two read-write transistors for reading and writing data.
[0018] The 6TSRAM module includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4; the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 together form a back-to-back inverter to store weight data; The gate of the first transistor M1 is connected to the gate of the second transistor M2 and the QB terminal of the back-to-back inverter; the drain of the first transistor M1 is connected to the drain of the second transistor M2 and the Q terminal of the back-to-back inverter; the source of the first transistor M1 is connected to the power supply voltage; the source of the second transistor M2 is grounded; The gate of the third transistor M3 is connected to the gate of the fourth transistor M4 and the Q end of the back-to-back inverter; the drain of the third transistor M3 is connected to the drain of the fourth transistor M4 and the QB end of the back-to-back inverter; the source of the third transistor M3 is connected to the power supply voltage; and the source of the fourth transistor M4 is grounded.
[0019] The 6TSRAM module further includes a fifth transistor M5 and a sixth transistor M6, where the fifth transistor M5 and the sixth transistor M6 are read-write transistors.
[0020] One end of the fifth transistor M5 is connected to the QB end of the back-to-back inverter, and the other end of the fifth transistor M5 is connected to the first bit line BLB; One end of the sixth transistor M6 is connected to the Q end of the back-to-back inverter, and the other end of the sixth transistor M6 is connected to the second bit line BL.
[0021] 2. Weight update module.
[0022] The weight updating module includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14; The drain of the seventh transistor M7 is connected to the drain of the eighth transistor M8; the drain of the ninth transistor M9 is connected to the drain of the tenth transistor M10; the drain of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12; the drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14; The source of the seventh transistor M7 is connected to the power supply voltage; the QB end of the back-to-back inverter is respectively connected to the source of the eighth transistor M8 and the source of the ninth transistor M9; the source of the eleventh transistor M11 is connected to the power supply voltage; The source of the tenth transistor M10 is grounded; the Q end of the back-to-back inverter is connected to the source of the twelfth transistor M12 and the source of the thirteenth transistor M13 respectively; the source of the fourteenth transistor M14 is grounded; The calculation result Z output by the calculation module is respectively connected to the gate of the seventh transistor M7 and the gate of the tenth transistor M10; the reverse calculation result ZN output by the calculation module is respectively connected to the gate of the eleventh transistor M11 and the gate of the fourteenth transistor M14; The control signal CTRL output by the external control module is connected to the gate of the ninth transistor M9 and the gate of the thirteenth transistor M13 respectively; the reverse control signal CTRLN output by the external control module is connected to the gate of the eighth transistor M8 and the gate of the twelfth transistor M12 respectively.
[0023] It should be noted that the eleventh transistor M11 in this embodiment needs to be turned on when the calculation result Z is 1 and turned on when Z is 0, and the eleventh transistor M11 is a PMOS transistor, which is turned on when the gate is 0, so it is necessary to introduce the inversion of the calculation result Z; similarly, the fourteenth transistor M14 needs to be turned off when Z is 1 and turned on when Z is 0, and the fourteenth transistor M14 is an NMOS transistor, which is turned on when the gate is 1, so it is also necessary to connect the inversion of the calculation result Z.
[0024] 3. Calculation module.
[0025] The calculation module includes a latch, a logic calculation unit and a calculation inverter D1, and the calculation data includes a calculation result Z and a reverse calculation result ZN.
[0026] The input end of the latch is connected to the Q end of the back-to-back inverter and the output end of the external control module respectively, and the output end of the latch is connected to the input end of the logic calculation unit; The input end of the logic calculation unit is also connected to the output end of the external data module; the output end of the logic calculation unit is respectively connected to the input end of the weight update module and the calculation inverter D1; The output of the computation inverter is connected to the input of the weight update module.
[0027] Specifically, the external data module is used to output external real-time data; Latch latch, used to obtain weight data of back-to-back inverters; A logic calculation unit, used to calculate a corresponding calculation result Z according to the external real-time data and the weight data; The calculation inverter D1 is used to obtain a reverse calculation result ZN according to the calculation result Z.
[0028] Specifically, the input data of the latch is read from the Q end of the back-to-back inverter, and the reverse control signal CTRLN is input by the external control module. The basic calculation process is implemented by the logic calculation unit, and the rewriting process of the calculation data is controlled by the calculation inverter.
[0029] The logic calculation unit in this embodiment is in the AND gate logic state and. In response to the logic calculation unit being in the AND gate logic state and, if the output signal of the latch and the output signal of the external data module are both high level, the output result of the logic calculation unit is high level; otherwise, the output result of the logic calculation unit is low level. The OR gate logic state can also be selected according to actual conditions. For example, in response to the logic calculation unit being in the OR gate logic state, if the output signal of the Latch latch or the output signal of the external data module is high, the output result of the logic calculation unit is high; otherwise, the output result of the logic calculation unit is low.
[0030] 4. External control module.
[0031] The external control module is connected to the control terminals of the calculation module and the weight updating module respectively to realize the control of the calculation process and the weight updating process.
[0032] 4.1. In response to the in-memory computing device being in a computing state, the control signal CTRL output by the external control module is controlled to be at a low level, and the reverse control signal CTRLN is at a high level, so that the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12 and the thirteenth transistor M13 are turned off, the current of the weight update module is turned off, the Latch latch is turned on, and the computing operation starts.
[0033] The calculation operation is mainly completed by the calculation module. At this time, the input data of the Latch latch is read from the Q end of the back-to-back inverter, and the reverse control signal CTRLN is input by the external control module. The logic calculation unit can be adjusted to the AND gate logic state, OR gate logic state, or NOT gate logic state according to the needs, obtain external real-time data and connect the output data of the Latch latch, complete the logical calculation of the weight data and the input data inside the computer, and obtain the calculation result Z; then obtain the reverse calculation result ZN through the calculation inverter to realize the basic calculation process.
[0034] 4.2. In response to the in-memory computing device being in a weight update state, the control signal CTRL output by the external control module is controlled to be high, and the reverse control signal CTRLN is low, so that the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, the latch is turned off, and the weight update operation starts, including: When the calculation result Z is a high level, the tenth transistor M10 and the eleventh transistor M11 are turned on, the Q end of the back-to-back inverter is charged to a high level, and the QB end of the back-to-back inverter is discharged to a low level to perform a data storage operation; When the calculation result Z is low level, the seventh transistor M7 and the fourteenth transistor M14 are turned on, the Q end of the back-to-back inverter is discharged to low level, and the QB end of the back-to-back inverter is charged to high level to perform data storage operation.
[0035] In this way, the calculation result Z can be written directly into the storage unit after the calculation is completed, without the need to read the calculation result Z first, and then write the calculation result Z and the reverse calculation result ZN through the BL / BLB position, which greatly reduces the complexity of weight update, thereby reducing the delay and power consumption of weight update.
[0036] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
[0037] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0038] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0039] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0040] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. An in-memory computing device based on weight update, characterized in that: Includes external control module, 6TSRAM module, calculation module and weight update module; The external control module is connected to the control terminals of the calculation module and the weight update module respectively to realize the control of the calculation process and the weight update process; The 6TSRAM module is used to store weight data; The calculation module is used to obtain external real-time data; and calculate corresponding calculation data according to the external real-time data and the weight data; The weight updating module is used to convert the calculated data into weight data and store it in the 6TSRAM module to achieve weight updating.
2. The in-memory computing device based on weight update according to claim 1, characterized in that: The 6TSRAM module includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4; the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 together form a back-to-back inverter to store weight data; The gate of the first transistor M1 is connected to the gate of the second transistor M2 and the QB terminal of the back-to-back inverter; the drain of the first transistor M1 is connected to the drain of the second transistor M2 and the Q terminal of the back-to-back inverter; the source of the first transistor M1 is connected to the power supply voltage; the source of the second transistor M2 is grounded; The gate of the third transistor M3 is connected to the gate of the fourth transistor M4 and the Q end of the back-to-back inverter; The drain of the third transistor M3 is connected to the drain of the fourth transistor M4 and the QB terminal of the back-to-back inverter; The source of the third transistor M3 is connected to the power supply voltage; A source of the fourth transistor M4 is grounded.
3. The in-memory computing device based on weight update according to claim 2, characterized in that: The 6TSRAM module further includes a fifth transistor M5 and a sixth transistor M6; One end of the fifth transistor M5 is connected to the QB end of the back-to-back inverter, and the other end of the fifth transistor M5 is connected to the first bit line BLB; One end of the sixth transistor M6 is connected to the Q end of the back-to-back inverter, and the other end of the sixth transistor M6 is connected to the second bit line BL.
4. The in-memory computing device based on weight update according to claim 2, characterized in that: The weight updating module includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14; The drain of the seventh transistor M7 is connected to the drain of the eighth transistor M8; the drain of the ninth transistor M9 is connected to the drain of the tenth transistor M10; the drain of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12; the drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14; The source of the seventh transistor M7 is connected to the power supply voltage; the QB end of the back-to-back inverter is respectively connected to the source of the eighth transistor M8 and the source of the ninth transistor M9; the source of the eleventh transistor M11 is connected to the power supply voltage; The source of the tenth transistor M10 is grounded; the Q end of the back-to-back inverter is connected to the source of the twelfth transistor M12 and the source of the thirteenth transistor M13 respectively; the source of the fourteenth transistor M14 is grounded; The calculation result Z output by the calculation module is respectively connected to the gate of the seventh transistor M7 and the gate of the tenth transistor M10; the reverse calculation result ZN output by the calculation module is respectively connected to the gate of the eleventh transistor M11 and the gate of the fourteenth transistor M14; The control signal CTRL output by the external control module is connected to the gate of the ninth transistor M9 and the gate of the thirteenth transistor M13 respectively; the reverse control signal CTRLN output by the external control module is connected to the gate of the eighth transistor M8 and the gate of the twelfth transistor M12 respectively.
5. The in-memory computing device based on weight update according to claim 4, characterized in that: The calculation module includes a latch, a logic calculation unit and a calculation inverter D1, and the calculation data includes a calculation result Z and a reverse calculation result ZN; The input end of the Latch latch is connected to the Q end of the back-to-back inverter and the output end of the external control module respectively, and the output end of the Latch latch is connected to the input end of the logic calculation unit; The input end of the logic calculation unit is also connected to the output end of the external data module; the output end of the logic calculation unit is respectively connected to the input end of the weight update module and the calculation inverter D1; The output end of the calculation inverter is connected to the input end of the weight update module; The external data module is used to output external real-time data; The Latch latch is used to obtain weight data of the back-to-back inverters; The logic calculation unit is used to calculate and obtain a corresponding calculation result Z according to the external real-time data and the weight data; The calculation inverter D1 is used to obtain a reverse calculation result ZN according to the calculation result Z.
6. The in-memory computing device based on weight update according to claim 5, characterized in that: The logic calculation unit includes an AND gate logic state and; In response to the logic calculation unit being in the AND gate logic state and, if the output signal of the Latch latch and the output signal of the external data module are both high level, the output result of the logic calculation unit is high level; otherwise, the output result of the logic calculation unit is low level.
7. The in-memory computing device based on weight update according to claim 5, characterized in that: In response to the in-memory computing device being in a computing state, the control signal CTRL output by the external control module is controlled to be at a low level, and the reverse control signal CTRLN is at a high level, so that the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12 and the thirteenth transistor M13 are turned off, and the Latch latch is turned on.
8. The in-memory computing device based on weight update according to claim 5, characterized in that: In response to the in-memory computing device being in a weight update state, the control signal CTRL output by the external control module is controlled to be high, and the reverse control signal CTRLN is low, so that the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, the latch is turned off, and the weight update operation starts, including: When the calculation result Z is a high level, the tenth transistor M10 and the eleventh transistor M11 are turned on, the Q end of the back-to-back inverter is charged to a high level, and the QB end of the back-to-back inverter is discharged to a low level to perform a data storage operation; When the calculation result Z is low level, the seventh transistor M7 and the fourteenth transistor M14 are turned on, the Q end of the back-to-back inverter is discharged to low level, and the QB end of the back-to-back inverter is charged to high level to perform data storage operation.