Analysis method of digital logic circuit, computer equipment and storage medium

Abstract

The invention provides an analysis method of a digital logic circuit, computer equipment and a storage medium. The method comprises the following steps: acquiring a digital logic circuit to be analyzed; performing circuit grading by taking a trigger of the digital logic circuit as a node, and selecting the digital logic circuit between any two adjacent stages as a target circuit; wherein the target circuit comprises at least one path, and the at least one path comprises at least one combinational logic unit; determining a variable sequence of the target circuit, and based on the variable sequence, determining a first result of the at least one combinational logic unit according to a Boolean function; wherein the first result corresponds to Boolean difference of output to input of at least one combinational logic unit; determining a target path in the at least one path, and performing ITE operation according to a first result corresponding to the target path; and determining an identification result of the target path according to the operation result.

Description

Technical Field

[0001] The present application relates to the technical field of digital logic circuits, and in particular to an analysis method, a computer device, and a storage medium for digital logic circuits. Background Art

[0002] As modern digital logic circuits become larger and more complex, how to efficiently analyze and optimize circuits has become an indispensable and important part of modern EDA (Electronic design automation) tools.

[0003] In the process of digital logic circuit design, false paths may account for 80% or even higher of all paths in digital logic circuits. Identifying false paths can reduce the workload of tools to repair illegal paths. However, in digital circuits, the number of logic gates reaches millions or even tens of millions, and identifying false paths within acceptable resource ranges is a challenge. Summary of the invention

[0004] In view of this, the present application proposes a digital logic circuit analysis method, a computer device and a storage medium to solve or partially solve the above problems.

[0005] Based on the above objectives, in a first aspect, the present application provides a method for analyzing a digital logic circuit, comprising: Obtain a digital logic circuit to be analyzed; The circuit is graded by taking the trigger of the digital logic circuit as a node, and the digital logic circuit between any two adjacent levels is selected as the target circuit; wherein the target circuit includes at least one path, and the at least one path includes at least one combinational logic unit; Determine a variable sequence of the target circuit, and determine a first result of the at least one combinatorial logic unit based on the variable sequence according to a Boolean function; wherein the first result corresponds to a Boolean difference of an output of the at least one combinatorial logic unit with respect to an input; Determine a target path among the at least one path, and perform an ITE operation according to a first result corresponding to the target path; The recognition result of the target path is determined according to the operation result.

[0006] In a second aspect of the present application, a computer device is provided, comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the program includes instructions for executing the method described in the first aspect.

[0007] According to a third aspect of the present application, a non-volatile computer-readable storage medium containing a computer program is provided. When the computer program is executed by one or more processors, the processors execute the method described in the first aspect.

[0008] From the above, it can be seen that the present application provides a method for analyzing a digital logic circuit, a computer device, and a storage medium. The present application determines the variable order of the target circuit, and then uses a Boolean function to represent the ROBDD, thereby determining the first result of the combinational logic unit in the target circuit, and finally performs an ITE operation according to the first result. If the operation result is always 0, it means that the target circuit belongs to a false path. In this way, when analyzing the target circuit, the number of nodes can be reduced by reducing the ordered binary decision graph, and the above method can reduce the space complexity and calculation time to a certain extent, improve the analysis efficiency, and speed up the false path identification process. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 A schematic diagram of the hardware structure of an exemplary computer device provided in an embodiment of the present disclosure is shown.

[0011] Figure 2 A basic structural diagram of an EDA tool according to an embodiment of the present disclosure is shown.

[0012] Figure 3 A schematic diagram showing a basic execution flow of a calculation command of an EDA tool according to an embodiment of the present disclosure is shown.

[0013] Figure 4 A flow chart of an exemplary method provided according to an embodiment of the present application is shown.

[0014] Figure 5 A schematic diagram of the structure of an exemplary target circuit provided according to an embodiment of the present application is shown.

[0015] Fig. 6A A schematic diagram of an exemplary BDD provided according to an embodiment of the present application is shown.

[0016] Figure 6B A schematic diagram of an exemplary ROBDD provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of this specification more clear, this specification is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0018] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements, objects or method steps appearing before the word cover the elements, objects or method steps listed after the word and their equivalents, without excluding other elements, objects or method steps. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0019] Figure 1 The schematic diagram of the structure of a computer device 100 provided in an embodiment of the present application is shown. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other in communication within the device through the bus 110.

[0020] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0021] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). Figure 1As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present application) and data to be processed. The processor 102 may also access the stored program instructions and data, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0022] The network interface 106 can be configured to provide the computer device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0023] The peripheral interface 108 may be configured to connect the computer device 100 to one or more peripheral devices to implement information input and output. For example, the peripheral devices may include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0024] The bus 110 may be configured to transmit information between various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0025] It should be noted that, although the above device only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include Figure 1 All components shown in .

[0026] Figure 2 A basic structural diagram of an EDA tool 200 according to an embodiment of the present application is shown.

[0027] like Figure 2As shown, the part above the dotted line is the user part; the part below the dotted line is the EDA tool 200, which can be Figure 1 The device 100 shown is implemented. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software for performing placement and routing based on chip design. The simulation tool 200 may include a Tcl command (or a graphic / window interface) module 204, various calculation modules (e.g., a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.) and a database system 212. The user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command (or graphic / window interface) module 204.

[0028] The Tcl command module 204 mainly performs the functions of message transmission or command transmission. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and transmit the instructions to the corresponding computing modules to perform specific tasks according to the specific contents of the instructions.

[0029] According to different computing tasks, each computing module can be divided into, for example, a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc. The Place computing module 206 can be used to calculate a reasonable placement position for all components, the Route computing module 208 can be used to calculate a reasonable wire connection method between each component, and the Optimization computing module 210 can be used to optimize the placement position and wire connection method between each component. The computing process of these computing modules can be, for example, Figure 1 is performed in the processor 102.

[0030] The database system 212 can be used to completely and comprehensively record and store all information of the chip being simulated or designed (such as location, direction, size, structure, wire connection method, etc.). This information, for example, can be stored in Figure 1 in the memory 104.

[0031] Figure 3 FIG. 3 shows a basic execution flow 300 of a calculation command of an EDA tool 200 according to an embodiment of the present application. Figure 3As shown, in step 302, the user 202 can issue a command (e.g., do_place command) to the EDA tool 200 through the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses this command and distributes it to the corresponding calculation module (e.g., Place calculation module 206). In step 306, each calculation module performs the specific calculation required by each. During this period, as shown in step 308, each calculation module needs to (high frequency, repeatedly) retrieve data from the database system 212 for calculation. After the calculation is completed, as shown in step 310, each calculation module can write the calculation result into the database system 212 and return the calculation result to the Tcl command module 204. In step 312, the Tcl command module 204 returns the calculation result to the user 202 through the command interface or graphical user interface (GUI), and the EDA tool 200 ends the processing process of a calculation command. In step 314, the user can evaluate according to the calculation result and then determine the next plan.

[0032] As mentioned in the background technology section, an important task of current EDA tools is to analyze and optimize digital logic circuits. For the initially designed digital logic circuits, there will be a large number of false paths, and EDA needs to first identify and mark these false paths, and then perform other operations such as pruning.

[0033] To facilitate understanding, some concepts involved in the embodiments of the present application are described below.

[0034] First of all, the digital logic circuit in this application refers to a circuit composed of a sequential logic unit and a combinational logic unit, which can be collectively referred to as a combo. The basic unit that constitutes the sequential logic unit is a flip-flop (FF), and the combinational logic unit (gate) is a circuit composed of logic gates (such as AND gates, OR gates, NOT gates, etc.), whose output is a function of the input signal and does not involve memory or storage functions.

[0035] After that, path: a sequence of nodes, in which there is a directed edge between any two adjacent nodes, so that the two nodes are the tail node and the head node of the edge respectively. Specifically, 1) the first node in the sequence is the starting node of the path; 2) the last node in the sequence is the ending node of the path. In the scenario applied to the present application, the path is a sequence from a starting node (start point) to an ending node (end point), which only passes through combo in the middle. Among them, the starting node (start point) can be specifically the output pin (Q pin or input data ports) of the trigger (launch FF) for launch in the data path, which is directly connected to the input pin (input pin) of a combo; the ending node (end point) can be specifically the input pin (D pin or output ports) of the trigger (capture FF) for capture in the data path, which is directly connected to the output pin (output pin) of a combo. From this, it can be seen that for the starting node (start point) to the ending node (end point) of the path (path), there is only a combinational logic unit (gate) in the combo.

[0036] After the concept of path is determined, the false path can be generally divided into three types: 1) False path that does not care about timing, which means that due to asynchronous clock, the timing of this path is not concerned. 2) False path that cannot be logically sensitized, which means that the path cannot be logically sensitized. 3) Delay-dependent False path, which can be logically sensitized, but the signal of this path is controlled by the signal of other pins outside the path.

[0037] In the initial digital logic circuit, false paths may account for 80% or more of all paths. Identifying false paths can reduce the workload of tools to repair illegal paths. However, in digital logic circuits, the number of logic gates reaches millions or even tens of millions, and identifying false paths within an acceptable resource range is a challenge.

[0038] In view of this, the present application proposes a method for analyzing digital logic circuits. The present application determines the variable order of the target circuit, and then uses a Boolean function to represent the ROBDD, thereby determining the first result of the combinational logic unit in the target circuit, and finally performs an ITE operation according to the first result. If the operation result is always 0, it means that the target circuit belongs to a false path. In this way, when analyzing the target circuit, the number of nodes can be reduced by reducing the ordered binary decision graph, and the above method can reduce the space complexity and calculation time to a certain extent, improve the analysis efficiency, and speed up the false path identification process.

[0039] In a specific application scenario, the solution proposed in this application has a more prominent recognition effect on the second type of false path in the aforementioned false path.

[0040] Figure 4 FIG. 4 is a flow chart of an exemplary method 400 provided in an embodiment of the present application. The method 400 may be Figure 1 The computer device 100 is implemented and can be implemented as Figure 2 A portion of the functionality of the EDA tool 200. Figure 4 As shown, the method 400 may further include the following steps.

[0041] Step 402: Obtain a digital logic circuit to be analyzed.

[0042] In this step, the digital logic circuit to be analyzed and optimized can be generated based on the chip design. For example, it is converted into a netlist file through logic synthesis, and then the digital logic circuit to be analyzed and optimized is obtained after layout and routing. In combination with the above, the digital logic circuit to be analyzed in the present application can be an initial digital logic circuit.

[0043] It can be understood that, in combination with the foregoing, the analysis and optimization in the embodiments of the present application can be analysis or optimization, or analysis and optimization. The specific operations can be set according to user needs and are not limited here.

[0044] Step 404, performing circuit grading with the triggers of the digital logic circuit as nodes, and selecting a digital logic circuit between any two adjacent levels as a target circuit; wherein the target circuit includes at least one path, and the at least one path includes at least one combinational logic unit.

[0045] In this step, as mentioned above, the digital logic circuit of the present application is composed of sequential logic units and combinational logic units, wherein the basic unit of the digital logic circuit is a flip-flop (FF), and a digital logic circuit can be graded with flip-flops (FF) as nodes.

[0046] Specifically, for a digital logic circuit to be analyzed, firstly, the FF in the circuit is used for grading. The total input port (input data ports) can be set to level 0. Then, from the input data ports, through the combo (as mentioned above, the combo here only has the combinatorial logic unit gate), it reaches the input pin (D pin) of the next trigger (FF). Then the trigger (FF) is the first level. From the output pin or clock pin (CK pin) of the first-level trigger (FF), through the combo, it reaches the input pin (D pin) of the new trigger (FF). Then the trigger (FF) is the second level. And so on, until the output pin or clock pin (CK pin) of the n-th level trigger (FF) reaches the total output port (outputports).

[0047] After that, after the grading is completed, the circuit between any two adjacent levels can be selected as the target circuit. For example, the clock pin (CK pin) of the i-th level trigger (FF) is comboed to the input pin (Dpin) of the i+1 level trigger (FF), and this is used as the target circuit. Among them, the i-th level trigger (FF) is the launch FF, and the i+1 level trigger (FF) is the capture FF. Through the aforementioned grading method, it can be seen that for two adjacent levels, there may be multiple launch FFs and multiple capture FFs. Specifically, if Figure 5 As shown, it is a specific structural diagram of a target circuit, where , and It can be considered that they represent three different launch FFs at level i, and represents the capture FF of the i+1th level. It can be seen that in this target circuit, , or arrive There can be many paths, and the units identified from a to g are all combinational logic units.

[0048] Step 406, determine the variable order of the target circuit, and determine the first result of the at least one combinational logic unit based on the variable order according to a Boolean function; wherein the first result corresponds to the Boolean difference of the output of the at least one combinational logic unit with respect to the input.

[0049] In this step, variable order usually refers to the process of arranging a set of variables in a certain order. This process can be applied to many scenarios, such as in topological sorting, arranging the vertices (variables) in a directed acyclic graph (DAG) in a topological order, ensuring that for any directed edge u→v, vertex u appears before vertex v in the sorting result.

[0050] What needs to be explained here is that as a form of expression of directed acyclic graph (DAG), the binary decision diagram (BDD) is essentially a rooted directed acyclic graph with one or two terminal nodes with out-degree 0, labeled 0 or 1, and including a set of variable nodes u with out-degree 2. The two outgoing edges of the variable node are defined by low(u) and high(u). Furthermore, if the variables follow a given linear order on all paths in the directed acyclic graph (DAG), the BDD is ordered (Ordered Binary Decision Diagram, OBDD). And further, it is a reduced ordered binary decision diagram (Reduced Ordered Binary Decision Diagram, ROBDD), which is obtained by reducing the BDD. If a BDD is reduced, no two different variable nodes u and v have the same variable names low and high child nodes, and no variable node u has the same low- and high-child nodes. For example Fig. 6A and 6B As shown, Fig. 6A As shown, it is a binary decision diagram (BDD) expression for a target circuit; Figure 6B As shown in Figure 2, it is a reduced ordered binary decision diagram (ROBDD) expression for the same target circuit, where low(u) and high(u) are in Fig. 6A and Figure 6B The dotted and solid lines in the figure indicate the node associated variable var(u); the circular nodes marked with variable names are internal nodes, i.e., non-leaf nodes. Fig. 6A and 6B The three internal nodes a, b, and c are shown in the figure; the square nodes at the bottom are leaf nodes. Fig. 6A and 6B Marked as 1 or 0.

[0051] In some embodiments, the digital logic circuit can be abstracted into a Boolean logic network, and the Boolean function can be used for conversion between the two. At the same time, since the output of the combinatorial logic unit (gate) can be expressed as a Boolean function expression of the input. Combined with the above, it can be seen that by combining the variable order with the Boolean function, for any combinatorial logic unit in the target circuit, the ROBDD can be uniquely represented by the given variable order. After that, with the help of the Boolean expression determined by the Boolean function, the Boolean difference of the input to the output of a combinatorial logic unit can be determined.

[0052] Specifically, a combinational logic unit The input pin is denoted as , The value is 1, 2, 3...j. j is the combinational logic unit The number of input pins, such as Figure 5 As shown, the combinational logic units a, b, etc. have 2 input pins, and the combinational logic unit f has 1 input pin. Combinational logic unit The only output pin. The Boolean expression can be written as: .and then right The Boolean difference of can be written as:

[0053] in, represents the negation factor of the Shannon expansion, represents the positive factor of the Shannon expansion.

[0054] In some embodiments, for the first result, since it corresponds to the Boolean difference of the output of the combinatorial logic unit to the input, it can be directly the calculation result of the Boolean difference. That is, the first result is the Boolean difference result of the ROBDD of the at least one combinatorial logic unit determined according to the Boolean function. In other scenarios, for larger circuits, the calculation of its Boolean function or Boolean difference is very large, and direct calculation will take up more computing space, so the first result here can only correspond to the logical expression of the Boolean difference, that is, only record the calculation method, and do not perform specific calculations, so that the first result can be obtained quickly, saving computing resources at this time. That is, the logical expression corresponding to the Boolean difference of the ROBDD of the at least one combinatorial logic unit determined according to the Boolean function.

[0055] In some more specific scenarios, since the process of finding Boolean differences is independent of each other, it can be processed by multi-threading. Assuming there are n nodes, n-1 threads can be established to obtain n-1 Boolean difference logical expressions in parallel with multi-threading (one Boolean difference calculation is required for each two adjacent nodes, so n-1 Boolean differences need to be calculated for n nodes), and save them in the form of suffix expressions in a map. The key of the map can be<celltype,inputpin> , value is the suffix expression form of the logical expression for the Boolean difference of the output pin of the cell type (AND, OR, NOT, NOR, etc.) to the input pin.

[0056] In some embodiments, the variable order can be determined by determining the level of each starting point in the target circuit. In combination with the above, there may be multiple starting points and multiple end points in a target circuit, such as Figure 5 As shown, , and It can be considered that they represent three different launch FFs of the i-th level, that is, three starting points, and It represents the capture FF of the i+1th level, that is, 1 end point. Then, starting from the end point, search forward along different paths, and add 1 for each combinatorial logic unit level passed. Then, due to the difference in paths, each starting point may correspond to multiple levels, and then the search can be performed using the depth-first search (DFS) method. It can be understood that each starting point selects the largest one in its corresponding level. Of course, according to the principle of depth-first search, the level of the combinatorial logic unit therein will also be set to the largest one. In this way, the level of each starting point is determined, and then the starting points can be sorted according to the level, such as descending order, ascending order or other specifically defined sorting methods. That is, in some embodiments, determining the variable order of the target circuit includes: determining at least one starting point and at least one end point of the target circuit; starting from the at least one end point, determining the level of the at least one starting point by depth-first search; wherein the level of any starting point corresponds to the number of combinatorial logic units passed from any starting point to any end point; sorting the at least one starting point according to the level of the at least one starting point, thereby determining the variable order.

[0057] Furthermore, the representation of BDD is highly correlated with the variable order. A bad variable order may result in the number of nodes in the BDD being , which is unacceptable. In order to reduce the number of nodes and reduce time and space complexity. The sorting method of the starting points can be to sort them in descending order according to their levels. That is, in some embodiments, sorting the at least one starting point according to its level includes: sorting the at least one starting point in descending order according to its corresponding level.

[0058] In a more specific embodiment, assume that there are m launch FFs in the target circuit, and its Q pin is the startpoint, with a total of m variables, and the m variables are independent of each other. Assume that there are q capture FFs in the target circuit, and the drivers corresponding to its D pin are q endpoints. Since the representation of BDD is highly related to the variable order, a bad variable order may result in the number of nodes in its BDD being , which is unacceptable. Therefore, for a target circuit, the variable order can be determined as follows: select a path in the target circuit, denoted as path1, According to the above definition, is an endpoint, consisting of Start forward depth-first search (DFS) to determine the level of each node, that is, the combinatorial logic unit. The level of the endpoint is 0, and the level of the i-th node is the maximum value of the determined levels. Finally, sort the levels of the start points in descending order, and the order of the start points obtained is the variable order used uniformly when representing the ROBDD related to the target circuit. Such a variable order can effectively reduce the number of nodes in the BDD.

[0059] Step 408: determine a target path in the at least one path, and perform an ITE operation according to the first result corresponding to the target path.

[0060] In this step, after the first result is determined, one of the multiple paths of the target circuit can be selected as the target path. The target path generally does not include all the combinational logic units in the target circuit. It is necessary to first determine the corresponding combinational logic unit and its first result. After that, the ITE operation can be used to perform operation calculations based on the first result. According to the calculation results, it can be determined whether the target path is a false path. The ITE operation here is a ternary Boolean operator that implements if f, then g, else h. f, g, and h are three Boolean functions with the same variable order. That is, .

[0061] It should be noted that, assuming a path is represented by ,in Represents a node in a path, such as the previous combinational logic unit The only output pin. Combinational Logic Unit The only output pin of go through ,arrive . is a starting point. is an endpoint. Then, the judgment condition for whether a path is a false path, especially the second type of false path mentioned above, can be: if the value of the following formula is always 0, then the path is the second type of false path.

[0062]

[0063] in, According to the above, it can be known that it is a combinational logic unit The Boolean difference of the output pin of the path to the input pin on the path. Therefore, to determine whether a path is a second type of false path, that is, whether the Boolean expression in the preceding step is always 0, it can be converted into a determination of whether the ROBDD has only leaf nodes with a value of 0.

[0064] In some embodiments, since the first result can only store logical expressions, then, for a target path, the target combinational logic unit corresponding to the target path can be determined first, and then the logical expressions corresponding to these target combinational logic units can be used as necessary logical expressions, and then the Boolean difference calculation of ROBDD is performed according to the specific logical expression, and then combined with the ITE operation, finally the calculation result is obtained. That is, in some embodiments, the ITE operation is performed according to the first result corresponding to the target path, including: in response to the first result being the logical expression, determining the target combinational logic unit corresponding to the target path, determining the necessary logical expression according to the target combinational logic unit, performing the Boolean difference calculation of ROBDD according to the necessary logical expression, and performing the ITE operation according to the calculation result.

[0065] Furthermore, in the process of determining the logical expression, the logical expressions can be simplified as much as possible, and the first result can be stored in this way. In this way, in the simplification process, the logical expression may eventually only have a constant or a node pointing to the path. The logical expression pointing to the node may point to the starting end of the target path or other combinational logic units. Since a constant or a ROBDD pointing to the starting end of the target path is relatively simple, or the corresponding result can be directly determined, it can be removed when determining the necessary logical expression, and the remaining one is used as the necessary logical expression. Specifically, for a combo with n inputs and 1 output, the logical expression of the Boolean difference of a certain input may not be related to all other input pins. For example, a combo with 4 inputs and 1 output, the logical expression of the Boolean difference of the output input 1 must not contain input 1, and may contain 3 other inputs, or only 2 or even 1 other input. Therefore, after the determination of the logic expression of each combo is completed, it is known which combo pins are needed and which are irrelevant. For irrelevant combo pins, there is no need to generate their ROBDD, which can further save time. That is, in some embodiments, when the first result is the logic expression, the logic expression is simplified to store the first result; the necessary logic expression is determined according to the target combinatorial logic unit, including: determining all simplified logic expressions corresponding to the target combinatorial logic unit, removing the logic expressions whose simplified results are constants or point to the starting end of the target path, and using the remaining as the necessary logic expressions.

[0066] Finally, for the target path containing n nodes, perform an AND operation (using the IRE operator) on the ROBDDs represented by n-1 Boolean differences to obtain the final ROBDD. If its leaf node is only node 0, it means it is the second type of false path.

[0067] Further, according to the above method, it can be seen that due to It is a multiplication process. If there is a value of 0 in the calculation process, then It must be 0, and then in the evaluation process, if the ROBDD of the product of several Boolean differences is always 0, it can be pruned and the final result returned in advance is always 0. And this evaluation process may appear in the process of formula simplification, and it can also appear in the specific calculation process. That is, in some embodiments, the Boolean difference calculation of ROBDD according to the necessary logical expression includes: in response to the result of the simplification of the logical expression corresponding to any target combinational logic unit being 0, the calculation of other logical expressions is stopped; or the Boolean difference calculation of ROBDD is performed in sequence on the necessary logical expressions according to the variable sequence, and in response to the calculation result of any necessary logical expression being 0, the calculation of other necessary logical expressions is stopped.

[0068] Furthermore, since the calculation of each ROBDD may be relatively large, multithreading can be used for parallel processing to speed up processing time and improve efficiency. For example, for the product of n-1 ROBDDs, it can be divided into [n-1 / 2] threads. The calculation is put into 1 thread, The calculation of is put into the second thread, and so on. Although the total number of operations is at the O(n) level, it can be accelerated by using multithreading. That is, in some embodiments, performing Boolean difference calculation of ROBDD according to the necessary logical expressions includes: determining the number of the necessary logical expressions, and allocating at least one processing thread according to the number.

[0069] In some embodiments, during the calculation of ROBDD, ROBDD can be understood as a graph, such as Figure 6B As shown in the figure, there are two types of nodes, namely leaf nodes and non-leaf nodes. Since there are only two values ​​for leaf nodes, 0 and 1 are used as examples. Afterwards, for each node, it generally corresponds to two ROBDDs, that is, two logical expressions. and (No ) is used to represent it. Figure 6B In the scenario shown, and The non-leaf nodes of the ROBDD are exactly the same, but The edges pointing to leaf node 0 are Will point to leaf node 1. The edges pointing to leaf node 1 are Will point to 0. Generally, in other scenarios, and However, in combination with the specific scenario of this application, since the leaf node has only two values, such as 0 and 1, if but In this way, the calculation process of ROBDD can be further simplified. For two ROBDDs with exactly the same non-leaf nodes: and , record only one of the values, and then and All of them point to this value, and for the value of another ROBDD, the recorded value is directly not operated, that is, after determining which value is recorded, another value is directly output. In a more specific scenario, for the convenience of explanation, the variable sequence obtained by a ROBDD is represented by The non-start point combo pins on the path can be expressed as is the logical expression of the variable. Each logical expression can be represented by a ROBDD. ROBDD is unique when the variable order is fixed. To save time and space, for each pin, when creating ROBDD, add a bool variable is_not. If it is known The ROBDD is expressed as , then , bool is_not is false; , bool is_not is true. and The difference is that if you want , just follow When the ROBDD reaches the leaf node, if it is 0, it is taken as 1, and if it is 1, it is taken as 0. Therefore, it does not occupy memory and stores and Instead of using two ROBDDs, the bool is_not variable is reused and the value is obtained according to the above rules. That is, in some embodiments, performing the ITE operation according to the first result corresponding to the target path includes: creating a ROBDD for the combinatorial logic unit that needs to be calculated on the target path; wherein the ROBDD of each combinatorial logic unit corresponds to only two results; determining at least one pair of target ROBDDs with completely identical non-leaf nodes in the created ROBDD; performing result calculation on one of the at least one pair of target ROBDDs to obtain a first result; and directing the result of the other one of the at least one pair of target ROBDDs to the first result through a non-operation.

[0070] Step 410: Determine the recognition result of the target path according to the operation result.

[0071] In this step, after the final result is obtained according to the aforementioned ITE operation, if the result is always 0, it means that the target path is a false path, specifically the aforementioned second false path, so as to determine the recognition result of the facial path. Then, in the subsequent process, corresponding operations can be performed according to the recognition result, and operations such as removal can be used to optimize the digital logic circuit after analysis.

[0072] In a more specific scenario, Figure 5 The target circuit shown illustrates the process of analyzing false paths using ROBDD.

[0073] like Figure 5 As shown, considering the path ,by Start, move forward , , The level of is 4, then the variable order is For the convenience of explanation, note: and: ;or: ;No: ; and not: .but:

[0074] Therefore, it can be seen that only and Perform ROBDD representation. Expressed as Pointer to the ROBDD and boolis_not = true.

[0075]

[0076] The combo pins on all paths are shown below for the sake of clarity. First, the following conventions are made:

[0077]

[0078]

[0079]

[0080] but , and The ROBDD representations are:

[0081]

[0082]

[0083] Then ROBDD is expressed as:

[0084] Finally, the ROBDD contains only leaf nodes of 0, so the path is a false path.

[0085] As can be seen from the above, the embodiment of the present application provides a method for analyzing a digital logic circuit. The present application determines the variable order of the target circuit, and then represents the ROBDD through a Boolean function to determine the first result of the combinational logic unit in the target circuit, and finally performs an ITE operation according to the first result. If the operation result is always 0, it means that the target circuit belongs to a false path. In this way, when analyzing the target circuit, the number of nodes can be reduced by reducing the ordered binary decision graph, and the above method can reduce the space complexity and calculation time to a certain extent, improve the analysis efficiency, and speed up the false path identification process.

[0086] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of the embodiment of the present application can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0087] It should be noted that the above describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in all the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0088] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-volatile computer-readable storage medium containing a computer program, wherein the non-volatile computer-readable storage medium containing a computer program stores computer instructions, and the computer instructions are used to enable the computer to execute method 400 described in any of the above embodiments.

[0089] The computer-readable storage medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0090] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method 400 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0091] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a computer program product, which includes a computer program. In some embodiments, the computer program is executable by one or more processors so that the processors execute the described method 400. Corresponding to the execution subject corresponding to each step in each embodiment of the method 400, the processor that executes the corresponding step may belong to the corresponding execution subject.

[0092] The computer program product of the above embodiment is used to enable the processor to execute the method 400 described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0093] Finally, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to the integrated circuit (IC) chip and other components may or may not be shown in all the figures provided. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0094] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0095] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A method for analyzing a digital logic circuit, characterized in that: include: Obtain a digital logic circuit to be analyzed; The circuit is graded by taking the trigger of the digital logic circuit as a node, and the digital logic circuit between any two adjacent levels is selected as the target circuit; wherein the target circuit includes at least one path, and the at least one path includes at least one combinational logic unit; Determine a variable sequence of the target circuit, and determine a first result of the at least one combinatorial logic unit based on the variable sequence according to a Boolean function; wherein the first result corresponds to a Boolean difference of an output of the at least one combinatorial logic unit with respect to an input; Determine a target path among the at least one path, and perform an ITE operation according to a first result corresponding to the target path; The recognition result of the target path is determined according to the operation result.

2. The method according to claim 1, characterized in that The determining of the variable sequence of the target circuit comprises: Determining at least one starting point and at least one end point of the target circuit; Starting from the at least one end point, the level of the at least one starting point is determined by a depth-first search method; wherein the level of any starting point corresponds to the number of combinational logic units passed from any starting point to any end point; The variable order is determined by sorting the at least one starting point according to the level of the at least one starting point.

3. The method according to claim 2, characterized in that The step of sorting the at least one starting point according to the level of the at least one starting point comprises: The at least one starting point is arranged in descending order according to the corresponding level.

4. The method according to claim 1, characterized in that: The first result is a Boolean difference result of the ROBDD of the at least one combinatorial logic unit determined according to the Boolean function, or a logical expression corresponding to the Boolean difference of the ROBDD of the at least one combinatorial logic unit determined according to the Boolean function.

5. The method according to claim 4, characterized in that The performing an ITE operation according to the first result corresponding to the target path includes: In response to the first result being the logical expression, the target combinational logic unit corresponding to the target path is determined, the necessary logical expression is determined according to the target combinational logic unit, the Boolean difference calculation of the ROBDD is performed according to the necessary logical expression, and the ITE operation is performed according to the calculation result.

6. The method according to claim 5, characterized in that When the first result is the logical expression, simplifying the logical expression to store the first result; The determining of necessary logic expressions according to the target combinational logic unit comprises: All simplified logical expressions corresponding to the target combinational logic unit are determined, logical expressions whose simplified results are constants or point to the starting end of the target path are removed, and the remaining ones are used as the necessary logical expressions.

7. The method according to claim 6, characterized in that The Boolean difference calculation of ROBDD according to the necessary logical expression includes: In response to the result of simplifying the logic expression corresponding to any target combinational logic unit being 0, the calculation of other logic expressions is stopped; Alternatively, the Boolean difference calculation of ROBDD is performed in sequence on the necessary logic expressions according to the variable sequence, and in response to the calculation result of any necessary logic expression being 0, the calculation of other necessary logic expressions is stopped.

8. The method according to claim 5, characterized in that The Boolean difference calculation of ROBDD according to the necessary logical expression includes: The number of necessary logical expressions is determined, and at least one processing thread is allocated according to the number.

9. The method according to claim 1, characterized in that: The performing an ITE operation according to the first result corresponding to the target path includes: Creating a ROBDD for the combinatorial logic unit that needs to be calculated on the target path; wherein the ROBDD of each combinatorial logic unit corresponds to only two results; Determine at least one pair of target ROBDDs having identical non-leaf nodes in the created ROBDD; Performing result calculation on one of the at least one pair of target ROBDDs to obtain a first result; The result of the other one of the at least one pair of target ROBDDs is directed to the first result through a negation operation.

10. A computer device, characterized in that: The method comprises one or more processors, a memory, and one or more programs; wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 9.

11. A non-volatile computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 9.

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