FPGA-based small-step real-time converter simulation acceleration method, device and system
By implementing the small step real-time converter simulation acceleration method on FPGA, using parallel matrix vector multiplication and historical variable multiplication calculation, the problem of high simulation delay of 100 nanoseconds is solved, and efficient and stable power system simulation is achieved. Expand the simulation scale.
Patent Information
- Application Number
- CN202411320393.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2025-01-07
AI Technical Summary
The prior art is difficult to achieve the simulation timeliness of small step converters in the order of 100 nanoseconds, with high computational delays, and FPGAs consume a lot of resources in high-frequency converter model simulation, limiting the simulation scale and parallel acceleration.
Using the FPGA-based small step real-time converter simulation acceleration method, data packet header recognition and verification are performed through cache and clock domain conversion circuit parameters, bit quantization splicing and parallel synchronization are performed, and parallel matrix vector multiplication and historical variable multiplication are used. Calculate and realize the solution simulation of small step converter system.
It realizes rapid simulation of small step power system, reduces calculation delay, improves simulation timeliness, ensures the stability of data communication, and increases the simulation scale by increasing the number of FPGA acceleration cards.
Smart Images
Figure CN119272687A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a small-step real-time converter simulation acceleration method, device and system based on FPGA, belonging to the technical field of power system simulation. Background Art
[0002] Due to the large-scale application of intelligent power systems and new energy equipment, the stable operation of power systems is crucial. In today's intelligent power systems, a large number of converters are used to achieve DC-DC, DC-AC, AC-AC, and AC-DC conversion. In order to ensure the stable operation of a large number of converters in the power grid system, real-time simulation of the switching effect transient characteristics of converters has been widely used.
[0003] In recent years, due to the rapid development of semiconductor technology and power devices, the switching devices in the converter, such as the high-voltage insulated-gate bipolar transistor (IGBT), tend to be high-frequency and can easily reach tens of kilohertz. In order to accurately analyze the switching transient behavior of the converter, the real-time simulation solver needs to perform small-step simulation at a speed much higher than the frequency of the switching device itself, generally requiring 20 to 100 times. However, small-step simulation will bring extremely high computational complexity and consume a lot of time to solve the model. This requires the real-time simulation system to have ultra-high computing power to achieve simulation with small steps of hundreds of nanoseconds to ensure the reliability of the simulation results of high-frequency switching devices.
[0004] At present, the simplest method for converter modeling is the node voltage method, but the equations modeled by this method have problems such as time-varying admittance matrix, strong nonlinearity, complex logic judgment based on component type, and data oscillation, which make it impossible for traditional CPU-based simulation systems to achieve real-time simulation at the level of hundreds of nanoseconds. In recent years, due to its advantages such as programmability, strong parallel computing capabilities, ultra-low latency, hardware acceleration, and power consumption, field programmable gate arrays (FPGAs) have deployed high-frequency converter models in FPGAs for simulation calculations. However, the strong data dependency and cumulative effect of historical variables in high-frequency converter models greatly increase the consumption of hardware resources, and also limit the parallel acceleration of FPGAs, which restricts the scale of FPGA in converter real-time simulation and the acceleration of small-step real-time simulation. Therefore, it is very necessary to study FPGA optimization methods that reduce resource consumption and improve parallelism.
[0005] Therefore, how to optimize and deploy the real-time simulation of mainstream algorithms in parallel on FPGA is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention
[0006] Purpose: In order to overcome the technical problems in the prior art of poor real-time performance and high calculation delay in simulation of converters with small step sizes of hundreds of nanoseconds, the present invention provides an FPGA-based small step size real-time converter simulation acceleration method, device and system.
[0007] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:
[0008] In the first aspect, a small step size real-time converter simulation acceleration method based on FPGA specifically includes:
[0009] The received circuit parameters of the converter are cached, and the cached circuit parameters of the converter are converted in the clock domain to obtain the converted circuit parameters of the converter.
[0010] The converted circuit parameters of the converter are identified and verified by the data packet header.
[0011] The circuit parameters after identification and verification are bit-quantized and spliced into variables to be simulated, and then the variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization.
[0012] The small-step converter system is solved and simulated according to the variables to be simulated after parallel synchronization to obtain the voltage vector result.
[0013] The voltage vector result is judged as abnormal, and different judgment results are sent according to the judgment situation.
[0014] Furthermore, the method further includes: performing clock domain conversion on different judgment results and then sending them.
[0015] Further, the small-step converter system solution simulation is performed according to the variables to be simulated after parallel synchronization to obtain the voltage vector result, which specifically includes:
[0016] Cache parallel synchronization of variables to be simulated.
[0017] According to the branch type, circuit switch state and one of the parallel synchronous variables to be simulated, the historical variable result is calculated to obtain the historical variable result, and in the next clock cycle, according to the calculation complexity of the branch type, the historical variable result is sent within a clock cycle.
[0018] In the bth clock cycle, N historical variable results are cached.
[0019] According to the N historical variable results and the branch node relationship, N current vectors are iteratively calculated within N clock cycles.
[0020] The voltage vector result is obtained by multiplying and superimposing the N current vectors input in parallel with the admittance matrix.
[0021] Furthermore, the voltage vector result is obtained by multiplying and superimposing the N current vectors input in parallel with the admittance matrix, specifically including:
[0022] Get the admittance matrix.
[0023] Convert the N current vectors into a current vector matrix.
[0024] The admittance matrix is multiplied by the current vector matrix and superimposed to obtain the voltage vector result.
[0025] Further, the circuit parameters after identification and verification are bit-quantized and spliced into variables to be simulated, and then the variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization, specifically including:
[0026] The circuit parameters after identification and verification are bit quantized to obtain quantized byte data.
[0027] The newly entered quantized byte data is first entered into the low byte position of the shift register, and the remaining quantized byte data is shifted one byte position to the high byte position in turn. After the splicing is completed, the variable to be simulated is obtained.
[0028] The variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization.
[0029] Furthermore, the circuit parameters after identification and verification are bit-quantized and spliced into variables to be simulated, and then the variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization, and further includes:
[0030] The variables to be simulated after parallel synchronization are sent in the same clock cycle.
[0031] In a second aspect, an FPGA acceleration card includes:
[0032] The asynchronous FIFO module is used to cache the received circuit parameters of the converter and perform clock domain conversion on the cached circuit parameters of the converter to obtain the converted circuit parameters of the converter.
[0033] The data packet identification and verification module is used to identify and verify the data packet header of the converted circuit parameters of the converter.
[0034] The parallel synchronization module is used to perform bit quantization on the circuit parameters after identification and verification to splice them into variables to be simulated, and then perform parallel synchronization on the variables to be simulated to obtain the variables to be simulated after parallel synchronization.
[0035] The solution module is used to perform small-step converter system solution simulation according to the variables to be simulated after parallel synchronization to obtain a voltage vector result.
[0036] The result preparation module is used to judge the abnormal result of the voltage vector result and send different judgment results according to the judgment situation.
[0037] Furthermore, the result preparation module further includes: performing clock domain conversion on different judgment results and then sending them.
[0038] Furthermore, the solution module includes:
[0039] The variable cache module is used to cache the variables to be simulated for parallel synchronization.
[0040] N historical variable multiplication and addition modules, the historical variable multiplication and addition modules are used to calculate according to the branch type, circuit switch state and one of the parallel variables to be simulated in parallel synchronization to obtain the historical variable results, and in the next clock cycle, according to the calculation complexity of the branch type, send the historical variable results within a clock cycles.
[0041] The historical variable cache module is used to cache N historical variable results in the bth clock cycle.
[0042] The current vector iterative calculation module is used to iteratively calculate and obtain N current vectors within N clock cycles according to N historical variable results and branch node relationships.
[0043] The parallel matrix-vector multiplication module is used to obtain a voltage vector result by multiplying and superimposing N current vectors input in parallel with the admittance matrix.
[0044] Furthermore, the parallel matrix-vector multiplication module comprises:
[0045] The admittance matrix parameter module is used to obtain the admittance matrix.
[0046] The current vector module is used to convert N current vectors into a current vector matrix.
[0047] The voltage vector module is used to multiply the admittance matrix and the current vector matrix and superimpose them to obtain the voltage vector result.
[0048] Furthermore, the parallel synchronization module includes:
[0049] The circuit parameters after identification and verification are bit quantized to obtain quantized byte data.
[0050] The newly entered quantized byte data is first entered into the low byte position of the shift register, and the remaining quantized byte data is shifted one byte position to the high byte position in turn. After the splicing is completed, the variable to be simulated is obtained.
[0051] The variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization.
[0052] Furthermore, the parallel synchronization module further includes: sending the variables to be simulated after parallel synchronization within the same clock cycle.
[0053] In a third aspect, a small-step real-time converter simulation acceleration system based on FPGA includes a server host computer, and the server host computer is bidirectionally connected to the FPGA acceleration card described in the second aspect via Gigabit or higher Ethernet.
[0054] Furthermore, the server host computer is used to run large-step converter simulation, perform converter modeling to be simulated, and prepare small-step simulation data.
[0055] Beneficial effect: The present invention provides a small-step real-time converter simulation acceleration method, device and system based on FPGA, which performs error detection and packet loss judgment on the received data, and accelerates the iterative calculation of multi-branch data by adopting the acceleration method of full expansion of branch historical variable multiplication and addition calculation and full expansion of parallel matrix-vector multiplication, so as to realize rapid simulation of the converter working condition.
[0056] Compared with the prior art, the present invention has the following beneficial effects:
[0057] (1) The present invention realizes application acceleration of small-step power system simulation based on FPGA and meets the real-time requirements. Within the simulation step time of the host computer, the server host computer data preparation, server host computer data transmission, FPGA acceleration card data reception, FPGA acceleration card small-step power system simulation, and FPGA acceleration card return small-step power system simulation results can be completed.
[0058] (2) The present invention can achieve efficient and stable data interaction and ensure the stability of computing and data communication.
[0059] (3) The present invention is scalable and can increase the scale of the simulated power grid by increasing the number of FPGA acceleration cards. BRIEF DESCRIPTION OF THE DRAWINGS
[0060] Figure 1 The present invention is a flowchart of a small-step real-time converter simulation acceleration method based on FPGA.
[0061] Figure 2 It is a schematic diagram of the connection of various modules inside the FPGA acceleration card of the present invention.
[0062] Figure 3 It is a connection diagram of the solution module of the present invention.
[0063] Figure 4It is a connection diagram of the parallel matrix-vector multiplication module of the present invention.
[0064] Figure 5 The diagram is a connection diagram of a small-step real-time converter simulation acceleration system based on FPGA.
[0065] Figure numerals: server host computer 100, FPGA acceleration card 200, asynchronous FIFO module 201, data packet identification and verification module 202, parallel synchronization module 203, solution module 204, result preparation module 205, variable cache module 301, historical variable multiplication and addition module 302, historical variable cache module 303, current vector iterative calculation module 304, parallel matrix-vector multiplication module 305, admittance matrix parameter 401, current vector 402, voltage vector 403. DETAILED DESCRIPTION
[0066] The technical solutions in the examples of the present invention are described clearly and completely below in conjunction with the accompanying drawings in the examples of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work belong to the protection scope of the present invention. The present invention is further described below in conjunction with specific embodiments.
[0067] Embodiment 1:
[0068] This embodiment introduces a small step size real-time converter simulation acceleration method based on FPGA. Figure 1 As shown, specifically including:
[0069] The received circuit parameters of the converter are cached, and the cached circuit parameters of the converter are converted in the clock domain to obtain the converted circuit parameters of the converter.
[0070] The converted circuit parameters of the converter are identified and verified by the data packet header.
[0071] The circuit parameters after identification and verification are bit-quantized and spliced into variables to be simulated, and then the variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization.
[0072] The small-step converter system is solved and simulated according to the variables to be simulated after parallel synchronization to obtain the voltage vector result.
[0073] The voltage vector result is judged as abnormal, and different judgment results are sent according to the judgment situation.
[0074] Furthermore, the method further includes: performing clock domain conversion on different judgment results and then sending them.
[0075] Further, the small-step converter system solution simulation is performed according to the variables to be simulated after parallel synchronization to obtain the voltage vector result, which specifically includes:
[0076] Cache parallel synchronization of variables to be simulated.
[0077] According to the branch type, circuit switch state and one of the parallel synchronous variables to be simulated, the historical variable result is calculated to obtain the historical variable result, and in the next clock cycle, according to the calculation complexity of the branch type, the historical variable result is sent within 15-22 clock cycles.
[0078] The N historical variable results are cached during the 16th to 23rd clock cycles.
[0079] According to the N historical variable results and the branch node relationship, N current vectors are iteratively calculated within N clock cycles.
[0080] The voltage vector result is obtained by multiplying and superimposing the N current vectors input in parallel with the admittance matrix.
[0081] Furthermore, the voltage vector result is obtained by multiplying and superimposing the N current vectors input in parallel with the admittance matrix, specifically including:
[0082] Get the admittance matrix.
[0083] Convert the N current vectors into a current vector matrix.
[0084] The admittance matrix is multiplied by the current vector matrix and superimposed to obtain the voltage vector result.
[0085] Further, the circuit parameters after identification and verification are bit-quantized and spliced into variables to be simulated, and then the variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization, specifically including:
[0086] The circuit parameters after identification and verification are bit quantized to obtain quantized byte data.
[0087] The newly entered quantized byte data is first entered into the low byte position of the shift register, and the remaining quantized byte data is shifted one byte position to the high byte position in turn. After the splicing is completed, the variable to be simulated is obtained.
[0088] The variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization.
[0089] Furthermore, the circuit parameters after identification and verification are bit-quantized and spliced into variables to be simulated, and then the variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization, and further includes:
[0090] The variables to be simulated after parallel synchronization are sent in the same clock cycle.
[0091] Embodiment 2:
[0092] This embodiment introduces an FPGA acceleration card, such as Figure 2 As shown, including:
[0093] The asynchronous FIFO module 201 is used to cache the received circuit parameters of the converter, and perform clock domain conversion on the cached circuit parameters of the converter to obtain the converted circuit parameters of the converter.
[0094] The data packet identification and verification module 202 is used to identify and verify the data packet header of the converted circuit parameters of the converter.
[0095] The parallel synchronization module 203 is used to perform bit quantization on the circuit parameters after identification and verification to splice them into variables to be simulated, and then perform parallel synchronization on the variables to be simulated to obtain the variables to be simulated after parallel synchronization.
[0096] The solving module 204 is used to perform small-step converter system solving simulation according to the variables to be simulated after parallel synchronization to obtain a voltage vector result.
[0097] The result preparation module 205 is used to judge the abnormal result of the voltage vector result and send different judgment results according to the judgment situation.
[0098] Furthermore, the result preparation module 205 further includes: performing clock domain conversion on different judgment results and then sending them.
[0099] Furthermore, the solving module 204 is as follows: Figure 3 As shown, including:
[0100] The variable cache module 301 is used to cache the variables to be simulated for parallel synchronization.
[0101] N historical variable multiplication and addition modules 302, the historical variable multiplication and addition modules 302 are used to calculate according to the branch type, circuit switch state and one of the parallel synchronous variables to be simulated, obtain the historical variable results, and in the next clock cycle, according to the calculation complexity of the branch type, send the historical variable results within 15-22 clock cycles.
[0102] The historical variable cache module 303 is used to cache N historical variable results in the 16th to 23rd clock cycles.
[0103] The current vector iterative calculation module 304 is used to iteratively calculate and obtain N current vectors within N clock cycles according to the N historical variable results and the branch node relationship.
[0104] The parallel matrix-vector multiplication module 305 is used to obtain a voltage vector result by multiplying the N current vectors input in parallel with the admittance matrix and superimposing them.
[0105] Furthermore, the parallel matrix-vector multiplication module 305 is as follows: Figure 4 As shown, including:
[0106] The admittance matrix parameter module 401 is used to obtain the admittance matrix.
[0107] The current vector module 402 is used to convert N current vectors into a current vector matrix.
[0108] The voltage vector module 403 is used to multiply the admittance matrix and the current vector matrix, and superimpose them to obtain a voltage vector result.
[0109] Furthermore, the parallel synchronization module 203 includes:
[0110] The circuit parameters after identification and verification are bit quantized to obtain quantized byte data.
[0111] The newly entered quantized byte data is first entered into the low byte position of the shift register, and the remaining quantized byte data is shifted one byte position to the high byte position in turn. After the splicing is completed, the variable to be simulated is obtained.
[0112] The variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization.
[0113] Furthermore, the parallel synchronization module 203 further includes: sending the variables to be simulated after parallel synchronization within the same clock cycle.
[0114] Furthermore, the asynchronous FIFO module 201 adopts a dual-port asynchronous FIFO module to cache the byte data sent by the server host computer.
[0115] Furthermore, the parallel synchronization module 203 includes a shift register array, which is composed of 8 shift registers with a depth of 64 bits. The structures of the shift registers in the shift register array are the same.
[0116] Embodiment 3:
[0117] This embodiment introduces a small step size real-time converter simulation acceleration system based on FPGA. Figure 5As shown, the data interaction system composed of the FPGA acceleration card and the server host described in Example 2 realizes the complete CPU-FPGA heterogeneous mixed step-size simulation function. The server host runs the large-step converter simulation, and the FPGA acceleration card runs the small-step converter simulation, so as to achieve real-time data interaction with the server host. Specifically including:
[0118] The server host computer 100 and the FPGA acceleration card 200 are bidirectionally connected via Gigabit Ethernet or higher, so as to realize high-speed data communication within 50 microseconds.
[0119] Furthermore, the server host computer 100 is used to model the converter to be simulated and prepare small-step simulation data, including: packaging the converter parameter matrix initialization data to be simulated into a UDP Ethernet data packet with a message header of 0x1111, and packaging the switch status of each branch of the converter into a UDP Ethernet data packet with a message header of 0x2222.
[0120] Furthermore, the Ethernet port of the FPGA acceleration card is driven by a Gigabit Ethernet physical layer chip.
[0121] Furthermore, the Ethernet transmission is transmitted in byte mode, that is, one byte of information is transmitted per working clock.
[0122] Embodiment 4:
[0123] This embodiment introduces a working method of a small-step real-time converter simulation acceleration system based on FPGA, specifically including:
[0124] The server host computer performs large-step converter system simulation to obtain the converter circuit parameters, and sends the converter circuit parameters to the FPGA accelerator card through the Ethernet protocol stack.
[0125] The FPGA accelerator card caches the circuit parameters of the converter into an asynchronous FIFO module, performs clock domain conversion, and obtains the converted circuit parameters of the converter.
[0126] The data packet identification and verification module performs data packet header identification and verification on the circuit parameters of the converter buffered by the asynchronous FIFO module.
[0127] After verification, the circuit parameters of the converter enter the parallel synchronization module, which performs bit quantization on all byte data and splices them into small-step converter system simulation variables. Then, parallel synchronization is performed to transmit the simulation variables to the solution module for small-step converter system solution simulation.
[0128] The solution module performs full parallel expansion on the calculation of historical variables of each branch of the converter with a parallelism of the number of branches N; the calculated historical variables of each branch of the converter are cached in parallel and synchronously for iterative calculation of the current vector; the current vector after iterative calculation is transmitted in parallel to the parallel matrix multiplication module, and the DSP multiplier is deployed in parallel through full expansion, so that the product of the admittance matrix elements and the current vector elements is calculated within one clock cycle, and the products are superimposed to obtain the voltage vector result.
[0129] The voltage vector result is passed to the result preparation module, and the result preparation module judges the abnormal result of the voltage vector result. If the result is abnormal, the result error identifier is sent to the asynchronous FIFO module; if the result is correct, when the number of iterations reaches the number required by the small step size, the result is packaged into an Ethernet data packet and sent to the asynchronous FIFO module.
[0130] The asynchronous FIFO module performs clock domain conversion on the error identifier or Ethernet data packet and sends it to the server host computer through the Ethernet protocol stack.
[0131] Furthermore, the circuit parameters of the converter include, but are not limited to: the number of circuit branches, branch types, node relationships, switch states, parameters of each component, admittance matrix, and simulation constants.
[0132] Furthermore, after the server host computer and the FPGA acceleration card shake hands through Ethernet, the server host computer program continuously sends multiple converter parameter matrix initialization data Ethernet data packets to the FPGA acceleration card. The FPGA acceleration card performs byte data cache and clock domain conversion on the converter parameter matrix initialization data Ethernet data packets through the asynchronous FIFO module. When the data of multiple Ethernet data packets received by the FPGA acceleration card are consistent and no packet is lost, the data is transmitted to the parallel synchronization module; if it is detected that the data of multiple Ethernet data packets are inconsistent or lost, an error flag string is returned to the server host computer.
[0133] Furthermore, the product of the admittance matrix element and the current vector element is calculated within one clock cycle, and the product is superimposed to obtain the voltage vector result, which specifically includes:
[0134] The admittance matrix parameters and the current vector elements are input into the parallel matrix-vector multiplication module in parallel and synchronously.
[0135] The size of the admittance matrix is M*M, the number of current vector elements is M, and a total of M*M multipliers are instantiated to obtain the product of the corresponding admittance matrix element and the current vector element.
[0136] Instantiate M accumulators to calculate the sum of the products of each admittance matrix element and the current vector element as the voltage vector result.
[0137] Furthermore, the large step size of the converter simulation model run by the server host computer is greater than 1 microsecond, the small step size of the converter simulation model run by the FPGA acceleration card is close to or less than or equal to 1 microsecond, and the small step size is more than 10 times the large step size.
[0138] Embodiment 5:
[0139] This embodiment introduces the application of the system of the present invention to the system simulation of the converter. The server host computer 100 is bidirectionally connected to the FPGA acceleration card 200. Specifically, high-speed data communication is performed between the server host computer 100 and the FPGA acceleration card 200 within 50 microseconds via Gigabit Ethernet.
[0140] The FPGA acceleration card 200 stores a small-step simulation and solving module 203 for high-frequency power system switching devices. Preferably, the solving module 300 uses a simulation step of less than 1 microsecond.
[0141] In this embodiment, the simulation step size is selected as 1 microsecond and the number of iterative calculations is selected as 50 times.
[0142] The server host computer 100 prepares small-step simulation data, including: packaging the power system parameter matrix initialization data to be simulated into a UDP Ethernet data packet with a message header of 0x1111, and packaging the switch status of each branch of the power system into a UDP Ethernet data packet with a message header of 0x2222.
[0143] The specific process of the FPGA acceleration card 200 performing small-step real-time power system simulation acceleration includes the following steps:
[0144] (1) The FPGA accelerator card 200 is connected to the server host computer 100 via an Ethernet cable. After power-on, the FPGA accelerator card 200 performs an ARP handshake verification with the server host computer 100. After the verification is successful, the next step is entered.
[0145] (2) The FPGA accelerator card 200 receives the converter parameter matrix initialization data Ethernet data packets sent by the server host computer 100 multiple times, stores the data packets into the asynchronous FIFO module 201, and converts the working clock domain frequency from 125 MHz to 100 MHz.
[0146] (3) The data buffered by the asynchronous FIFO module 201 is transmitted to the data packet identification and verification module 202. For the Ethernet data packet with a message header of 0x1111, the module checks whether the initialization data packet transmitted by the server host computer more than 100 times is correct. If it is correct, the Ethernet data packet with a message header of 0x1111 is transmitted to the parallel synchronization module 203.
[0147] (4) The FPGA acceleration card 200 receives the Ethernet data packets of the branch switch variables sent by the server host computer, stores the data packets into the asynchronous FIFO module 201, and converts the operating frequency from 125 MHz to 100 MHz.
[0148] (5) The data buffered by the asynchronous FIFO module 201 is transmitted to the data packet identification and verification module 202 . For the Ethernet data packet with the message header 0x2222, it is transmitted to the parallel synchronization module 203 .
[0149] (6) The parallel synchronization module 203 performs bit quantization on the correct data transmitted from the data packet identification and verification module 202 and splices them into variables, and then transmits the variables to the solution module 204 in parallel and synchronously; the parallel synchronization module 203 is composed of a shift register array, and the shift register array is composed of 8 shift registers with a depth of 64. After the byte data is transmitted to the shift register, it is quantized into 48 bits or 64 bits. According to the principle of little end first, the newly entered byte data first enters the low byte position of the shift register, and the remaining quantized data is shifted to the high byte position one byte position in turn; after the quantization and splicing are completed, the circuit simulation variables are obtained and effectively transmitted to the solution module within the same clock cycle; the structures of the various shift registers in the shift register array are the same and are transmitted to the solution module 204.
[0150] (7) The parallel synchronization module 202 transfers the bit-quantized circuit simulation variables to the solution module 203, and the variable cache module 301 stores the variables; according to the number of branches N of the variables, the historical variable multiplication and addition module 302 with a parallel degree of N is instantiated. Preferably, the number of circuit branches is 14; after the N historical variable multiplication and addition modules 302 complete the calculation, the calculated historical variable results are stored in the historical variable cache module 303. Specifically, the calculation of the historical variables requires 15-22 clock cycles, and the historical variables are stored in the historical variable cache module 303 in the 23rd clock cycle. In the variable result cache module 303; the current vector iteration calculation module 304 completes the iterative calculation of the current vector according to the relationship between the historical variables and each branch node within N clock cycles, and transmits the current vector to the parallel matrix vector multiplication module 305 to perform the matrix vector multiplication calculation of the admittance matrix and the current vector to obtain the final voltage vector result. Specifically, the parallel matrix vector multiplication module 305 obtains the voltage vector result within one clock cycle; repeat the calculation step (7), and when the number of iterations reaches 50 times required by the 1 microsecond small step simulation, enter step (8);
[0151] (8) The solving module 204 transmits the calculated voltage vector result to the result preparation module 205. The result preparation module 205 determines the abnormal result of the voltage vector result. If the result is abnormal, the result error identifier 0x3335 is sent to the asynchronous FIFO module. If the result is correct, the result is packaged into an Ethernet data packet with a message header of 0x3333 and sent to the asynchronous FIFO module 201.
[0152] (9) The asynchronous FIFO module 201 sends the error identifier or voltage vector result Ethernet data packet to the server host computer 100 through the Ethernet protocol stack.
[0153] Specifically, in this example, the parallel matrix-vector multiplication module 305 performs full parallel expansion optimization of matrix-vector multiplication with M=8, and the operation steps of left-multiplying the admittance matrix parameter 401 by the current vector 402 are as follows:
[0154] (1) Multiply the data of each row of the admittance matrix parameter 401 by the data of the current vector 402 in order of columns to obtain 8*8=64 products. For example, the admittance matrix element Y 23 The product of the current vector I3 is R 23 , and so on to get the product result matrix;
[0155] (2) Then add the products of each row of the product result matrix to obtain a voltage vector, for example, add the product results of the first row to obtain a voltage vector V0, and so on to obtain a voltage vector 403. Specifically, the number of single calculation cycles of the solution module 204 is composed of the following parts: the variable cache module 301 takes 1 clock cycle, the historical variable multiplication and addition module takes 22 clock cycles, the historical variable cache module 303 takes 1 clock cycle, the current vector iteration calculation module 304 takes 14 clock cycles, and the parallel matrix vector multiplication module 305 takes 1 clock cycle; the total single calculation of the solution module 204 requires 1+22+1+14+1=38 clock cycles, and 50 iterations require a total of 38*50=1900 clock cycles. When the working frequency of the solution module is 100MHz, the total time consumed is 1900*10=19000 nanoseconds=19 microseconds.
[0156] Specifically, a single Gigabit Ethernet communication between the server host computer 100 and the FPGA acceleration card 200 takes about 12 microseconds, and the total time for a single data interaction between the server host computer 100 and the FPGA acceleration card 200 is about 12+19=31 microseconds, meeting the real-time simulation requirement within 50 microseconds.
[0157] The FPGA acceleration card and the server host computer are bidirectionally connected and perform data communication via high-speed Ethernet; the FPGA acceleration card performs error detection and packet loss judgment on the data transmitted by the server host computer, the FPGA acceleration card internally stores a small-step power system simulation program, and uses an acceleration method of full expansion of branch historical variable multiplication and addition calculation and full expansion of parallel matrix-vector multiplication to accelerate the iterative calculation of multi-branch data of a high-frequency small-step circuit simulation model.
[0158] The FPGA acceleration card of the present invention can collaborate with the server host computer to perform large- and small-step real-time mixed-granularity power system simulation, and can complete large- and small-step mixed-granularity power system simulation of the server host computer and the FPGA acceleration card, and can increase the scale of the circuit simulation model by increasing the number of FPGA acceleration cards, and can accurately simulate the electrical behavior of high-frequency switching devices in real time, so that the power system simulation is closer to the actual power grid operation conditions.
[0159] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A small step size real-time converter simulation acceleration method based on FPGA, characterized in that: Specifically include: caching the received circuit parameters of the converter, and performing clock domain conversion on the cached circuit parameters of the converter to obtain converted circuit parameters of the converter; Performing data packet header identification and verification on the circuit parameters of the converted converter; The circuit parameters after identification and verification are bit-quantized and spliced into variables to be simulated, and then the variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization; Perform small-step converter system solution simulation based on the variables to be simulated after parallel synchronization to obtain the voltage vector result; The voltage vector result is judged as abnormal, and different judgment results are sent according to the judgment situation.
2. The FPGA-based small-step real-time converter simulation acceleration method according to claim 1, characterized in that: Also includes: Different judgment results are sent after clock domain conversion.
3. The FPGA-based small-step real-time converter simulation acceleration method according to claim 1 or 2, characterized in that: The method performs small-step converter system solution simulation according to the variables to be simulated after parallel synchronization to obtain a voltage vector result, specifically including: caching the variables to be simulated of parallel synchronization; calculating according to the branch type, the circuit switch state and one of the parallel variables to be simulated of the variables to be simulated of parallel synchronization to obtain a historical variable result, and sending the historical variable result within a clock cycle in the next clock cycle according to the calculation complexity of the branch type; caching N historical variable results in the bth clock cycle; iteratively calculating within N clock cycles according to the N historical variable results and the branch node relationship to obtain N current vectors; and obtaining a voltage vector result by multiplying and superimposing the N current vectors input in parallel with the admittance matrix.
4. The FPGA-based small-step real-time converter simulation acceleration method according to claim 1 or 2, characterized in that: The voltage vector result is obtained by multiplying and superimposing the N current vectors input in parallel with the admittance matrix, specifically including: Get the admittance matrix; Convert N current vectors into a current vector matrix; The admittance matrix is multiplied by the current vector matrix and superimposed to obtain the voltage vector result.
5. The FPGA-based small-step real-time converter simulation acceleration system according to claim 1 or 2, characterized in that: The step of bit-quantizing and splicing the circuit parameters after identification and verification into variables to be simulated, and then performing parallel synchronization on the variables to be simulated to obtain the variables to be simulated after parallel synchronization specifically includes: Quantizing the circuit parameters after identification and verification to obtain quantized byte data; The newly entered quantized byte data is first entered into the low byte position of the shift register, and the remaining quantized byte data is shifted one byte position to the high byte position in turn. After the splicing is completed, the variable to be simulated is obtained; The variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization.
6. The FPGA-based small-step real-time converter simulation acceleration method according to claim 5, characterized in that: The step of bit-quantizing and splicing the identified and verified circuit parameters into variables to be simulated, and then performing parallel synchronization on the variables to be simulated to obtain the variables to be simulated after parallel synchronization, further comprises: The variables to be simulated after parallel synchronization are sent in the same clock cycle.
7. An FPGA acceleration card, characterized in that: include: An asynchronous FIFO module is used to cache the received circuit parameters of the converter and perform clock domain conversion on the cached circuit parameters of the converter to obtain the converted circuit parameters of the converter; A data packet identification and verification module is used to identify and verify the data packet header of the converted circuit parameters of the converter; A parallel synchronization module is used to perform bit quantization on the circuit parameters after identification and verification to splice them into variables to be simulated, and then perform parallel synchronization on the variables to be simulated to obtain the variables to be simulated after parallel synchronization; A solution module is used to perform small-step converter system solution simulation according to the variables to be simulated after parallel synchronization to obtain a voltage vector result; The result preparation module is used to judge the abnormal result of the voltage vector result and send different judgment results according to the judgment situation.
8. The FPGA acceleration card according to claim 7, characterized in that: The result preparation module further includes: performing clock domain conversion on different judgment results and then sending them.
9. The FPGA acceleration card according to claim 7 or 8, characterized in that: The solution module comprises: Variable cache module, used to cache variables to be simulated for parallel synchronization; N historical variable multiplication and addition modules, the historical variable multiplication and addition modules are used to calculate according to the branch type, the circuit switch state and one of the parallel variables to be simulated of the parallel synchronous variables to be simulated, obtain the historical variable result, and send the historical variable result within a clock cycle in the next clock cycle according to the calculation complexity of the branch type; A historical variable cache module is used to cache N historical variable results in the bth clock cycle; A current vector iterative calculation module is used to iteratively calculate and obtain N current vectors within N clock cycles according to N historical variable results and branch node relationships; The parallel matrix-vector multiplication module is used to obtain a voltage vector result by multiplying and superimposing N current vectors input in parallel with the admittance matrix.
10. The FPGA acceleration card according to claim 9, characterized in that: The parallel matrix-vector multiplication module comprises: Admittance matrix parameter module, used to obtain the admittance matrix; A current vector module, used for converting N current vectors into a current vector matrix; The voltage vector module is used to multiply the admittance matrix and the current vector matrix and superimpose them to obtain the voltage vector result.
11. An FPGA acceleration card according to claim 7 or 8, characterized in that: The parallel synchronization module comprises: Quantizing the circuit parameters after identification and verification to obtain quantized byte data; The newly entered quantized byte data is first entered into the low byte position of the shift register, and the remaining quantized byte data is shifted one byte position to the high byte position in turn. After the splicing is completed, the variable to be simulated is obtained; The variables to be simulated are synchronized in parallel to obtain the variables to be simulated after parallel synchronization.
12. The FPGA acceleration card according to claim 11, characterized in that: The parallel synchronization module also includes: sending the variables to be simulated after parallel synchronization within the same clock cycle.
13. A small step size real-time converter simulation acceleration system based on FPGA, characterized in that: The method comprises a server host computer, wherein the server host computer is bidirectionally connected to the FPGA acceleration card according to any one of claims 7 to 12 via Gigabit Ethernet or higher.
14. The FPGA-based small-step real-time converter simulation acceleration system according to claim 13, characterized in that: The server host computer is used to run large-step converter simulation, perform converter modeling to be simulated, and prepare small-step simulation data.