Method, computing system and non-transitory computer-readable storage medium for estimating plurality of performance values of plurality of wafers

Abstract

A method, computing system and non-transitory computer-readable storage medium for estimating performance values of a plurality of wafers are provided. The method comprises the following steps: (A) training a first neural network module by using a plurality of oscillation period vectors of a wafer group to be divided to obtain a training error; (B) dividing the wafer group to be divided into a plurality of divided wafer groups according to the training error; (C) training a second neural network module by using the plurality of oscillation period vectors of the plurality of divided wafer groups to obtain a plurality of weight vectors respectively corresponding to the plurality of divided wafer groups; the product of the oscillation period vector of each divided wafer group and the weight vector of the divided wafer group is larger than the product of the oscillation period vector of the divided wafer group and the weight vector of each other divided wafer group. The method, the non-transitory computer readable storage medium and the computing system can estimate the efficiency values of a plurality of wafers with different process temperature voltage to delay (PVT-to-delay) sensitivities.

Description

Technical Field

[0001] The present disclosure relates to a technology for estimating chip performance values, and more particularly to a method, a computing system, and a non-transitory computer-readable storage medium for estimating multiple performance values ​​of multiple chips. Background Art

[0002] The critical path can be used to estimate the performance of an integrated circuit because the signal delay of the critical path determines the maximum frequency at which the chip can operate. Under different process voltage temperature (PVT) conditions, the critical path of the chip may change. The output of the ring oscillator will change in response to PVT variations, so the output of the ring oscillator is often used to construct a formula to estimate the chip performance value (i.e., the transmission delay of the critical path). However, different chips may have different PVT-to-delay sensitivities. In this case, the performance values ​​of different chips cannot be estimated by the same formula. Summary of the invention

[0003] The present disclosure provides a method for estimating multiple performance values ​​of multiple chips, which includes the following steps: (A) using multiple oscillation period vectors of a chip group to be divided to train a first neural network module corresponding to the chip group to be divided to obtain a training error of the chip group to be divided, wherein when step (A) is performed for the first time, the chip group to be divided includes multiple chips; (B) dividing the chip group to be divided into multiple divided chip groups according to the training error; and (C) using multiple oscillation period vectors of the multiple divided chip groups as training data of a second neural network module, so that the second neural network module outputs multiple weight vectors corresponding to the multiple divided chip groups respectively. The product of one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the one of the multiple divided chip groups is greater than the product of one or more oscillation period vectors of the one of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups.

[0004] In some embodiments of the method for estimating multiple performance values ​​of multiple chips, step (A) includes: (a1) using multiple oscillation period vectors of the chip group to be divided as training data for the first neural network module so that the first neural network module generates a preliminary weight vector corresponding to the chip group to be divided; and (a2) adjusting the preliminary weight vector to minimize the training error, wherein the training error is associated with: (1) the product of the system clock period and the unit vector and (2) the product of the multiple oscillation period vectors of the chip group to be divided and the preliminary weight vector.

[0005] In some embodiments of the method for estimating multiple performance values ​​of multiple chips, step (B) includes: (b1) in response to the training error not presenting a normal distribution, dividing the to-be-divided chip group into two chip groups; (b2) taking each of the two chip groups as the to-be-divided chip group to repeatedly perform step (A) and step (B) on each of the two chip groups; and (b3) in response to the training error of each of the multiple chip groups presenting a normal distribution, taking the multiple chip groups as the multiple divided chip groups to perform step (C).

[0006] In some embodiments of the method for estimating multiple performance values ​​of multiple chips, step (C) includes: (c1) using multiple oscillation period vectors of multiple divided chip groups as training data of a second neural network module so that the second neural network module outputs multiple weight vectors; (c2) adjusting the multiple weight vectors to minimize the training errors of the multiple divided chip groups, wherein the training error is associated with: (1) the product of one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the multiple divided chip groups, minus the product of the system clock cycle and the unit vector and (2) the product of one or more oscillation period vectors of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups, minus the product of the system clock cycle and the unit vector.

[0007] In some embodiments, the method for estimating a plurality of performance values ​​of a plurality of chips further comprises: (D) estimating a plurality of performance values ​​of the plurality of chips according to a plurality of weight vectors.

[0008] In some embodiments of the method for estimating a plurality of performance values ​​of a plurality of chips, each performance value represents a sum of a propagation delay and a setup time of a critical path of a corresponding one of the plurality of chips when the corresponding one of the plurality of chips operates at a predetermined operating voltage.

[0009] In some embodiments of the method for estimating a plurality of performance values ​​for a plurality of wafers, the first neural network module and the second neural network module are each feed-forward neural network (FNN) modules.

[0010] The present disclosure document provides a non-transitory computer-readable storage medium for storing one or more computer-readable instructions. When one or more processors execute the one or more computer-readable instructions, the one or more computer-readable instructions cause the one or more processors to perform the following steps to estimate multiple performance values ​​of multiple chips: (A) using multiple oscillation period vectors of the chip group to be divided to train a first neural network module corresponding to the chip group to be divided to obtain a training error of the chip group to be divided, wherein when step (A) is performed for the first time, the chip group to be divided includes multiple chips; (B) dividing the chip group to be divided into multiple divided chip groups according to the training error; and (C) using the multiple oscillation period vectors of the multiple divided chip groups as training data of a second neural network module, so that the second neural network module outputs multiple weight vectors corresponding to the multiple divided chip groups respectively. The product of the one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the one of the multiple divided chip groups is greater than the product of the one or more oscillation period vectors of the one of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups.

[0011] In some embodiments of a non-transitory computer-readable storage medium, step (A) includes: (a1) using multiple oscillation period vectors of the chip group to be divided as training data for the first neural network module so that the first neural network module generates a preliminary weight vector corresponding to the chip group to be divided; and (a2) adjusting the preliminary weight vector to minimize the training error, wherein the training error is associated with: (1) the product of the system clock period and the unit vector and (2) the product of the multiple oscillation period vectors of the chip group to be divided and the preliminary weight vector.

[0012] In some embodiments of the non-transitory computer-readable storage medium, step (B) includes: (b1) in response to the training error not presenting a normal distribution, dividing the chip group to be divided into two chip groups; (b2) taking each of the two chip groups as the chip group to be divided, and repeating step (A) and step (B) for each of the two chip groups; and (b3) in response to the training error of each of the plurality of chip groups presenting a normal distribution, taking the plurality of chip groups as a plurality of divided chip groups to perform step (C).

[0013] In some embodiments of the non-transitory computer-readable storage medium, step (C) includes: (c1) using multiple oscillation period vectors of multiple divided chip groups as training data of the second neural network module so that the second neural network module outputs multiple weight vectors; (c2) adjusting the multiple weight vectors to minimize the training errors of the multiple divided chip groups, wherein the training error is associated with: (1) the product of one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the multiple divided chip groups, minus the product of the system clock cycle and the unit vector and (2) the product of one or more oscillation period vectors of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups, minus the product of the system clock cycle and the unit vector.

[0014] In some embodiments of the non-transitory computer readable storage medium, the one or more processors are further configured to execute: (D) estimating a plurality of performance values ​​of a plurality of chips based on a plurality of weight vectors.

[0015] In some embodiments of the non-transitory computer readable storage medium, each performance value represents a sum of a propagation delay and a setup time of a critical path of a corresponding one of the plurality of chips when the corresponding one of the plurality of chips operates at an operating voltage of a predetermined magnitude.

[0016] In some embodiments of the non-transitory computer readable storage medium, the first neural network module and the second neural network module are each feed-forward neural network modules.

[0017] The present disclosure document provides a computing system, which includes one or more processors. The one or more processors are used to perform the following steps to estimate multiple performance values ​​of multiple chips: (A) using multiple oscillation period vectors of the chip group to be divided to train a first neural network module corresponding to the chip group to be divided to obtain a training error of the chip group to be divided, wherein when step (A) is performed for the first time, the chip group to be divided includes multiple chips; (B) dividing the chip group to be divided into multiple divided chip groups according to the training error; and (C) using multiple oscillation period vectors of the multiple divided chip groups as training data of a second neural network module, so that the second neural network module outputs multiple weight vectors corresponding to the multiple divided chip groups respectively. The product of one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the one of the multiple divided chip groups is greater than the product of one or more oscillation period vectors of the one of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups.

[0018] In some embodiments of the operating system, step (A) includes: (a1) using multiple oscillation period vectors of the chip group to be divided as training data of the first neural network module so that the first neural network module generates a preliminary weight vector corresponding to the chip group to be divided; and (a2) adjusting the preliminary weight vector to minimize the training error, wherein the training error is related to: (1) the product of the system clock period and the unit vector and (2) the product of the multiple oscillation period vectors of the chip group to be divided and the preliminary weight vector.

[0019] In some embodiments of the computing system, step (B) includes: (b1) in response to the training error not presenting a normal distribution, dividing the chip group to be divided into two chip groups; (b2) taking each of the two chip groups as the chip group to be divided, and repeating step (A) and step (B) for each of the two chip groups; and (b3) in response to the training error of each of the multiple chip groups presenting a normal distribution, taking the multiple chip groups as the multiple divided chip groups to perform step (C).

[0020] In some embodiments of the operating system, step (C) includes: (c1) using multiple oscillation period vectors of multiple divided chip groups as training data of the second neural network module so that the second neural network module outputs multiple weight vectors; (c2) adjusting the multiple weight vectors to minimize the training errors of the multiple divided chip groups, wherein the training error is associated with: (1) the product of one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the multiple divided chip groups, minus the product of the system clock cycle and the unit vector and (2) the product of one or more oscillation period vectors of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups, minus the product of the system clock cycle and the unit vector.

[0021] In some embodiments of the computing system, the one or more processors are further configured to execute: (D) estimating a plurality of performance values ​​of a plurality of chips based on a plurality of weight vectors.

[0022] In some embodiments of the computing system, each performance value represents a sum of a propagation delay and a setup time of a critical path of a corresponding one of the plurality of chips when the corresponding one of the plurality of chips operates at a predetermined operating voltage.

[0023] One of the advantages of the above-described method, non-transitory computer readable storage medium, and computing system is that multiple performance values ​​of multiple chips with different process temperature voltage to delay (PVT-to-delay) sensitivities can be accurately estimated without extracting the critical path of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A simplified functional block diagram of a chip according to an embodiment of the present disclosure;

[0025] Figure 2 A schematic diagram for explaining Formula 2 according to an embodiment of the present disclosure;

[0026] Figure 3 A flowchart of a method for estimating a plurality of performance values ​​of a plurality of chips according to an embodiment of the present disclosure;

[0027] Figure 4 is a schematic diagram for explaining steps S310 to S320 according to an embodiment of the present disclosure;

[0028] Figure 5 FIG. 4 is a schematic diagram for explaining step S330 according to an embodiment of the present disclosure.

[0029]

Explanation of symbols

[0030] 100: Chip

[0031] 110_1~110_r: Oscillator circuit

[0032] 120: monitoring control circuit

[0033] 130: Critical Path

[0034] OS_1~OS_r: oscillation signal

[0035] VDD: operating voltage

[0036] CLK: System clock

[0037] 210,220,230,T,Tes:matrix

[0038] M1,M2,M3: product

[0039] K: weight vector

[0040] K': initial weight vector

[0041] D: The period of the oscillation signal

[0042] DGa, DGb, DGc: Divided chip groups

[0043] max(): operator

[0044] 300: Method for estimating multiple performance values ​​of multiple wafers

[0045] S310~S340: Steps

[0046] 410A, 410B, 410C: first neural network module

[0047] 412: Multi-layer neural structure

[0048] 414:Optimizer

[0049] 420: Detection module

[0050] PDG, PDGa, PDGb: Chip groups to be divided

[0051] GA,GB: Chip Group

[0052] Tcycle: system clock cycle

[0053] Vo1, Vo2, Vo3, Vo4, Vo5: Oscillation period vector

[0054] Terr: training error

[0055] u: unit vector

[0056] 510: Second neural network module

[0057] 512: Multi-layer neural structure

[0058] 514: Operation module

[0059] 516:Optimizer

[0060] L: training error DETAILED DESCRIPTION

[0061] The following will illustrate the embodiments of the present disclosure with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.

[0062] Figure 1 The simplified functional block diagram of the chip 100 according to one embodiment of the present disclosure document is shown. The chip 100 is used to receive the working voltage VDD and the system clock CLK, and includes a plurality of oscillator circuits 110_1 to 110_r and a monitoring control circuit 120. The oscillator circuits 110_1 to 110_r are arranged at different positions of the chip 100. The oscillator circuits 110_1 to 110_r are used to generate a plurality of oscillation signals OS_1 to OS_r respectively. The monitoring control circuit 120 is coupled to the oscillator circuits 110_1 to 110_r, and is used to receive the oscillation signals OS_1 to OS_r, and perform signal processing such as filtering and amplifying the oscillation signals OS_1 to OS_r. The monitoring control circuit 120 is also used to output the oscillation signals OS_1 to OS_r.

[0063] In some embodiments, each of the oscillator circuits 110_1 ˜ 110_r may be implemented by a ring oscillator. In some embodiments, the period of each of the oscillation signals OS_1 ˜OS_r is used to reflect the process voltage-temperature (PVT) variation of the location corresponding to the oscillation signal.

[0064] It is worth mentioning that at least part of the oscillator circuits 110_1 to 110_r are disposed near the critical path 130 of the chip 100, so that the oscillation signals OS_1 to OS_r can be used to estimate the performance of the chip 100. The power consumption of the chip 100 can be reduced by reducing the operating voltage VDD, but the sum of the propagation delay and the setup time of the critical path 130 will also increase. When the sum of the propagation delay and the setup time of the critical path 130 increases to approximately equal to the system clock cycle Tcycle of the system clock CLK, the chip 100 will enter a fault state. Therefore, in some embodiments, estimating the performance of the chip 100 refers to calculating the sum of the propagation delay and the setup time of the critical path 130 when the chip 100 operates at a preset operating voltage VDD, thereby helping to achieve a balance between power consumption and performance when designing the chip 100.

[0065] By utilizing the characteristic that the periods of the oscillation signals OS_1 -OS_r change with the operating voltage VDD, the performance estimation function of the single chip 100 can be expressed by the following "Formula 1".

[0066]

[0067] The symbol “Tes” represents the performance value of the chip 100, that is, the sum of the propagation delay and the setup time of the critical path 130; the symbol “T 1×r ” is a 1×r matrix, whose r elements are the periods of the oscillation signals OS_1 to OS_r of the chip 100, where r is a positive integer; is a 1×r matrix representing the weight vector of the wafer 100 .

[0068] In some embodiments where the performance values ​​of multiple chips 100 need to be estimated simultaneously, the critical paths 130 of different chips 100 may have different process temperature voltage to delay (PVT-to-delay) sensitivities. Therefore, in order to accurately estimate the performance values ​​of multiple chips 100, "Formula 1" needs to be adjusted to the following "Formula 2". For ease of explanation, in the following embodiments, it is assumed that the number of chips 100 for which the performance values ​​need to be estimated is 5. However, the present disclosure is not limited to this, and "Formula 2" is applicable to estimating the performance values ​​of any number of chips 100.

[0069]

[0070] Please refer to Figure 2 ,in Figure 2 Schematic diagram for explaining Formula 2 according to an embodiment of the present disclosure. 5×1 is a 5×1 matrix, each element of which is the performance value of a chip 100, so the matrix Tes 5×1 Contains the performance values ​​of 5 chips 100. Matrix T 5×r is a 5×r matrix, each row vector of which (hereinafter referred to as an oscillation period vector) records the period of an oscillation signal OS_1 to OS_r of a chip 100. For example, the matrix T 5×r The first row vector [D11, D12, ... D1r] and the second row vector [D21, D22, ... D2r] of respectively record the periods of the oscillation signals OS_1 to OS_r of two different chips 100. Therefore, the matrix T 5×r It includes the cycles of the oscillation signal of five chips 100.

[0071] It is worth mentioning that the five chips 100 are divided into three divided chip groups DGa-DGb according to PVT delay sensitivity. 5×r In FIG. 1 , three dotted boxes represent the divided chip groups DGa to DGb from top to bottom. The number of chips 100 in the divided chip groups DGa to DGb is 2, 2, and 1, respectively. However, the number of divided chip groups and the number of chips 100 in each divided chip group are not limited thereto, and each divided chip group may include at least one chip 100. The grouping method of the chips 100 will be coordinated with Figure 3 to Figure 5 In some embodiments, the wafers 100 in the same group have the same or similar PVT sensitivity to delay.

[0072] Weight vector is a 1×r matrix, which is used to represent the weight vector of the jth divided chip group, where j is a positive integer in the range of 1 to 3 because there are 3 divided chip groups in total, that is, Figure 2 As shown, the weight vector Contains 3 different weight vectors as well as

[0073] It is worth mentioning that Figure 2 As shown, the matrix T 5×r It will be multiplied by the weight vector as well as Therefore, taking the divided chip group DGa as an example, the oscillation period vector of the divided chip group DGa (that is, the matrix T 5×rThe first row vector [D11, D12, ... D1r] and the second row vector [D21, D22, ... D2r] of In addition to multiplication, it is also multiplied by the two weight vectors of the divided chip groups DGb and DGc and Therefore, the products M1-M3 associated with the oscillation period vectors of the divided chip group DGa are located in the three matrices 210-230 respectively.

[0074] Operator max j () is used to select the largest product associated with the oscillation period vector of the j-th divided chip group as the matrix Tes 5×1 One or more elements of . Taking the divided chip group DGa as an example, the operator max1() is used to select the largest one among the products M1-M3. Ideally, the multiple oscillation period vectors of the divided chip group DGa (that is, the matrix T 5×r The 1st to 2nd row vectors of ) and the weight vector of the divided chip group DGa The product M1 is greater than the multiple oscillation period vectors of the divided chip group DGa and the weight vectors of the remaining divided chip groups DGb and DGc. and The product of M2 and M3 will be Figure 3 to Figure 5 In this case, the product M1 will be taken as the matrix Tes 5×1 In general, a product of one or more oscillation period vectors of each of the plurality of divided chip groups and the weight vector of the one of the plurality of divided chip groups (e.g., product M1) is greater than a product of one or more oscillation period vectors of the one of the plurality of divided chip groups and the weight vector of each of the remaining divided chip groups (e.g., products M2 and M3).

[0075] In some embodiments, the product M1 is greater than the products M2 and M3, which means that any element in the product M1 is greater than the corresponding element in the products M2 and M3. Elements greater than M2 Also greater than the element of M3

[0076] The process of estimating the performance values ​​of the remaining divided chip groups in the aforementioned five chips 100 through "Formula 2" and the functions of the operators max2() and max3() are similar to the aforementioned multiple embodiments regarding the first divided chip group, and for the sake of brevity, they are not repeated here.

[0077] In some embodiments, since the periods of the oscillation signals OS_1 -OS_r are measurable, the matrix T 5×r The row vector of is known. However, since the PVT delay sensitivity of the chip 100 is difficult to measure directly, the weight vector The value of and the grouping method of the wafers 100 (eg, the total number of divided wafer groups and the divided wafer group to which each wafer 100 belongs) cannot be determined by measuring the wafers 100.

[0078] Therefore, in order to construct Formula 2, this disclosure document proposes Figure 3 A method 300 for estimating a plurality of performance values ​​of a plurality of wafers 100 is provided. Any combination of features of the method 300 may be implemented by a plurality of instructions stored in a non-transitory computer-readable medium. When the instructions are executed by one or more processors of a computing system (not shown), such as a personal computer, a notebook computer, or other suitable device with logical computing capabilities, the instructions cause part or all of the method 300 to be executed. It should be understood that the method 300 may include more or fewer steps than those shown in the flowchart, and the steps in the method 300 may be performed in any suitable order.

[0079] In some embodiments, the computing system is coupled to the five chips 100 and is used to receive the period of the oscillation signals OS_1 ˜OS_r of each of the five chips 100 .

[0080] Please also refer to Figure 3-4 ,in Figure 4 Schematic diagram for explaining steps S310-S320 according to an embodiment of the present disclosure. When executing step S310 for the first time, the computing system uses all the chips 100 whose performance values ​​need to be estimated as the chip group PDG to be divided, that is, the chip group PDG to be divided includes 5 chips 100. Then, the computing system uses a plurality of oscillation period vectors Vo1-Vo5 of the chip group PDG to be divided to train the first neural network module 410A corresponding to the chip group PDG to be divided, wherein the oscillation period vectors Vo1-Vo5 respectively record the periods of the oscillation signals OS_1-OS_r of the 5 chips 100.

[0081] Specifically, in step S310, the operation system may use the oscillation period vectors Vo1-Vo5 as training data of the first neural network module 410A, and input them into the multi-layer neural structure 412 of the first neural network module 410A, so that the first neural network module 410A generates a preliminary weight vector corresponding to the chip group to be divided PDG. The initial weight vector is a 1×r matrix. In some embodiments, the first neural network module 410A may be implemented by a feedforward neural network (FNN) module.

[0082] Next, in order to calculate the training error Terr 1×m The operation system will first calculate the oscillation period vectors Vo1~Vo5 and the preliminary weight vector The product of (hereinafter referred to as the initial performance value Tes′ of the chip group to be divided PDG) 1×m ), where the initial performance value Tes′ 1×m is a 1×m matrix, where m is the number of chips 100 in the chip group PDG to be divided. Next, the computing system will convert the initial performance value Tes′ 1×m Subtract the system clock cycle Tcycle of the system clock CLK and the unit vector The product of to get the training error Terr 1×m . In other words, the loss function of the first neural network module 410A is the following "Formula 3".

[0083]

[0084] The computing system will convert the training error Terr 1×m Provided to the optimizer 414 of the first neural network module 410A. The optimizer 414 is used to 1×m Adjust the weights of the multi-layer neural structure 412, thereby adjusting the preliminary weight vector To minimize the training error Terr 1×m In some embodiments, the optimizer 414 may be implemented by an Adam optimizer. In summary, the computing system may adjust the preliminary weight vector To minimize the training error Terr 1×m , and the training error Terr 1×m It is related to the following two things: (1) the period Tcycle of the system clock and the unit vector The product of (2) the multiple oscillation period vectors Vo1 to Vo5 of the chip group PDG to be divided and the preliminary weight vector The product of .

[0085] Next, in step S320, the computing system is used to calculate the training error Terr 1×m The chip group PDG to be divided is divided into multiple chip groups. Specifically, the operation system will minimize the training error Terr 1×m Provided to the detection module 420. The detection module 420 is used to determine the minimized training error Terr 1×mIf the detection module 420 determines whether the training error Terr 1×m The detection module 420 divides the wafer group PDG to be divided into two wafer groups GA and GB, wherein the wafer groups GA and GB each include at least one wafer 100. In some embodiments, the detection module 420 divides the wafer group PDG to be divided into the wafer groups GA and GB using a k-means clustering method, and the wafers 100 divided into the same group have the same or similar PVT delay sensitivity.

[0086] In step S320, the operation system further uses chip groups GA and GB as chip groups to be divided PDGa and PDGb, respectively, and then repeats steps S310 to S320 for chip groups GA and GB (i.e., chip groups to be divided PDGa and PDGb). Figure 4 As shown, one or more oscillation period vectors of the chip group to be divided PDGa will be used to train the first neural network module 410B corresponding to the chip group to be divided PDGa, and one or more oscillation period vectors of the chip group to be divided PDGb will be used to train the first neural network module 410C corresponding to the chip group to be divided PDGb. The first neural network modules 410B and 410C are similar to the first neural network module 410A. For the sake of brevity, the training process of the first neural network modules 410B and 410C will not be repeated here.

[0087] On the other hand, after executing steps S310 to S320 one or more times, if the detection module 420 determines in step S320 that the training errors Terr of all chip groups are 1×m All of them show normal distribution, and the computing system will treat all chip groups as Figure 5 The plurality of divided chip groups DGa-DGc are then processed, and step S330 is executed. In some embodiments, the normal distribution refers to the training error Terr 1×m The average value of all elements of is 0 or approximately 0.

[0088] Please refer to Figure 5 ,in Figure 5 FIG. 4 is a schematic diagram for explaining step S330 according to an embodiment of the present disclosure. Figure 5 The divided chip groups DGa~DGc are Figure 2 The matrix T 5×rEach of the divided chip groups DGa~DGc includes at least one chip 100, so each divided chip group DGa~DGc has one or more oscillation period vectors. In step S330, the operation system uses the oscillation period vectors Vo1~Vo5 of the divided chip groups DGa~DGc as training data for the second neural network module 510. In some embodiments, the second neural network module 510 can be implemented by a feedforward neural network module.

[0089] In step S330, the operation system first uses the oscillation period vectors Vo1-Vo5 as training data of the second neural network 510 and inputs them into the multi-layer neural structure 512 of the second neural network module 510, so that the multi-layer neural structure 512 outputs weight vectors corresponding to the divided chip groups DGa-DGc respectively. and

[0090] Next, the computing system converts the oscillation period vectors Vo1 to Vo5 and the weight vector and The calculation module 514 of the second neural network module 510 calculates the training error L of the divided chip groups DGa-DGc. The loss function for calculating the training error L is shown in the following "Formula 4".

[0091] L = α × [(Tmain_a-Tcycle) 2 +(Tmain_b-Tcycle) 2 +(Tmain_c-Tcycle) 2 ]+β×[SiLU(Tother_1a-Tcycle)+SiLU(Tother_2a-Tcycle)+SiLU(Tother_1b-Tcycle)+SiLU(Tother_2b-Tcycle)+SiLU(Tother_1c-Tcycle)+SiLU(Tother_2c-Tcycle)] "Formula 4"

[0092] In Formula 4, the matrices Tmain_a, Tmain_b, and Tmain_c represent the oscillation period vectors Vo1 to Vo2 and the weight vector The product of "the oscillation period vector Vo3~Vo4 and the weight vector The product of the oscillation period vector Vo5 and the weight vector The product of .

[0093] In addition, in Formula 4, the matrices Tother_1a and Tother_2a represent the weight vectors of the oscillation period vectors Vo1 to Vo2 and the divided chip group DGb. The product of the oscillation period vector Vo1~Vo2 and the weight vector of the divided chip group DGc The matrices Tother_1b and Tother_2b represent the product of the oscillation period vectors Vo3-Vo4 and the weight vectors of the divided chip groups DGa. The product of the oscillation period vector Vo3-Vo4 and the weight vector of the divided chip group DGc The matrices Tother_1c and Tother_2c represent the product of the oscillation period vector Vo5 and the weight vector of the divided chip group DGa. The product of the oscillation period vector Vo5 and the weight vector of the divided chip group DGb The product of .

[0094] In Formula 4, the system clock Tcycle is multiplied by the unit vector u with the appropriate number of columns. T To perform matrix subtraction, for simplicity, the unit vector u T Not shown in Formula 4. In summary, the training error L is related to: (1) the product of one or more oscillation cycle vectors of each of the plurality of divided chip groups and the weight vector of the one of the plurality of divided chip groups (i.e., the matrix Tmain), minus the difference obtained by multiplying the system clock cycle Tcycle and the unit vector, and is related to (2) the product of one or more oscillation cycle vectors of the one of the plurality of divided chip groups and the weight vector of each of the remaining divided chip groups (i.e., the matrix Tother), minus the difference obtained by multiplying the system clock cycle Tcycle and the unit vector.

[0095] In step S330, the training error L is provided to the optimizer 516 of the second neural network module 510. The optimizer 516 is used to adjust the weights of the multi-layer neural structure 512 to adjust the weight vector Then minimize the training error L. The weight vector obtained when the training error L is minimized and It can be used as the weight vector in Formula 2 To construct "Formula 2". It is worth mentioning that in the process of minimizing the training error L, the matrix Tmain will change to be greater than all the corresponding matrices Tother. For example, any element of the matrix Tmain_a will be greater than the elements of the corresponding positions of the matrices Tother_1a and Tother_2a, where the matrices Tmain_a, Tother_1a and Tother_2a are Figure 2 The product of M1, M2 and M3.

[0096] In some embodiments, method 300 further includes step S340. In step S340, the computing system calculates the weight vector and Estimate multiple (eg, 5) performance values ​​of the aforementioned multiple (eg, 5) wafers 100. Specifically, the computing system uses the weight vector obtained through steps S310 to S330 and Formula 2 is constructed and used to estimate the five performance values ​​of the five chips 100 (i.e., the five performance values ​​generated Figure 2 The matrix Tes 5×1 ). The estimation process of multiple performance values ​​of multiple chips 100 has been described in the above-mentioned Figure 2 For the sake of brevity, the description is not repeated here. As mentioned above, each performance value represents the sum of the delay time and the setup time of the critical path 130 of the corresponding one of the plurality of chips 100 when the corresponding one of the plurality of chips 100 operates at a predetermined working voltage VDD.

[0097] In summary, the method 300 can accurately estimate a plurality of performance values ​​of a plurality of wafers 100 having different PVT sensitivity to delay without extracting the critical path 130 of the wafer 100 .

[0098] In some embodiments, first neural network modules 410A-410C, detection module 420 and / or second neural network module 510 may be implemented by a plurality of computer-readable instructions stored in a non-transitory computer-readable storage medium, and one or more processors in a computing system may execute these computer-readable instructions to run first neural network modules 410A-410C, detection module 420 and / or second neural network module 510 in the computing system. In other embodiments, first neural network modules 410A-410C, detection module 420 and / or second neural network module 510 may be implemented as one or more processors (e.g., application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs)) in the computing system to run first neural network modules 410A-410C, detection module 420 and / or second neural network module 510 in the computing system.

[0099] As used herein, "about", "approximately" or "roughly approximately" generally refers to an error or range of a numerical value within 20%, preferably within 10%, and more preferably within 5%. If there is no explicit explanation in the text, the numerical values ​​mentioned are all regarded as approximate values, that is, the error or range represented by "about", "approximately" or "roughly approximately".

[0100] Certain words are used in the specification and claims to refer to specific components. However, those with ordinary knowledge in the technical field should understand that the same component may be referred to by different nouns. The specification and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The "including" mentioned in the specification and claims is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal connected to the second element through other elements or connection means.

[0101] The description method of "and / or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes the meaning of the plural term.

[0102] The above are only preferred embodiments of the present disclosure. Various modifications and equivalent changes may be made to the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.

Claims

1. A method for estimating a plurality of performance values ​​of a plurality of wafers, characterized in that: Include: (A) using a plurality of oscillation period vectors of a chip group to be divided to train a first neural network module corresponding to the chip group to be divided to obtain a training error of the chip group to be divided, wherein when step (A) is performed for the first time, the chip group to be divided includes the plurality of chips; (B) dividing the to-be-divided chip group into a plurality of divided chip groups according to the training error; and (C) using the plurality of oscillation period vectors of the plurality of divided chip groups as training data for a second neural network module, so that the second neural network module outputs a plurality of weight vectors respectively corresponding to the plurality of divided chip groups, A product of one or more oscillation period vectors of each of the plurality of divided chip groups and a weight vector of the one of the plurality of divided chip groups is greater than a product of the one or more oscillation period vectors of the one of the plurality of divided chip groups and a weight vector of each of the remaining divided chip groups.

2. The method for estimating the plurality of performance values ​​of the plurality of chips according to claim 1, wherein: Step (A) comprises: (a1) using a plurality of oscillation period vectors of the chip group to be divided as training data for the first neural network module, so that the first neural network module generates a preliminary weight vector corresponding to the chip group to be divided; and (a2) adjusting the preliminary weight vector to minimize the training error, wherein the training error is associated with: (1) a product of a system clock cycle and a unit vector and (2) a product of the plurality of oscillation cycle vectors of the chip group to be divided and the preliminary weight vector.

3. The method for estimating the plurality of performance values ​​of the plurality of chips as claimed in claim 2, wherein: Step (B) comprises: (b1) in response to the training error not presenting a normal distribution, dividing the to-be-divided wafer group into two wafer groups; (b2) taking each of the two chip groups as the chip group to be divided, and repeating step (A) and step (B) for each of the two chip groups; and (b3) In response to the training error of each of the plurality of chip groups presenting a normal distribution, the plurality of chip groups are used as the plurality of divided chip groups to perform step (C).

4. The method for estimating the plurality of performance values ​​of the plurality of chips as claimed in claim 1, wherein: Step (C) comprises: (c1) using the plurality of oscillation period vectors of the plurality of divided chip groups as training data for the second neural network module, so that the second neural network module outputs the plurality of weight vectors; (c2) adjusting the multiple weight vectors to minimize a training error of the multiple divided chip groups, wherein the training error is associated with: (1) a product of the one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the one of the multiple divided chip groups, minus a difference obtained by multiplying a system clock cycle and a unit vector and (2) a product of the one or more oscillation period vectors of the one of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups, minus a difference obtained by multiplying the system clock cycle and the unit vector.

5. The method for estimating the plurality of performance values ​​of the plurality of chips as claimed in claim 1, wherein: Also includes: (D) estimating the plurality of performance values ​​of the plurality of chips according to the plurality of weight vectors.

6. The method for estimating the plurality of performance values ​​of the plurality of chips as claimed in claim 1, wherein: Each performance value represents a sum of a propagation delay and a setup time of a critical path of a corresponding one of the plurality of chips when the corresponding one of the plurality of chips operates at a working voltage of a predetermined magnitude.

7. The method for estimating the plurality of performance values ​​of the plurality of chips as claimed in claim 1, wherein: The first neural network module and the second neural network module are each a feed-forward neural network (FNN) module.

8. A non-transitory computer-readable storage medium for storing one or more computer-readable instructions, characterized in that: When one or more processors execute the one or more computer readable instructions, the one or more computer readable instructions cause the one or more processors to perform the following steps to estimate a plurality of performance values ​​of a plurality of chips: (A) using a plurality of oscillation period vectors of a chip group to be divided to train a first neural network module corresponding to the chip group to be divided to obtain a training error of the chip group to be divided, wherein when step (A) is performed for the first time, the chip group to be divided includes the plurality of chips; (B) dividing the to-be-divided chip group into a plurality of divided chip groups according to the training error; and (C) using the plurality of oscillation period vectors of the plurality of divided chip groups as training data for a second neural network module, so that the second neural network module outputs a plurality of weight vectors respectively corresponding to the plurality of divided chip groups, A product of one or more oscillation period vectors of each of the plurality of divided chip groups and a weight vector of the one of the plurality of divided chip groups is greater than a product of the one or more oscillation period vectors of the one of the plurality of divided chip groups and a weight vector of each of the remaining divided chip groups.

9. The non-transitory computer-readable storage medium of claim 8, wherein: Step (A) comprises: (a1) using a plurality of oscillation period vectors of the chip group to be divided as training data for the first neural network module, so that the first neural network module generates a preliminary weight vector corresponding to the chip group to be divided; and (a2) adjusting the preliminary weight vector to minimize the training error, wherein the training error is associated with: (1) a product of a system clock cycle and a unit vector and (2) a product of the plurality of oscillation cycle vectors of the chip group to be divided and the preliminary weight vector.

10. The non-transitory computer-readable storage medium of claim 9, wherein: Step (B) comprises: (b1) in response to the training error not presenting a normal distribution, dividing the to-be-divided wafer group into two wafer groups; (b2) taking each of the two chip groups as the chip group to be divided, and repeating step (A) and step (B) for each of the two chip groups; and (b3) In response to the training error of each of the plurality of chip groups presenting a normal distribution, the plurality of chip groups are used as the plurality of divided chip groups to perform step (C).

11. The non-transitory computer readable storage medium of claim 8, wherein: Step (C) comprises: (c1) using the plurality of oscillation period vectors of the plurality of divided chip groups as training data for the second neural network module, so that the second neural network module outputs the plurality of weight vectors; (c2) adjusting the multiple weight vectors to minimize a training error of the multiple divided chip groups, wherein the training error is associated with: (1) a product of the one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the one of the multiple divided chip groups, minus a difference obtained by multiplying a system clock cycle and a unit vector and (2) a product of the one or more oscillation period vectors of the one of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups, minus a difference obtained by multiplying the system clock cycle and the unit vector.

12. The non-transitory computer readable storage medium of claim 8, wherein: The one or more processors are further configured to execute: (D) estimating the plurality of performance values ​​of the plurality of chips according to the plurality of weight vectors.

13. The non-transitory computer readable storage medium of claim 8, wherein: Each performance value represents a sum of a propagation delay and a setup time of a critical path of a corresponding one of the plurality of chips when the corresponding one of the plurality of chips operates at a working voltage of a predetermined magnitude.

14. The non-transitory computer readable storage medium of claim 8, wherein: The first neural network module and the second neural network module are each a feed-forward neural network (FNN) module.

15. A computing system, characterized in that: The method comprises one or more processors, wherein the one or more processors are configured to perform the following steps to estimate a plurality of performance values ​​of a plurality of chips: (A) using a plurality of oscillation period vectors of a chip group to be divided to train a first neural network module corresponding to the chip group to be divided to obtain a training error of the chip group to be divided, wherein when step (A) is performed for the first time, the chip group to be divided includes the plurality of chips; (B) dividing the to-be-divided chip group into a plurality of divided chip groups according to the training error; and (C) using the plurality of oscillation period vectors of the plurality of divided chip groups as training data for a second neural network module, so that the second neural network module outputs a plurality of weight vectors respectively corresponding to the plurality of divided chip groups, A product of one or more oscillation period vectors of each of the plurality of divided chip groups and a weight vector of the one of the plurality of divided chip groups is greater than a product of the one or more oscillation period vectors of the one of the plurality of divided chip groups and a weight vector of each of the remaining divided chip groups.

16. The computing system according to claim 15, wherein: Step (A) comprises: (a1) using a plurality of oscillation period vectors of the chip group to be divided as training data for the first neural network module, so that the first neural network module generates a preliminary weight vector corresponding to the chip group to be divided; and (a2) adjusting the preliminary weight vector to minimize the training error, wherein the training error is associated with: (1) a product of a system clock cycle and a unit vector and (2) a product of the plurality of oscillation cycle vectors of the chip group to be divided and the preliminary weight vector.

17. The computing system according to claim 16, wherein: Step (B) comprises: (b1) in response to the training error not presenting a normal distribution, dividing the to-be-divided wafer group into two wafer groups; (b2) taking each of the two chip groups as the chip group to be divided, and repeating step (A) and step (B) for each of the two chip groups; and (b3) In response to the training error of each of the plurality of chip groups presenting a normal distribution, the plurality of chip groups are used as the plurality of divided chip groups to perform step (C).

18. The computing system according to claim 15, wherein: Step (C) comprises: (c1) using the plurality of oscillation period vectors of the plurality of divided chip groups as training data for the second neural network module, so that the second neural network module outputs the plurality of weight vectors; (c2) adjusting the multiple weight vectors to minimize a training error of the multiple divided chip groups, wherein the training error is associated with: (1) a product of the one or more oscillation period vectors of each of the multiple divided chip groups and the weight vector of the one of the multiple divided chip groups, minus a difference obtained by multiplying a system clock cycle and a unit vector and (2) a product of the one or more oscillation period vectors of the one of the multiple divided chip groups and the weight vector of each of the remaining divided chip groups, minus a difference obtained by multiplying the system clock cycle and the unit vector.

19. The computing system of claim 15, wherein: The one or more processors are further configured to execute: (D) estimating the plurality of performance values ​​of the plurality of chips according to the plurality of weight vectors.

20. The computing system of claim 15, wherein: Each performance value represents a sum of a propagation delay and a setup time of a critical path of a corresponding one of the plurality of chips when the corresponding one of the plurality of chips operates at a working voltage of a predetermined magnitude.

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