Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, pixel driving lines and data lines are electrically connected with pixel driving circuits respectively and are used for transmitting control signals and data signals to the pixel driving circuits respectively; the shift register circuit is used for transmitting control signals to the pixel driving lines, and the gating circuit is used for transmitting data signals to the data lines. The shifting register circuit comprises a plurality of cascaded shifting registers, namely a plurality of cascaded first shifting registers and a second shifting register cascaded with the first shifting registers, and the first shifting registers are located in the area where the pixel driving circuit array is located. The second shifting register is located on the side, facing the edge of the display panel, of the pixel driving circuit array, and the gating circuit is located between the pixel driving circuit array and the second shifting register. Therefore, the signal interference between the shift register circuit and the data line can be reduced, and the display accuracy of a display product can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] Existing display products usually have various circuits arranged therein. How to reasonably arrange them to reduce interference between different signals has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device, which are beneficial to reducing signal interference between a shift register circuit and a data line and improving the display accuracy of a display product.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a pixel driving circuit array, a shift register circuit and a gating circuit, as well as pixel driving lines and data lines, wherein the pixel driving circuit array comprises a plurality of pixel driving circuits;

[0006] The pixel driving line and the data line are electrically connected to the pixel driving circuit respectively, the pixel driving line is used to transmit a control signal to the pixel driving circuit, and the data line is used to transmit a data signal to the pixel driving circuit;

[0007] The shift register circuit is configured to transmit the control signal to the pixel driving line, and the gating circuit is configured to transmit the data signal to the data line;

[0008] The shift register circuit includes a plurality of cascaded shift registers, and the shift register includes a plurality of cascaded first shift registers and a second shift register cascaded with the first shift register, the first shift register is located in the area where the pixel driving circuit array is located, and the second shift register is located on the side of the pixel driving circuit array facing the edge of the display panel; the gating circuit is located between the pixel driving circuit array and the second shift register.

[0009] In a second aspect, the present disclosure provides a display device, comprising the display panel provided by the first aspect of the present invention.

[0010] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0011] The present disclosure adjusts the positional relationship of the shift register and the gating circuit relative to the pixel driving circuit array, specifically, multiple first shift registers in the shift register circuit are set in the area where the pixel driving circuit array is located, and the second shift register cascaded with the first shift register is set in the area outside the pixel driving circuit array, that is, set on the side of the edge of the pixel driving circuit array facing the display panel, and the edge of the display panel mentioned in this embodiment refers to the lower edge of the display panel. At this time, the second shift register and the gating circuit are both located on the side of the edge of the pixel driving circuit array facing the display panel, and the second shift register is located between the gating circuit and the edge of the display panel, that is, the gating circuit is closer to the pixel driving circuit array than the second shift register, that is, the gating circuit will be closer to the end of the data line. At this time, when the end of the data line is connected to the gating circuit, the connection can be achieved without passing through the second shift register, thereby avoiding the signal interference problem of the second shift register on the data line, which is conducive to improving the accuracy of the data signal transmitted on the data line. At the same time, by setting the enabling circuit between the second shift register and the pixel driving circuit array, there is no interference from other lines between the data line and the enabling circuit, and the data line can be connected to the enabling circuit without changing the line, thereby avoiding the risk of disconnection or short circuit caused by changing the data line, which is beneficial to improving the display stability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0014] Figure 1 Shown is a planar structural diagram of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 2 Shown is a planar structural diagram of a display panel provided by an embodiment of the present disclosure;

[0016] Figure 3 Shown is a planar structural diagram of a display panel provided in the related art;

[0017] Figure 4 FIG. 1 is a connection diagram of a shift register circuit provided by an embodiment of the present disclosure;

[0018] Figure 5 Shown is a layout diagram of a pixel driving circuit, a gating circuit, and a shift register circuit;

[0019] Figure 6 Shown is a connection circuit diagram of a data line and a strobe circuit;

[0020] Figure 7 Shown is a connection layout diagram of a data line and a gating circuit;

[0021] Figure 8 The figure shows a relative position relationship diagram of the pixel driving circuit, the gating circuit and the shift register circuit;

[0022] Fig. 9 Shown is a schematic diagram of a connection between a pixel driving circuit and a data line;

[0023] Fig.10 The figure shows a schematic diagram showing the relative position relationship between the level transmission signal line and the gate control line;

[0024] Fig.11 Shown is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure;

[0025] Fig.12 The figure shows a relative position relationship diagram between a switch element group and a gating control line in a gating circuit provided by an embodiment of the present disclosure;

[0026] Fig.13 Another relative position relationship diagram between the switch element group and the gating control line in the gating circuit provided by the embodiment of the present disclosure is shown;

[0027] Fig.14 Shown is a schematic diagram of a layout of a gating control line and a first signal line overlapping the gating control line;

[0028] Fig.15 Another planar structural diagram of a display panel provided by an embodiment of the present disclosure is shown;

[0029] Fig.16 Shown is a layout diagram of a pixel driving circuit array in a display panel provided by an embodiment of the present disclosure, facing an edge side of the display panel;

[0030] Fig.17 Shown is a reference layout diagram of a pixel driving circuit array facing an edge side of a display panel;

[0031] Fig.18 It is a schematic diagram of a layout of the light emitting element in the embodiment of the present disclosure;

[0032] Fig.19 Shown is a schematic diagram of a partial layout of a display panel;

[0033] Fig. 20 Shown is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0036] Figure 1 FIG. 1 is a plan view of a display panel provided in an embodiment of the present disclosure. Please refer to FIG. Figure 1 The present disclosure provides a display panel 100, including a pixel driving circuit array 10, a shift register circuit 20 and a gating circuit 30, as well as pixel driving lines GL and data lines DL. The pixel driving circuit array 10 includes a plurality of pixel driving circuits 11. It should be noted that: Figure 1 Only the relative position relationship among the pixel driving circuit array 10, the shift register circuit 20 and the selection circuit 30 is illustrated, and the number and arrangement of the pixel driving circuits 11 actually included in the pixel driving circuit array 10 are not limited, nor is the number of shift registers actually included in the shift register circuit 20 limited.

[0037] In the display panel 100 provided by the present disclosure, the pixel driving line GL and the data line DL are electrically connected to the pixel driving circuit 11 respectively, and the pixel driving line GL is used to transmit a control signal to the pixel driving circuit 11, and the control signal is, for example, a reset signal for controlling the pixel driving circuit 11 to reset, or a control signal for controlling the pixel driving circuit 11 to write data, or a light emitting control signal for controlling the pixel driving circuit 11 to emit light. It should be noted that Figure 1 Only one pixel driving line GL connected to the pixel driving circuit 11 is shown, but the number of pixel driving lines GL actually connected to the pixel driving circuit 11 is not limited. In the present disclosure, the data line DL is used to transmit a data signal to the pixel driving circuit 11; the shift register circuit 20 is configured to transmit a control signal to the pixel driving line GL, and the pixel driving line GL further transmits the control signal to the pixel driving circuit 11; the gating circuit 30 is configured to transmit a data signal to the data line DL, and the data line DL further transmits the data signal to the pixel driving circuit 11.

[0038] In the present disclosure, the shift register circuit 20 includes a plurality of cascaded shift registers, and the shift register includes a plurality of cascaded first shift registers 21 and a second shift register 22 cascaded with the first shift register 21, the first shift register 21 is located in the area where the pixel driving circuit array 10 is located, and the second shift register 22 is located on the side of the pixel driving circuit array 10 facing the edge B of the display panel; the selection circuit 30 is located between the pixel driving circuit array 10 and the second shift register 22. Figure 1 The illustrated embodiment is described by taking the pixel driving circuit array 10 including a plurality of pixel driving circuits 11 arranged in a matrix as an example. In this case, the area where the pixel driving circuit array 10 is located can be regarded as a rectangular area formed by all pixel driving circuits 11. In the present disclosure, the first shift register 21 is located in the rectangular area formed by the pixel driving circuit array 10, and the second shift register 22 is located outside the rectangular area. It should be noted that Figure 1 The rectangular area formed by the pixel driving circuit array 10 in the figure is only for illustration, but is not limited thereto. In some other embodiments of the present disclosure, the area where the pixel driving circuit array 10 is located may also be embodied in other non-rectangular shapes. It should also be noted that, Figure 1 Only one group of shift register circuits 20 in the display panel is shown, but the number of shift register circuits 20 actually included in the display panel is not limited. Figure 2 , Figure 2 FIG. 1 is a planar structural diagram of a display panel provided by an embodiment of the present disclosure. Figure 2 The illustrated embodiment shows two groups of shift register circuits 20 in the display panel, the first shift registers 21 in the shift register circuits 20 are all located in the area where the pixel drive circuit array 10 is located, and the second shift registers 22 are located on the side of the pixel drive circuit array 10 facing the edge B of the display panel. It should be noted that the two groups of shift register circuits 20 can transmit control signals to the same pixel drive line GL to improve the driving capability of the control signal, or they can transmit control signals to different pixel drive lines GL respectively, which is not specifically limited in the present disclosure.

[0039] In the process of designing the display panel, the inventors found an implementation method as follows Figure 3 , all the shift registers in the shift register circuit 20' are arranged in the area where the pixel driving circuit array 10' is located, and the gating circuit 30' is arranged outside the pixel driving circuit array 10', that is, the gating circuit 30' is located on the side of the shift register circuit 20' facing the edge B' of the display panel, Figure 3 The figure shows a planar structure diagram of a display panel provided in the related art. However, the inventors have found that Figure 3In the design method, the data signal on the data line DL' is interfered by other signals because the end of the data line DL' needs to pass through the shift register at the level closest to the selection circuit 30' when connected to the selection circuit 30'. If the data line DL' and the signal line corresponding to the shift register are set on the same layer, signal interference will occur. The inventor further discovered that in order to reduce the signal interference of the shift register on the data line DL', the data line DL' at the position of the shift register closest to the selection circuit 30' can be switched to avoid being set on the same layer as the signal line corresponding to the shift register. However, since the data line DL' is thin, switching the line will increase the risk of disconnection or short circuit, affecting the display effect.

[0040] Based on the above problems, the present disclosure adjusts the positional relationship between the shift register and the gating circuit 30 relative to the pixel driving circuit array 10. For details, please refer to Figure 1 and Figure 2 , multiple first shift registers 21 in the shift register circuit 20 are arranged in the area where the pixel driving circuit array 10 is located, and the second shift register 22 cascaded with the first shift register 21 is arranged in the area outside the pixel driving circuit array 10, that is, arranged on the side of the pixel driving circuit array 10 facing the edge B of the display panel, and the edge B of the display panel mentioned in this embodiment refers to the lower edge of the display panel. At this time, the second shift register 22 and the gating circuit 30 are both located on the side of the pixel driving circuit array 10 facing the edge B of the display panel, and the second shift register 22 is located between the gating circuit 30 and the edge B of the display panel, that is, the gating circuit 30 is closer to the pixel driving circuit array 10 than the second shift register 22, so that the gating circuit 30 will be closer to the end of the data line DL. At this time, when the end of the data line DL is connected to the gating circuit 30, the connection can be achieved without passing through the second shift register 22, thereby avoiding the signal interference problem of the second shift register 22 on the data line DL, which is conducive to improving the accuracy of the data signal transmitted on the data line DL. At the same time, by setting the enabling circuit 30 between the second shift register 22 and the pixel driving circuit array 10, there is no other line interference between the data line DL and the enabling circuit 30, and the data line DL can be connected to the enabling circuit 30 without changing the line, thereby avoiding the risk of disconnection or short circuit caused by changing the data line DL, which is beneficial to improving the display stability of the display panel.

[0041] Figure 4 FIG. 2 is a schematic diagram showing a connection of a shift register circuit 20 provided in an embodiment of the present disclosure. Figure 1 , Figure 2 and Figure 4In an optional embodiment of the present disclosure, the output terminal OUT of the first shift register 21 is electrically connected to the pixel driving circuit 11 through the pixel driving line GL, the display panel further includes a binding pad P1, and the output terminal OUT of the second shift register 22 is electrically connected to the binding pad P1. In other words, the first shift register 21 mentioned in the embodiment of the present disclosure is a shift register connected to the pixel driving line GL and used to provide a control signal to the pixel driving circuit 11 through the pixel driving line GL, while the second shift register 22 can be regarded as a dummy shift register, whose output terminal OUT is not connected to the pixel driving line GL, but is connected to the binding pad P1 in the display panel, and the second shift register 22 does not need to provide a control signal to the pixel driving line GL in the display panel.

[0042] Optionally, refer to Figure 1 , Figure 2 and Figure 4 The display panel further includes a test signal line CL, and the output end of the second shift register 22 is also electrically connected to the test signal line CL.

[0043] The binding pad P1 introduced in the display panel is used to bind with the control chip or the flexible circuit board, so as to realize the electrical connection between the control chip or the flexible circuit board and the binding pad P1, and then realize the electrical connection with the circuit in the display panel. The display panel is formed by cutting the motherboard. Before cutting, a test pad VT-P is arranged on the motherboard. The test pad VT-P is used to electrically connect with the test signal line CL in the display panel, and is used to detect the corresponding signal. For example, the output terminal OUT of the second shift register 22 is electrically connected with the test signal line CL. The signal of the second shift register 22 can be tested before cutting. During the test, the test probe is inserted into the test pad VT-P, and the signal at the output terminal of the second shift register 22 can be detected, so as to determine whether the control signal output by the shift register circuit 20 is abnormal. The test pad VT-P does not need to be bound with the control chip or the flexible circuit board. Optionally, when the display panel is cut, the test pad VT-P will be cut off.

[0044] Figure 5 FIG. 1 is a layout diagram of a pixel driving circuit, a gating circuit, and a shift register circuit. Figure 6 FIG. 1 is a circuit diagram showing a connection between a data line DL and a gate circuit 30. Figure 7 FIG. 1 is a connection layout diagram of the data line DL and the gate circuit 30. Please refer to FIG. Figure 5 , Figure 6 and Figure 7 In an optional embodiment of the present disclosure, the gating circuit 30 includes a plurality of switch element groups 31, the switch element group 31 includes at least two switch elements T, and the output end of the switch element T is electrically connected to the data line DL; please combine Figure 1 and Figure 2 The data line DL includes an electrically connected first portion X1 and a second portion X2, the first portion X1 is at least located in the area where the pixel driving circuit array 10 is located, and the second portion X2 is located on the side of the pixel driving circuit array 10 facing the edge B of the display panel, the first portion X1 is electrically connected to the switching element T through the second portion X2, and the first portion X1 and the second portion X2 are arranged in the same layer.

[0045] Figure 6 and Figure 7 In the embodiment shown, the switch element group 31 in the gating circuit 30 includes three switch elements T as an example for explanation, but it is not limited to this. In the display panel, the output end of the switch element T in the switch element group 31 is electrically connected to the data line DL in a one-to-one correspondence, and is used to transmit the data signal to the data line DL. In this embodiment, the first portion X1 of the data line DL can be regarded as a line segment of the data line DL located in the area where the pixel driving circuit array 10 is located, and the second portion X2 can be regarded as a line segment for electrically connecting the first portion X1 with the switch element T in the gating circuit 30. When the switch element group 31 is not arranged directly below the first portion X1 in the data line DL, the electrical connection between the first portion X1 and the switch element T in the gating circuit 30 can be achieved by introducing the second portion X2 arranged directly above the switch element group 31. The extension direction of at least part of the line segment in the second portion X2 is different from the extension direction of at least part of the line segment in the first portion X1. In this embodiment, the first portion X1 extends along the second direction D2, and at least part of the line segment in the second portion X2 extends along the first direction D1 as an example for explanation. In the present embodiment, when the first portion X1 and the second portion X2 of the data line DL are arranged on the same film layer, the electrical connection between the data line DL and the switching element group 31 can be achieved without changing the line of the data line DL, which is beneficial to avoiding the risk of disconnection or short circuit caused by changing the line. Moreover, when the first portion X1 and the second portion X2 of the data line DL are arranged on the same layer, it is also beneficial to avoid the punching process introduced when the two are arranged on different layers, thereby also helping to simplify the manufacturing process of the data line DL.

[0046] Please continue to refer to Figure 5 , Figure 6 and Figure 7 In an optional embodiment of the present disclosure, the gating circuit 30 includes at least two gating control lines K. This embodiment is described by taking the gating circuit 30 including three gating control lines K (respectively, a first gating control line K1, a second gating control line K2, and a third gating control line K3) as an example. The number of gating control lines K is the same as the number of switching elements included in a single switching element group 31. In the same switching element group 31, the gates of different switching elements are connected to different gating control lines K. The gating control line K extends along the first direction D1, the first portion X1 extends along the second direction D2, and the first direction D1 and the second direction D2 intersect. Figure 1and Figure 2 , along the second direction D2, the switch element group 31 is located between the gate control line K and the pixel driving circuit array 10. The three gate control lines K in the gate circuit 30 send enable signals in time division to turn on the switch elements T connected thereto. When the switch elements T are turned on, the data signals can be transmitted to the corresponding data lines DL through the turned-on switch elements.

[0047] Please combine Figure 1 , Figure 2 , Figure 5 , Figure 6 and Figure 7 In the embodiment of the present disclosure, the gate control line K is arranged on the side of the switch element group 31 away from the pixel driving circuit array 10, that is, the switch element group 31 is closer to the pixel driving circuit array 10 than the gate control line K. In this way, when the data line DL is electrically connected to the switch element T in the switch element group 31, it does not need to pass through the gate control line K. The gate control line K will not affect the connection between the data line DL and the switch element T. The data line DL can be electrically connected to the switch element T without changing the line, thereby avoiding the risk of disconnection or short circuit caused by changing the line.

[0048] Please combine Figure 1 , Figure 2 , Figure 5 , Figure 6 and Figure 7 In the gating circuit 30, the gating control line K extends along the first direction D1 as a whole, occupying almost the entire width of the display panel along the first direction D1. In the shift register circuit 20, a single shift register occupies a relatively small width of the display panel along the first direction D1. Figure 3 If the gating circuit 30' is disposed on the side of each shift register facing the edge B' of the display panel, in the area between the pixel driving circuit array 10' and the gating circuit 30', in addition to the shift register, some other spaces (such as Figure 3The space on both sides of the second shift register 22' along the first direction D1 cannot be effectively utilized, resulting in a waste of space. However, in the present disclosure, when the gating circuit 30 is arranged between the second shift register 22 and the pixel driving circuit array 10, on the side of the gating circuit 30 facing the edge B of the display panel, the space on both sides of the second shift register 22 along the first direction D1 can be effectively utilized, for example, some routing lines originally arranged below the second shift register 22 are moved up, and wiring is performed in the space on both sides of the second shift register 22 (this will be described in detail in subsequent embodiments), thereby reducing the space occupied by the second shift register 22 and the aforementioned routing lines as a whole along the second direction D2, so that the electrostatic protection circuit and other structures originally arranged below the second shift register 22 can be moved toward the direction of the pixel driving circuit array 10, so that some transistors in the display panel (such as transistors in the electrostatic protection circuit) are kept away from the edge B of the display panel. Considering that the display panel is formed by cutting the motherboard, the edge B of the display panel can be regarded as the cutting edge. When the transistor in the display panel is set away from the edge B of the display panel, it is beneficial to reduce the impact of the laser on the transistor during the laser cutting process and reduce the risk of laser damage to the transistor.

[0049] Figure 8 FIG. 1 is a diagram showing a relative position relationship among the pixel driving circuit 11, the gating circuit 30 and the shift register circuit 20. Fig. 9 FIG. 1 is a schematic diagram showing a connection between a pixel driving circuit and a data line. Fig.10 The figure shows a schematic diagram showing the relative position relationship between the level transmission signal line X0 and the gate control line K. Figure 8 and Fig.10 In an optional embodiment of the present disclosure, the second shift register 22 is electrically connected to the first shift register 21 through a level transfer signal line X0. Along a direction perpendicular to the plane where the display panel is located, the level transfer signal line X0 overlaps with the selection control line K to form a first overlapping area Q1. In the first overlapping area Q1, the level transfer signal line X0 and the selection control line K are arranged in different layers.

[0050] Please combine Figure 5 , Figure 8 , Fig. 9 and Fig.10When the second shift register 22 is set on the side of the gating circuit 30 facing the edge B of the display panel, it is equivalent to introducing the gating circuit 30 between the first shift register 21 and the second shift register 22. Since the gating control line K extends along the first direction D1 as a whole, and the level transmission signal line X0 connecting the first shift register 21 and the second shift register 22 extends along the second direction D2 as a whole, the level transmission signal line X0 will overlap with the gating control line K to form a first overlapping area Q1. In this embodiment, the level transmission signal line X0 and the gating control line K in the first overlapping area Q1 are set in different film layers, which is conducive to reducing the signal interference between the two. Optionally, in the first overlapping area Q1, the gating control line K is located in the first metal layer M1 in the display panel, and the level transmission signal line is located in the second metal layer M2 in the display panel. The specific setting method of the gating control line K and the film layer structure of the display panel will be described in subsequent embodiments.

[0051] In the embodiment of the present disclosure, when the selection circuit 30 is set between the first shift register 21 and the second shift register 22, the level transfer signal line X0 led out from the first shift register 21 will pass through the selection control line K in the selection circuit 30 and be electrically connected to the second shift register 22. At this time, it is necessary to swap the connection between one of the selection control line K and the level transfer signal line X0. Fig.10 The embodiment shown shows the way of switching the gate control line K. Fig.10 Optionally, the selection control line K includes a main body K01 and a bridge portion K02 connected to the main body K01. The main body K01 and the bridge portion K02 are arranged in different layers and both extend along the first direction D1. The bridge portion K02 is at least partially located in the first overlapping area Q1, and the level transfer signal line X0 is arranged in the same layer as the main body K01. For the selection control line K, its main body K01 accounts for a large proportion of the entire selection control line K. The bridge portion K02 is a cross-line structure arranged to facilitate other signal lines passing through the selection control line K. The proportion of the bridge portion K02 in the entire selection control line K is less than that of the main body K01. Optionally, the main body K01 is located in the second metal layer M2, and the bridge portion K02 is located in the first metal layer M1.

[0052] In this embodiment, a main body K01 and a bridge portion K02 connected to the main body K01 are introduced into the selection control line K. The bridge portion K02 and the main body K01 are located in different film layers, and the two are electrically connected through the connecting hole LK. When the level transmission signal line X0 passes through the selection control line K, the level transmission signal line X0 overlaps with the bridge portion K02 in the first overlapping area Q1. At this time, the level transmission signal line X0 can be set in the same film layer as the main body K01 in the selection control line K, which can avoid interference with the selection control line K, reasonably utilize the film layer structure in the display panel, and also avoid line switching of the level transmission signal line X0.

[0053] Optionally, the line width of the gate control line K is greater than the line width of the first portion X1 of the data line DL. If the second shift register 22 is disposed between the gate circuit 30 and the pixel driving circuit array 10, in order to realize the electrical connection between the data line DL and the gate circuit 30, the data line DL needs to pass through the second shift register 22. Since the number of data lines DL is large and the setting space is small, the line width thereof is small. If the data line DL is connected by changing the line to reduce signal interference, there is a risk of short circuit or disconnection. If the enabling circuit 30 is arranged between the second shift register 22 and the pixel driving circuit array 10, the data line DL can be connected to the enabling circuit 30 without crossing the line. Considering that the first shift register 21 and the second shift register 22 need to be connected by the level transfer signal line X0, the level transfer signal line X0 will pass through the enabling control line K. Therefore, in the embodiment of the present disclosure, the line width of the enabling control line K is set to be larger, so that it is larger than the line width of the data line DL. Therefore, the main part K01 and the bridge part K02 of the enabling control line K are connected across the line, which is beneficial to reduce the risk caused by line switching.

[0054] Fig.11 FIG. 1 is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure. In an optional implementation of the present disclosure, the display panel includes a substrate 00 and a first metal layer M1 and a second metal layer M2 disposed on the substrate 00. The resistivity of the second metal layer M2 is less than the resistivity of the first metal layer M1. Fig.10 The main body K01 of the gate control line K and the level transfer signal line X0 are located in the second metal layer M2, and the bridge portion K02 of the gate control line K is located in the first metal layer M1.

[0055] A plurality of transistors are usually provided in the display panel, such as the transistors in the pixel driving circuit 11, the transistors corresponding to the switch elements of the gating circuit 30, the transistors in the shift register circuit 20, and the like. In the film layer structure of the display panel, optionally, the gate of the transistor is provided in the above-mentioned first metal layer M1, and the source and drain of the transistor are provided in the above-mentioned second metal layer M2. Optionally, the material of the first metal layer M1 is mainly Mo, and the material of the second metal layer M2 is Ti-Al-Ti. Due to the characteristics of the material itself, the impedance of the first metal layer M1 is greater than the impedance of the second metal layer M2, that is, the resistivity of the first metal layer M1 is greater than the resistivity of the second metal layer M2, and the conductive effect of the second metal layer M2 is better than the conductive effect of the first metal layer M1. When the main body K01 of the gating control line K is provided in the second metal layer M2 in the present disclosure, it is beneficial to reduce the overall impedance of the gating control line K, reduce the voltage drop of the control signal transmitted on the gating control line K, and thus help to improve the accuracy of the signal transmitted by the gating control line K. In addition, when the level transmission signal line X0 is also disposed in the second metal layer M2 in the embodiment of the present disclosure, it is also beneficial to reduce the impedance of the level transmission signal line X0 and the voltage drop of the transmitted signal, thereby improving the accuracy of the level transmission signal transmitted by the level transmission signal.

[0056] Optionally, the data line DL provided in the embodiment of the present disclosure is also located in the second metal layer M2 to reduce the impedance of the data line DL, which is beneficial to reduce the voltage drop of the data signal transmitted on the data line DL and improve the accuracy of the data signal transmitted on the data line DL.

[0057] Optionally, the display panel provided by the embodiment of the present disclosure also includes a semiconductor layer poly arranged on the side of the first metal layer M1 facing the substrate 00 and an auxiliary metal layer M0 arranged on the side of the semiconductor layer poly facing the substrate. It should be noted that the display panel may include a transistor with a dual-gate structure. At this time, one of the gates of the transistor may be located in the first metal layer M1, and the other gate may be located in the auxiliary metal layer M0. In the direction perpendicular to the plane where the substrate 00 is located, the first metal layer M1 and the auxiliary metal layer M0 are overlapped with the semiconductor layer poly, and the auxiliary metal layer M0 also has a light-shielding function to prevent light from affecting the semiconductor layer poly. Optionally, a capacitor metal layer MC is further included between the first metal layer M1 and the second metal layer M2, and the capacitor metal layer MC can form a capacitor structure with the second metal layer M2. Optionally, a third metal layer M3 and a fourth metal layer M4 are also included on the side of the second metal layer M2 away from the substrate, and the third metal layer M3 and the fourth metal layer M4 can both be used to lay signal lines.

[0058] Please refer to Figure 5 , Figure 8 and Fig.10In an optional embodiment of the present disclosure, along the first direction D1, the bridge portion K02 is located between adjacent switch element groups 31; along the second direction D2, the second shift register 22 and the switch element group 31 overlap; along the first direction D1, the level transfer signal line X0 connected to the second shift register 22 is located on the same side of the second shift register 22 and the switch element group 31 corresponding to the second shift register 22. This embodiment is described by taking the example that the level transfer signal line X0 is located on the right side of the switch element group 31 and the corresponding second shift register 22. Specifically, when the bridge portion K02 is introduced into the enable control line K, the bridge portion K02 can be set in the area between adjacent switch element groups 31, and the level transfer signal line X0 is wired on the same side of the second shift register 22 and the switch element group 31 adjacent to the second shift register 22. The level transfer signal line X0 led out from the first shift register 21 passes through the bridge portion K02 of the enable control line K and is connected to the second shift register 22. In this way, the interference between the level transfer signal line X0 and the enable control line K can be avoided, and it is also helpful to simplify the wiring structure of the level transfer signal line X0.

[0059] Please refer to Figure 8 and Fig.10 , and combined with Figure 5 In an optional embodiment of the present disclosure, the level transfer signal line X0 includes a main part X01 and a winding part X02 electrically connected to the main part, the main part X01 is located in the area where the pixel driving circuit array 10 is located, along the second direction D2, the winding part X02 is located on the side of the edge B of the pixel driving circuit array 10 facing the display panel, and the winding part X02 is electrically connected to the second shift register 22; the main part X01 extends along the second direction D2, and the winding part X02 includes a first winding X21, a connecting part X23 and a second winding X22 electrically connected in sequence, the first winding X21 and the second winding X22 extend along the first direction D1, the connecting part X23 extends along the second direction D2, the first winding X21 is connected to the main part X01, and the second winding X22 is connected to the second shift register 22.

[0060] It should be noted that this embodiment shows a scheme in which the bridge portion K02 in the selection control line K and the main portion X01 of the level transfer signal line X0 are staggered in the second direction D2, that is, the bridge portion K02 in the selection control line K is not located in the area directly below the extension direction of the main portion X01 of the level transfer signal line X0, and therefore it is necessary to introduce a winding portion X02 for the main portion X01 of the level transfer signal line X0 so as to realize the electrical connection between the main portion X01 and the second shift register 22 through the winding portion X02. Taking the figure as an example, when the bridge portion K02 of the selection control line K is located in the lower right area of ​​the main portion X01 of the level transmission signal line X0, the main portion X01 is first connected to the first winding X21 extending along the first direction D1 in the winding portion X02, the first winding X21 extends to the right area of ​​the main portion X01, and the first winding X21 is connected to the connecting portion X23 extending along the second direction D2, which is equivalent to the connecting portion X23 extending below the first winding X21, passing through the bridge portion K02 of the selection control line K, and then continuing to extend downward and then connected to the second winding X22, the second winding X22 extends along the second direction D2 to the area where the second shift register 22 is located, and realizes the connection with the second shift register 22. In this way, by introducing the winding portion X02, the line change of the level transmission signal line X0 is avoided, which is conducive to simplifying the film layer setting of the display panel. At the same time, if the level transmission signal line X0 is set as a whole in the second metal layer M2, it is also conducive to reducing the impedance of the level transmission signal line X0 and improving the transmission efficiency of the level transmission signal. It should be noted that when the bridge portion K02 is located directly below the main portion X01 of the stage transfer signal line X0, there is no need to introduce a winding portion.

[0061] Please continue to refer to Figure 8 and Fig.10In an optional embodiment of the present disclosure, the pixel driving circuit array 10 includes a plurality of pixel circuit column groups Z0 arranged along the first direction D1, and the pixel circuit column group includes at least two pixel circuit columns. This embodiment is described by taking a single pixel circuit column group including three pixel circuit columns as an example, but is not limited thereto. There is a spacing area Q0 between adjacent pixel circuit column groups Z0, and along the second direction D2, the bridge portion K02 overlaps the spacing area Q0. In this way, it is equivalent to setting the bridge portion K02 in the gate control line K in the area directly below the spacing area Q0 along the second direction D2. Taking into account that signal lines extending along the second direction D2 are arranged between the pixel circuit column groups Z0, some of these signal lines (the types of these signal lines will be specifically described in subsequent embodiments) need to extend to the side of the edge B of the pixel driving circuit array 10 facing the display panel and be electrically connected to the binding pad P1. Therefore, when the bridge portion K02 of the selection control line K is set in the area directly below the spacing area Q0, the aforementioned signal line will be able to pass through the bridge portion K02 for further extension. These signal lines can be set in the second metal layer M2. When passing through the area where the bridge portion K02 is located, there is no need to change the line or wind the line, and the original routing layout can be maintained. This is conducive to simplifying the wiring difficulty of the routing in the display panel after the introduction of the bridge portion K02, and simplifying the manufacturing process.

[0062] Please refer to Figure 4 , Figure 8 and Fig.10 In an optional embodiment of the present disclosure, the display panel further includes a plurality of first signal lines 51 extending along the second direction D2, and the first signal lines 51 are configured to provide signals to the shift register circuit 20; the first signal lines 51 are located on at least one side of the shift register circuit 20 along the first direction D1 and in the spacing area Q0; along a plane perpendicular to the light emitting surface of the display panel, the first signal lines 51 overlap with the bridge portion K02 and do not overlap with the main body portion K01; the first signal lines 51 are arranged on the same layer as the main body portion K01.

[0063] The first signal line 51 mentioned in this embodiment is a wiring connected to the shift register circuit 20 and providing a signal to the shift register circuit 20, such as a constant high-level signal line VGH providing a high-level signal to the shift register circuit 20, a constant low-level signal line VGL providing a low-level signal to the shift register circuit 20, and a first clock signal line XCK and a second clock signal line CK providing a clock signal to the shift register circuit 20. Optionally, the above four signal lines can be distributed in pairs on both sides of the corresponding shift register circuit 20 along the first direction D1, for example, the first clock signal line XCK and the second clock signal line CK are located on the left side of the shift register circuit 20, and the constant high-level signal line VGH and the constant low-level signal line VGL are located on the right side of the shift register circuit 20, so as to facilitate the connection between the shift register circuit 20 and these signal lines and make the wiring of these signal lines more uniform. When the first signal line 51 extends to the side of the pixel driving circuit array 10 facing the edge B of the display panel, it will overlap with the bridge portion K02 of the gate control line K and be arranged in a different layer from the bridge portion K02, for example, it can be arranged in the same layer as the main body K01 of the gate control line K. In this way, the first signal line 51 can be wired according to the original wiring method without the need for line switching. Therefore, even if the gate unit is set between the second shift register 22 and the pixel driving circuit array 10, it will not affect the wiring structure of the first signal line 51. Optionally, the first signal line 51 and the main body K01 of the gate control line K are both located in the second metal layer M2 of the display panel. The resistivity on the second metal layer M2 is relatively low, which is more conducive to reducing the voltage drop during signal transmission and improving signal transmission efficiency.

[0064] Please continue to refer to Figure 8 and Fig.10In an optional embodiment of the present disclosure, the level transmission signal line X0 is located in the spacing area Q0 and is located on the side of the first signal line 51 facing the shift register circuit 20. In addition to the first signal line 51 mentioned in the above embodiment, the signal line connected to the shift register circuit 20 also includes a level transmission signal line X0. The level transmission signal line X0 is used to connect the shift registers of adjacent levels. For example, for the first shift register 21, the output end of the first shift register 21 of this level is not only electrically connected to the pixel driving line GL, but also connected to the input end of the next level shift register through the level transmission signal line X0. The first signal line 51 is a signal line shared by multiple shift registers in the shift register circuit 20. For example, the high-level signals required by the multiple shift registers in the shift register circuit 20 are all provided by the same constant high-level signal line VGH, and the level transmission signal line X0 is used to transmit the output signal of the shift register of this level to the shift register of the next level. In this embodiment, when both the level transmission signal line X0 and the first signal line 51 are arranged in the spacing area Q0, the level transmission signal line X0 is arranged on the side of the first signal line 51 facing the shift register circuit 20, that is, the level transmission signal line X0 is closer to the shift register circuit 20 than the first signal line 51, so that it is more convenient to connect the level transmission signal line X0 with the shift registers of two adjacent stages. Optionally, the level transmission signal line X0 is located in the second metal layer M2.

[0065] Please continue to refer to Figure 8 and Fig.10 In an optional embodiment of the present disclosure, the data lines DL include a first type of data line DL1 and a second type of data line DL2 corresponding to the pixel circuit column group Z0, the first type of data line DL1 and the second type of data line DL2 are both electrically connected to the pixel driving circuit 11, and the first type of data line DL1 is also electrically connected to the selection circuit 30; along the first direction D1, the first type of data line DL1 and the second type of data line DL2 are respectively located on opposite sides of the corresponding pixel circuit column group Z0, and the level transfer signal line X0 and the second type of data line DL2 corresponding to the pixel driving circuit column group Z0 in the same column as the shift register circuit are located in the same spacing area Q0.

[0066] Optionally, combine Figure 5 , Fig. 9 and Fig.10, the display panel provided in the embodiment of the present disclosure is a Micro LED display panel, and the light-emitting element in the display panel is a Micro LED. The pixel driving circuit 11 is used to connect with the light-emitting element to drive the light-emitting element to emit light. The pixel driving circuit 11 includes a pulse width modulation circuit PWM and a pulse amplitude modulation circuit PAM (the specific structure of the pulse width modulation circuit PWM and the pulse amplitude modulation circuit PAM can refer to the existing structure, and the present disclosure does not specifically limit this), the pulse width modulation circuit PWM is electrically connected to the pulse amplitude modulation circuit PAM, and the output end of the pulse amplitude modulation circuit PAM is electrically connected to the light-emitting element to provide a driving current to the light-emitting element; the pulse amplitude modulation circuit PAM is configured to control the amplitude of the driving current, and the pulse width modulation circuit PWM is configured to control the pulse width of the driving current; wherein, the pulse width of the driving current is understood as the duration of the driving current, and the amplitude of the driving current is understood as the current value of the driving current. The first type of data line DL1 mentioned in this embodiment is a signal line for transmitting a data signal to the pulse width modulation circuit PWM, and the second type of data line DL2 is a signal line for transmitting a data signal to the pulse amplitude modulation circuit PAM. In order to achieve uniform arrangement of signal lines, the first type of data lines DL1 and the second type of data lines DL2 are respectively arranged on both sides of the pixel driving circuit 11 along the first direction D1. Optionally, the second type of data lines DL2 are global signal lines. For example, the second type of data lines DL2 that provide data signals to the light-emitting elements of the same color are electrically connected, so there is no need to introduce a gating circuit 30 for the second type of data lines DL2. The first type of data lines DL1 are connected to the gating circuit 30 on the side of the pixel driving circuit array 10 facing the edge B of the display panel. When connected, the first part X1 of the first type of data lines DL1 is wound to the top of the gating circuit 30 through the second part X2 and is electrically connected to the gating circuit 30. The level transmission signal line X0 is electrically connected to the second shift register 22 through the winding part X02. If the level transmission signal line X0 and the first type of data line DL1 are arranged in the same interval, the second part X2 of the first type of data line DL1 will interfere with the winding part X02 of the level transmission signal line X0, and the line needs to be changed to achieve electrical connection with the second shift register 22. In this embodiment, when the level transfer signal line X0 and the second type data line DL2 are arranged in the same spacing area Q0 on one side of the pixel driving circuit 11, the second portion X2 in the first type data line DL1 and the winding portion X02 in the level transfer signal line X0 do not interfere with each other, which is more conducive to simplifying the wiring of the first type data line DL1 and the level transfer signal line X0.

[0067] Please continue to refer to Figure 8 and Fig.10 In an optional embodiment of the present disclosure, Figure 8 and Fig.10Taking the pixel driving circuit column group Z0 on the left as an example, the shift register circuit and the pixel driving circuit column group Z0 are located in the same column. When the level transfer signal line X0 and the second type of data line DL2 are set in the same spacing area Q0, the second type of data line DL2 is located between the level transfer signal line X0 and the first signal line 51.

[0068] This embodiment defines the relative position relationship of the level transfer signal line X0, the first signal line 51 and the second type of data line DL2 when they are simultaneously arranged in the same spacing area Q0. It should be noted that the spacing area Q0 mentioned in this embodiment is the spacing area Q0 located on both sides of the same shift register circuit 20 and adjacent to the shift register circuit 20, and is also the spacing area Q0 located on both sides of the same pixel circuit column group Z0 and adjacent to the pixel circuit column group Z0. The above-mentioned level transfer signal line X0 and the first signal line 51 are both connected to the shift register circuit 20, and the second type of data line DL2 is electrically connected to the pixel driving circuit 11. In this embodiment, the level transfer signal line X0 is closest to the shift register circuit 20, and the second type of data line DL2 is located between the level transfer signal line X0 and the first signal line 51, and the first signal line 51 is farthest from the shift register circuit 20. In this way, it is more convenient to wire the level transfer signal line X0 used to connect the first shift register 21 and the second shift register 22, avoiding winding. At the same time, when the winding portion X02 in the level transfer signal line X0 and the first signal line 51 are extended to the bridge portion K02 of the selection control line K, the level transfer signal line X0 and the first signal line 51 will not interfere with each other, which is beneficial to reduce the difficulty of wiring.

[0069] In an optional implementation of the present disclosure, please combine Figure 8 and Fig.10 In the same switch element group 31, the input ends of different switch elements T are connected to the same input line 60. Along the direction perpendicular to the light emitting surface of the display panel, the input lines 60 corresponding to at least some of the switch element groups 31 overlap with the bridge portion K02 of the selection control line K, and the input line 60 and the main body K01 of the selection control line K are arranged on the same layer.

[0070] In order to facilitate the connection between the data line DL and the switch elements in the switch element group 31 and avoid the data line DL from changing lines, in the gating circuit 30 provided by the present disclosure, the switch elements are located between the pixel driving circuit array 10 and the gating control line K, and the input ends of the switch elements in the same switch element group 31 are electrically connected to the same input line 60, which is used to be electrically connected to the binding pad P1 in the display panel. The binding pad P1 is usually arranged on the side of the gating circuit 30 away from the pixel driving circuit array 10. Therefore, when the input line 60 is electrically connected to the binding pad P1, the input line 60 will pass through the gating control line K. In this embodiment, please refer to Figure 8 and Fig.10The input line 60 corresponding to the switch element group 31 on the left side is arranged in the same layer as the main body K01 of the gate control line K, and the input line 60 is arranged to pass through the gate control line K from the position of the bridge portion K02. At this time, the input line 60 does not need to be replaced, which is conducive to simplifying the wiring process of the input line 60. In addition, the input line 60 can be arranged in the second metal layer M2 of the display panel to reduce the impedance and signal transmission voltage drop of the input line 60, and improve the signal transmission rate on the input line 60.

[0071] When the first shift register 21 is introduced into the area where the pixel circuit array is located, the first signal line 51 connected to the shift register circuit 20 and the stage transfer signal line X0 are set in the interval area Q0 adjacent to the first shift register 21. In order to avoid the interference of the gate control line K in the gate circuit 30 with these signal lines, a bridge portion K02 is introduced into the gate control line K, and the above signal line passes through the gate control line K at the position of the bridge portion K02. For the input line 60 connected to the switch element in the gate circuit 30, if the gate control line K in the area is provided with a bridge portion K02, the input line 60 can pass through the gate control line K from the position of the bridge portion K02. Considering that the gate circuit 30 is provided on the side of each pixel circuit column group Z0 facing the edge B of the display panel, and the shift register circuit 20 is only provided at the position corresponding to the individual pixel circuit column group Z0, the bridge portion K02 of the gate control line K is not introduced between each adjacent switch element group 31, for example Figure 8 and Fig.10 In the embodiment shown, the position corresponding to the pixel driving circuit column group Z0 on the right is not provided with a shift register circuit. In the switch element group 31 corresponding to the pixel driving circuit column Z0, in the area corresponding to the input line 60, when no bridge portion is provided on the gate control line K, the input line 60 can also be switched when passing through the bridge portion K02. For example, please refer to Fig.10 The input line 60 corresponds to the switch element group 31 on the right. At this time, in the same switch element group 31, the input ends of different switch elements are connected to the same input line 60. Along the direction perpendicular to the light emitting surface of the display panel, at least part of the input lines 60 corresponding to the switch element groups 31 overlap with the main body K01 of the selection control line K to form a second overlapping area Q2. In the second overlapping area Q2, the input line 60 and the bridge part K02 of the selection control line K are arranged on the same layer.

[0072] This embodiment shows that when the input line 60 of the switching element group 31 passes through the enable control line K, and the bridge portion K02 is not set at the position corresponding to the enable control line K, the input line 60 can be set to overlap with the main portion K01 of the enable control line K. In the second overlapping area Q2 formed by the overlap of the two, the input line 60 and the main portion K01 of the enable control line K are set in different layers, and the input line 60 can be set in the same layer as the bridge portion K02 in other areas on the enable control line K, so as to reasonably utilize the existing film layer in the display panel to avoid interference between the input line 60 and the enable control line K.

[0073] Fig.12 and Fig.13 8 and 9 are another relative position relationship diagrams of the switch element group 31 and the gate control line K in the gate circuit 30 provided in the embodiment of the present disclosure, please refer to FIG. Fig.12 and Fig.13 In an optional embodiment of the present disclosure, the line width of the main body K01 in the second overlapping area Q2 is less than or equal to its line width in other areas; and / or, the main body K01 also includes a first opening 91, and the first opening 91 is at least located in the second overlapping area Q2 along a direction perpendicular to the plane where the display panel is located.

[0074] When the input line 60 is overlapped with the main part K01 of the gate control line K by changing the line, Fig.12 The embodiment shown shows a scheme of narrowing the width of the line segment of the main body K01 located in the second overlapping area Q2, so that the overlapping area of ​​the input line 60 and the gate control line K in the second overlapping area Q2 can be reduced, thereby facilitating the reduction of the coupling capacitance between the two, and reducing or avoiding the interference of the coupling capacitance on the signals on the input line 60 and the gate control line K. In addition, it is also possible to adopt Fig.13 In the embodiment shown, a first opening 91 is formed on the line segment of the main body K01 located in the second overlapping region Q2, so that the first opening 91 overlaps with the input line 60, which can also reduce the actual overlapping area between the input line 60 and the gate control line K, and thus is also conducive to reducing the coupling capacitance between the two. It should be noted that in order to further reduce the coupling capacitance between the input line 60 and the gate control line K, in the second overlapping region Q2, while narrowing the line width of the main body K01, the first opening 91 can also be formed on the main body K01 with a narrower line width, for example Fig.13 The scheme shown.

[0075] Please continue to refer to Fig.12 and Fig.13In an optional embodiment of the present disclosure, the gate of the switching element is electrically connected to the selection control line K through the gate connection line 70, and the gate connection line 70 extends along the second direction D2; along the direction perpendicular to the plane where the light emitting surface of the display panel is located, at least one gate connection line 70 overlaps with the main body K01 to form a third overlapping area Q3; the line width of the main body K01 in the third overlapping area Q3 is less than or equal to its line width in other areas; and / or, the main body K01 also includes a second opening 92, and along the direction perpendicular to the plane where the display panel is located, the second opening 92 is at least located in the third overlapping area Q3.

[0076] Please combine Figure 1 , Figure 2 , Fig.12 and Fig.13 In order to facilitate the connection between the switch element in the gating circuit 30 and the data line DL and avoid the risk of short circuit or disconnection caused by the data line DL changing, the switch element group 31 in the gating circuit 30 is arranged on the side of the gating control line K facing the pixel driving circuit array 10 in the embodiment of the present disclosure. Considering that the gate of the switch element in the switch element group 31 is connected to the gating control line K, Fig.12 For example, three switch elements in the same switch element group 31 are electrically connected to three gate control lines K respectively, and the three gate control lines K are arranged along the second direction D2. When the switch element is connected to the gate control line K that is not adjacent to the switch element, the gate connection line 70 will pass through one or two other gate control lines K, and overlap with other gate control lines K to form a third overlapping area Q3. The gate connection line 70 and the gate of the switch element can be set in the same layer, so that the gate connection line 70 and the main body K01 of the gate control line K are located in different film layers. In this way, the gate connection line 70 can be electrically connected to the corresponding gate control line K without changing the line, which is beneficial to simplify the wiring complexity of the gate connection line 70.

[0077] Considering that when the gate connection line 70 overlaps with the gate control line K, a coupling capacitor may be generated between the gate connection line 70 and the gate control line K, causing signal interference, the line width of the main body K01 of the gate control line K can be reduced in the third overlapping area Q3. Fig.12 and Fig.13 , so as to reduce the actual overlapping area between the gate connection line 70 and the gate control line K, thereby reducing the coupling capacitance between the two. Fig.13, a second opening 92 may be formed on the main body K01 of the third overlapping region Q3, so that the second opening 92 overlaps the gate connection line 70, which can also reduce the actual overlapping area between the gate connection line 70 and the gate control line K, and reduce the coupling capacitance between the two. Alternatively, in the third overlapping region Q3, while reducing the line width of the main body K01, the second opening 92 is formed on the main body K01, which is more conducive to reducing the actual overlapping area between the gate connection line 70 and the gate control line K, and reducing or avoiding signal interference between the two.

[0078] Optionally, the gate connection line 17 can be wired on the left side of the corresponding transistor along the first direction to achieve electrical connection with the selection control line K, or can be wired on the right side of the corresponding transistor along the first direction to achieve electrical connection with the selection control line K, which is not specifically limited in the present disclosure.

[0079] Fig.14 The figure shows a layout diagram of the gate control line K and the first signal line 51 overlapping with it. When the gate control line K extending along the first direction D1 overlaps with the first signal line 51 extending along the second direction D2, at this time, the first signal line 51 can be arranged in the same layer as the main body K01 of the gate control line K, and overlap with the bridge part K02 of the gate control line K. In order to reduce the signal interference between the two, the line width of the first signal line 51 can be reduced in the overlapping area of ​​the two, so that the line width of the first signal line 51 in the overlapping area is smaller than the line width in other areas. It should be noted that Fig.14 Only the signal line overlapping with the gate control line K is the first signal line 51 as an example for description. In some other embodiments of the present disclosure, when the signal line overlapping with the gate control line K is other signal lines, the same method as shown in FIG. Fig.14 The above-mentioned design reduces the line width of the signal line extending along the second direction D2 in the overlapping area.

[0080] It should also be noted that when the main body K01 and the bridge K02 are introduced on the gate control line, the main body K01 and the bridge K02 located in different film layers can be electrically connected through one or more connection holes LK. When there are multiple connection holes LK, for example, please refer to Fig.14 , multiple connection holes LK are equivalent to being connected in parallel, which is beneficial to reducing the overall impedance of the selection control line K.

[0081] Please refer to Figure 1 and Figure 2 , and combined with Figure 8In an optional embodiment of the present disclosure, the pixel driving circuit array 10 includes a plurality of pixel circuit column groups Z0 arranged along a first direction D1, the pixel circuit column group Z0 includes at least two pixel circuit columns, and there is a spacing area Q0 between adjacent pixel circuit column groups Z0; along the second direction D2, the shift register circuit 20 and the gating circuit 30 both overlap with the pixel circuit column group Z0, the first direction D1 and the second direction D2 intersect, and the second direction D2 is the direction from the pixel driving circuit array 10 to the second shift register 22.

[0082] In the embodiment of the present disclosure, the first shift register 21 in the shift register circuit 20 is set in the area where the pixel drive circuit array 10 is located. Generally, the display area includes the area where the aforementioned pixel drive circuit array 10 is located, so it is equivalent to setting at least most of the shift registers in the shift register circuit 20 in the display area, without occupying the space of the border area of ​​the display panel, which is conducive to realizing the narrow border or borderless design of the display panel. When the shift register circuit 20 and the gating circuit 30 are introduced into the display panel, the present disclosure sets the shift register circuit 20 and the gating circuit 30 to overlap with the pixel circuit column group Z0 along the second direction D2, specifically, the shift register in the shift register circuit 20 and the switch element group 31 in the gating circuit 30 overlap with the pixel circuit column group Z0, so that the space occupied by the shift register or the switch element group 31 in the spacing area Q0 between the pixel circuit column groups Z0 can be reduced, and the shift register or the switch element group 31 can be prevented from affecting the original wiring structure in the spacing area Q0.

[0083] Please refer to Figure 8 In an optional embodiment of the present disclosure, along the second direction D2, the first shift register 21 and the second shift register 22 do not overlap with the spacing area Q0. In this way, the first shift register 21 does not occupy the space of the spacing area Q0 between the column groups of the pixel driving circuit 11, and the second shift register 22 does not occupy the space in the extension direction of the spacing area Q0, and thus does not affect the original wiring structure of the spacing area Q0.

[0084] Fig.15 FIG. 1 is another planar structure diagram of the display panel provided in the embodiment of the present disclosure, please refer to FIG. Fig.15 In an optional embodiment of the present disclosure, the display panel includes an electrostatic protection circuit 70, which is located on the side of the pixel driving circuit array 10 facing the edge B of the display panel, and at least part of the electrostatic protection circuit 70 is electrically connected to the second shift register 22. It should be noted that Fig.15 Only the electrostatic protection circuit 70 connected to the second shift register 22 is shown. In fact, other electrostatic protection circuits 70 may be provided on the side of the pixel driving circuit array 10 facing the edge B of the display panel. Figure 5, and electrically connected to other signal lines that require electrostatic protection, etc., which is not specifically limited in the present disclosure.

[0085] This embodiment shows a solution of introducing an electrostatic protection circuit 70 on the side of the pixel driving circuit array 10 facing the edge B of the display panel. The electrostatic protection circuit 70 is arranged on the side of the display panel close to its edge, and is used to connect with some signal lines in the display panel close to its edge position to avoid static electricity from affecting the display panel. For example, part of the electrostatic protection circuit 70 can be electrically connected to the output end of the second shift register 22, so as to avoid static electricity from affecting the shift register circuit 20. It should be noted that the electrostatic protection circuit 70 can adopt the structure in the relevant technology, and this disclosure does not specifically limit this.

[0086] Fig.16 FIG. 1 is a layout diagram of a pixel driving circuit array 10 in a display panel provided by an embodiment of the present disclosure, which is located on the side of an edge B of the display panel. It should be noted that: Fig.16 Only some of the film layers in the display panel are shown, not all of the film layers are shown. Fig.16 In an optional embodiment of the present disclosure, the display panel further includes a second signal line 52 disposed between the electrostatic protection circuit 70 and the pixel driving circuit array 10. On the side of the pixel driving circuit array 10 facing the edge B of the display panel, the second signal line 52 extends in the first direction D1 as a whole, and a broken line appears in a partial area. For example, the second signal line 52 includes a first line segment 521, a connecting line segment 520, and a second line segment 522 that are electrically connected in sequence and disposed in the same layer. The first line segment 521 and the second line segment 522 both extend along the first direction D1, and the connecting line segment 520 extends along the second direction D2. The first direction D1 and the second direction D2 intersect; along the first direction D1, at least part of the first line segment 521 and the connecting line segment 520 overlap with the second shift register 22, and the second line segment 522 does not overlap with the second shift register 22.

[0087] Optionally, the second signal line 52 includes a power signal line for providing a power signal to the electrostatic protection circuit, and may also include a detection signal line for connecting the second shift register circuit and the test pad. The power signal line can also be used to provide a power signal to the pixel driving circuit, that is, the power signal of the electrostatic protection circuit can be multiplexed with the power signal of the pixel driving circuit. It should be noted that Fig.16 Only the wiring structure of the second signal line 52 is illustrated, and the actual number of the second signal lines 52 is not limited. In this embodiment, when the second signal lines 52 are arranged on the side of the pixel driving circuit array facing the edge B of the display panel, compared with the method of setting the second signal lines 52 as straight lines, the space on both sides of the second shift register 22 along the first direction D1 is reasonably utilized. For example, please refer to Fig.16 and Fig.17 , Fig.17 The reference layout diagram of the pixel driving circuit array facing the edge B of the display panel is shown. The gating circuit 30 is located on the side of the shift register circuit 20 facing the edge of the display panel. The gating control line and the second signal line 52 are both located on the side of the switch element group 31 facing the edge B of the display panel. The gating control line and the second signal line 52 are both straight line structures extending along the first direction D1. The space occupied by the two as a whole is relatively large. When the minimum distance d0 between the second signal line 52 and the edge B of the display panel is fixed, Fig.17 In the wiring method, the electrostatic protection circuit 70 is arranged on the side of the second signal line 52 toward the edge B of the display panel, so that the distance d2 between the electrostatic protection circuit 70 and the edge B of the display panel is small. When cutting to form the display panel, the risk of the transistor in the electrostatic protection circuit 70 being damaged by the cutting laser is increased. In the embodiment of the present disclosure, the arrangement of the gating circuit 30 and the second shift register 22 is adjusted, and the second shift register 22 is set on the side of the gating control line K in the gating circuit 30 facing the edge B of the display panel. On the side of the gating control line K facing the edge B of the display panel, the second shift registers 22 are arranged along the first direction D1, and there is a spacing space between adjacent second shift registers 22. This part of the spacing space can be used to layout part of the line segments in the second signal line 52. For example, moving the first line segment 521 and the connecting line segment 520 to this part of the space is equivalent to moving part of the line segments of the second signal line 52 upward. When the line segments of the first signal line 52 are moved upward, the electrostatic protection circuit 70 located on the side of the second signal line 52 facing the edge B of the display panel also has space to move upward. In this way, when the minimum distance between the second signal line 52 and the edge B of the display panel is fixed to d0, the distance d1 between at least part of the electrostatic protection circuit 70 and the edge B of the display panel can also be increased, so that d1>d2, which is beneficial to reduce the risk of transistors in this part of the electrostatic protection circuit 70 being damaged by cutting laser.

[0088] It should be noted that the distances between different electrostatic protection circuits 70 and the edge B of the display panel can be set to be different, and the distances between different electrostatic protection circuits 70 and the edge B of the display panel can be adjusted according to actual wiring conditions, and the present disclosure does not make specific limitations on this.

[0089] Please continue to refer to Fig.15In an optional embodiment of the present disclosure, the pixel driving circuit array 10 includes a plurality of pixel circuit column groups Z0 arranged along a first direction D1, the pixel circuit column group Z0 includes at least two pixel circuit columns, and there is a spacing area Q0 between adjacent pixel circuit column groups Z0; along the second direction D2, at least part of the electrostatic protection circuit 70 overlaps with the pixel circuit column group Z0 and does not overlap with the spacing area Q0; the first direction D1 and the second direction D2 intersect, and the second direction D2 is the direction of the pixel driving circuit array 10 pointing to the second shift register 22.

[0090] Taking into account that part of the signal lines arranged in the spacing area between the pixel circuit column groups Z0 need to extend to the edge area B of the display panel and be electrically connected to the binding pad P1, this part of the signal lines is equivalent to penetrating most of the length direction of the display panel along the second direction D2. When the electrostatic protection circuit 70 is introduced on the side of the edge B of the display panel facing the pixel driving circuit array 10, the embodiment of the present disclosure arranges at least part of the electrostatic protection circuit 70 along the second direction D2 so that it does not overlap with the spacing area Q0, but arranges the electrostatic protection circuit 70 directly below the pixel driving circuit 11 column group. In this way, this part of the electrostatic protection circuit 70 will not occupy the space in the extension direction of the spacing area Q0, thereby avoiding the interference of the electrostatic protection circuit 70 with the signal lines in the spacing area that originally need to extend to the edge area B of the display panel and be electrically connected to the binding pad P1, and avoiding the need for this part of the signal lines to bypass the electrostatic protection circuit 70 for winding, which is beneficial to simplify the wiring process of the signal lines in the spacing area Q0.

[0091] Fig.18 FIG. 1 is a schematic diagram showing a layout of a light emitting element LD in an embodiment of the present disclosure. Fig.19 The following is a partial layout diagram of the display panel. Fig.18 and Fig.19 In an optional embodiment of the present disclosure, the display panel further includes a light emitting element LD electrically connected to the pixel driving circuit 11. Optionally, the light emitting elements LD are evenly arranged in the display panel, and at least part of the light emitting elements LD are located on the side of the pixel driving circuit array 10 facing the edge B of the display panel. It should be noted that Fig.18 Only one arrangement of the light emitting elements LD in the display panel is given as an example, and the number of light emitting elements LD actually included in the display panel and the relative position relationship and quantity correspondence between the light emitting elements LD and the pixel driving circuit are not limited. It should also be noted that the light emitting elements may include a variety of different colors, such as red light emitting elements, green light emitting elements, and blue light emitting elements, etc., and the present disclosure does not limit this.

[0092] In the display panel, the area where the light-emitting element LD is arranged can be regarded as the display area. When the light-emitting element LD is arranged on the side of the edge B of the pixel driving circuit array 10 facing the display panel, it means that the side of the edge B of the pixel driving circuit array 10 facing the display panel also belongs to a part of the display area. Such arrangement is conducive to increasing the proportion of the display area in the display panel, improving the screen-to-body ratio of the display panel, and realizing the extremely narrow frame or even frameless design of the display panel. Since the pixel driving circuit 11 connected to the light-emitting element LD is located in the area where the pixel driving circuit array 10 is located, the light-emitting element LD located on the side of the edge B of the pixel driving circuit array 10 facing the display panel can be electrically connected to the corresponding pixel driving circuit 11 through a signal line led from the pixel driving circuit array 10 to the outside of the pixel driving circuit array 10.

[0093] Please continue to refer to Fig.18 and Fig.19 In an optional embodiment of the present disclosure, at least part of the light emitting element LD overlaps with the gating circuit 30 in a direction perpendicular to the plane where the display panel is located. In the direction perpendicular to the plane where the display panel is located, it is equivalent to setting the light emitting element LD on the side of the light emitting surface of the gating circuit 30 facing the display panel, and the area where this part of the light emitting element LD is located is reused with the area where the gating circuit 30 is located, which is conducive to the reasonable use of the space of the display panel to layout the light emitting element LD and improve the space utilization rate of the display panel. In addition, since the area where this part of the light emitting element LD is located is reused with the area where the gating circuit 30 is located, it is equivalent to setting the gating circuit 30 in the display area of ​​the display panel, avoiding the gating circuit 30 occupying the space of the non-display area, which is conducive to realizing an extremely narrow frame or a frameless design of the display panel.

[0094] Please continue to refer to Fig.18 and Fig.19 In an optional embodiment of the present disclosure, the display panel further includes an electrostatic protection circuit 70 disposed on a side of the pixel driving circuit array 10 facing the edge B of the display panel, and at least part of the light emitting elements LD are located on the side of the electrostatic protection circuit 70 facing the edge B of the display panel. This embodiment shows a solution of disposing the light emitting elements LD on a side of the electrostatic protection circuit 70 away from the pixel driving circuit array 10, which is equivalent to disposing the light emitting elements LD in the area close to the lower edge of the display panel. In this way, the electrostatic protection circuit 70 is also integrated in the display area, does not occupy the space of the non-display area, and is also conducive to realizing an extremely narrow frame or a frameless design of the display panel.

[0095] Please combine Fig.11 and Fig.18In an optional embodiment of the present disclosure, the display panel further includes a first electrode P01 and a second electrode P02 electrically connected to the light emitting element LD; along a direction perpendicular to the light emitting surface of the display panel, the first electrode P01 and the second electrode P02 are located on the side of the pixel driving circuit 11 facing the light emitting surface of the display panel. Among them, the first electrode P01 is used to be electrically connected to the pixel driving circuit 11, and the second electrode P02 is electrically connected to a constant level signal line. When the pixel driving circuit 11 provides a driving current to the first electrode P01, the corresponding light emitting element LD can be driven to emit light. Optionally, the first electrode P01 and the second electrode P02 can be located in the same film layer of the display panel, or can be set in different layers of the display panel according to actual conditions, and the present disclosure does not specifically limit this. When the light emitting element LD is not located directly above the corresponding pixel driving circuit 11, the pixel driving circuit 11 and the first electrode P01 can be electrically connected through a signal line.

[0096] Based on the same inventive concept, the present disclosure also provides a display device, Fig. 20 FIG. 1 is a schematic diagram of a structure of a display device provided in an embodiment of the present disclosure. Please refer to FIG. Fig. 20 , the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in the embodiment of the present disclosure can be any electronic device with display function, such as a tablet computer with touch and display functions, a display product in a display cabinet, a television, or a vehicle-mounted display device, and is particularly suitable for display devices with extremely narrow borders or no borders. The display device 200 provided in the embodiment of the present disclosure has the beneficial effects of the display panel 100 provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel 100 in the above embodiments, and this embodiment will not be repeated here.

[0097] Understandably, Fig. 20 Only a rectangular structure is used to illustrate the display device. In some other embodiments of the present disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and the present disclosure does not specifically limit this.

[0098] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0099] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It includes a pixel driving circuit array, a shift register circuit and a gating circuit, as well as a pixel driving line and a data line, wherein the pixel driving circuit array includes a plurality of pixel driving circuits; The pixel driving line and the data line are electrically connected to the pixel driving circuit respectively, the pixel driving line is used to transmit a control signal to the pixel driving circuit, and the data line is used to transmit a data signal to the pixel driving circuit; The shift register circuit is configured to transmit the control signal to the pixel driving line, and the gating circuit is configured to transmit the data signal to the data line; The shift register circuit includes a plurality of cascaded shift registers, and the shift register includes a plurality of cascaded first shift registers and a second shift register cascaded with the first shift register, the first shift register is located in the area where the pixel driving circuit array is located, and the second shift register is located on the side of the pixel driving circuit array facing the edge of the display panel; the gating circuit is located between the pixel driving circuit array and the second shift register.

2. The display panel according to claim 1, characterized in that: The output end of the first shift register is electrically connected to the pixel driving circuit through the pixel driving line. The display panel further includes a binding pad, and the output end of the second shift register is electrically connected to the binding pad.

3. The display panel according to claim 2, characterized in that: The display panel further includes a test signal line, and the output end of the second shift register is also electrically connected to the test signal line.

4. The display panel according to claim 1, characterized in that: The gating circuit includes a plurality of switch element groups, each of which includes at least two switch elements, and the output end of each switch element is electrically connected to the data line; The data line includes a first portion and a second portion that are electrically connected, the first portion is at least located in the area where the pixel driving circuit array is located, the second portion is located on a side of the edge of the pixel driving circuit array facing the display panel, the first portion is electrically connected to the switching element through the second portion, and the first portion and the second portion are arranged on the same layer.

5. The display panel according to claim 4, characterized in that: The gating circuit includes at least two gating control lines. In the same switching element group, the gates of different switching elements are connected to different gating control lines. The gating control line extends along a first direction, the first part extends along a second direction, and the first direction and the second direction intersect; along the second direction, the switching element group is located between the gating control line and the pixel driving circuit array.

6. The display panel according to claim 5, characterized in that: The line width of the gate control line is greater than the line width of the first portion.

7. The display panel according to claim 5, characterized in that: The second shift register is electrically connected to the first shift register through a level transfer signal line. Along a direction perpendicular to the plane where the display panel is located, the level transfer signal line overlaps with the selection control line to form a first overlapping area. In the first overlapping area, the level transfer signal line and the selection control line are arranged in different layers.

8. The display panel according to claim 7, characterized in that: The selection control line includes a main body and a bridge portion connected to the main body, the main body and the bridge portion are arranged in different layers and both extend along the first direction, the bridge portion is at least partially located in the first overlapping area, and the level transfer signal line is arranged in the same layer as the main body.

9. The display panel according to claim 8, characterized in that: The display panel includes a substrate and a first metal layer and a second metal layer arranged on the substrate, the resistivity of the second metal layer is smaller than the resistivity of the first metal layer, the main body of the selection control line and the level transfer signal line are located in the second metal layer, and the bridge portion of the selection control line is located in the first metal layer.

10. The display panel according to claim 8, characterized in that: Along the first direction, the bridge portion is located between adjacent switch element groups; along the second direction, the second shift register and the switch element groups overlap; Along the first direction, the stage transfer signal line connected to the second shift register is located on the same side of the second shift register and the switch element group corresponding to the second shift register.

11. The display panel according to claim 10, characterized in that: The level transfer signal line includes a main portion and a winding portion electrically connected to the main portion, the main portion is located in the area where the pixel driving circuit array is located, along the second direction, the winding portion is located on a side of the pixel driving circuit array facing the edge of the display panel, and the winding portion is electrically connected to the second shift register; The main part extends along the second direction, and the winding part includes a first winding, a connecting part and a second winding which are electrically connected in sequence, the first winding and the second winding extend along the first direction, the connecting part extends along the second direction, the first winding is connected to the main part, and the second winding is connected to the second shift register.

12. The display panel according to claim 8, characterized in that: The pixel driving circuit array includes a plurality of pixel circuit column groups arranged along the first direction, the pixel circuit column groups include at least two pixel circuit columns, there is a spacing area between adjacent pixel circuit column groups, and along the second direction, the bridge portion overlaps the spacing area.

13. The display panel according to claim 12, characterized in that: The display panel also includes a plurality of first signal lines extending along the second direction, the first signal lines being configured to provide signals to the shift register circuit; the first signal lines are located on at least one side of the shift register circuit along the first direction and in the spacing area; along a plane perpendicular to the light emitting surface of the display panel, the first signal lines overlap with the bridge portion and do not overlap with the main body portion; the first signal lines are arranged on the same layer as the main body portion.

14. The display panel according to claim 13, characterized in that: The stage transfer signal line is located in the spacing area and is located on a side of the first signal line facing the shift register circuit.

15. The display panel according to claim 13, characterized in that: The data lines include a first type of data lines and a second type of data lines corresponding to the pixel circuit column group, the first type of data lines and the second type of data lines are both electrically connected to the pixel driving circuit, and the first type of data lines are also electrically connected to the selection circuit; along the first direction, the first type of data lines and the second type of data lines are respectively located on opposite sides of the corresponding pixel circuit column group, and the level transfer signal line and the second type of data line are located in the same said spacing area.

16. The display panel according to claim 15, characterized in that: The second type data line is located between the level transfer signal line and the first signal line.

17. The display panel according to claim 8, characterized in that: In the same switching element group, input ends of different switching elements are connected to the same input line, and along the direction perpendicular to the light emitting surface of the display panel, the input lines corresponding to at least part of the switching element groups overlap with the bridge portion of the selection control line, and the input lines are arranged on the same layer as the main body of the selection control line.

18. The display panel according to claim 8, characterized in that: In the same switching element group, input ends of different switching elements are connected to the same input line. Along the direction perpendicular to the light emitting surface of the display panel, the input lines corresponding to at least part of the switching element group overlap with the main body of the selection control line to form a second overlapping area. In the second overlapping area, the input line and the bridge part of the selection control line are arranged on the same layer.

19. The display panel according to claim 18, characterized in that: The line width of the main body in the second overlapping area is less than or equal to its line width in other areas; and / or the main body also includes a first opening, and the first opening is at least located in the second overlapping area along a direction perpendicular to the plane where the display panel is located.

20. The display panel according to claim 8, characterized in that: The gate of the switching element is electrically connected to the selection control line through a gate connection line, and the gate connection line extends along the second direction; along a direction perpendicular to the plane where the light emitting surface of the display panel is located, at least one of the gate connection lines overlaps with the main body to form a third overlapping area; the line width of the main body in the third overlapping area is less than or equal to its line width in other areas; and / or the main body also includes a second opening, and along a direction perpendicular to the plane where the display panel is located, the second opening is at least located in the third overlapping area.

21. The display panel according to claim 1, characterized in that: The pixel driving circuit array includes a plurality of pixel circuit column groups arranged along a first direction, the pixel circuit column groups include at least two pixel circuit columns, and adjacent pixel circuit column groups have a spacing area; along a second direction, the shift register circuit and the gating circuit both overlap with the pixel circuit column groups, the first direction and the second direction intersect, and the second direction is the direction in which the pixel driving circuit array points to the second shift register.

22. The display panel according to claim 21, characterized in that: Along the second direction, the first shift register and the second shift register do not overlap with the spacing area.

23. The display panel according to claim 1, characterized in that: The display panel comprises an electrostatic protection circuit, which is located on a side of the pixel driving circuit array facing an edge of the display panel, and at least a part of the electrostatic protection circuit is electrically connected to the second shift register.

24. The display panel according to claim 23, characterized in that: The display panel further includes a second signal line disposed between the electrostatic protection circuit and the pixel driving circuit array, the second signal line including a first line segment, a connecting line segment, and a second line segment that are electrically connected in sequence and disposed in the same layer, the first line segment and the second line segment both extend along a first direction, the connecting line segment extends along a second direction, and the first direction and the second direction intersect; Along the first direction, at least part of the first line segment and the connecting line segment overlap with the second shift register, and the second line segment does not overlap with the second shift register.

25. The display panel according to claim 24, characterized in that: The second signal line includes a power signal line and at least one detection signal line. The power signal line is at least used to provide a power signal for the pixel driving circuit. The detection signal line is used to be electrically connected to the output end of the second shift register.

26. The display panel according to claim 24, characterized in that: The pixel driving circuit array includes a plurality of pixel circuit column groups arranged along a first direction, the pixel circuit column groups include at least two pixel circuit columns, and there is a spacing area between adjacent pixel circuit column groups; along a second direction, at least part of the electrostatic protection circuit overlaps with the pixel circuit column groups and does not overlap with the spacing area; the first direction and the second direction intersect, and the second direction is the direction of the pixel driving circuit array pointing to the second shift register.

27. The display panel according to claim 1, characterized in that: It also includes light-emitting elements electrically connected to the pixel driving circuit, and at least part of the light-emitting elements are located on a side of the pixel driving circuit array facing the edge of the display panel.

28. The display panel according to claim 27, characterized in that: Along a direction perpendicular to the plane where the display panel is located, at least a portion of the light emitting element overlaps with the gating circuit.

29. The display panel according to claim 27, characterized in that: It also includes an electrostatic protection circuit arranged on a side of the edge of the pixel driving circuit array facing the display panel, and at least part of the light-emitting elements are located on a side of the electrostatic protection circuit facing the edge of the display panel.

30. The display panel according to claim 27, characterized in that: It also includes a first electrode and a second electrode electrically connected to the light-emitting element; along a direction perpendicular to the light-emitting surface of the display panel, the first electrode and the second electrode are located on a side of the pixel driving circuit facing the light-emitting surface of the display panel.

31. A display device, characterized in that: The display panel comprises any one of claims 1 to 30.

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