Chip Memory

Abstract

The present disclosure relates to the field of semiconductor manufacturing equipment, and provides a chip storage device, including a handling device, a carrier and a control device. The clamping mechanism of the handling device includes a first clamping part and a second clamping part arranged in sequence along a first straight line direction. The first clamped part of the first chip box and the second clamped part of the second chip box are respectively located at a first position and a second position arranged in sequence along a second straight line direction on the carrier. When the control device controls the clamping mechanism to move to the target position, the first straight line direction and the second straight line direction coincide with each other as the same straight line direction, and the first clamping part and the second clamping part are respectively aligned with the first position and the second position along the same straight line direction, so that the first clamping part and the second clamping part can respectively clamp or release the first clamped part located at the first position and the second clamped part located at the second position. Accordingly, the control device only needs to follow the same set of control logic when controlling the handling device to carry the first chip box and the second chip box.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor production and manufacturing, and in particular to a chip memory. Background Art

[0002] Wafer storage is a commonly used equipment in wafer production and manufacturing. Wafer storage is usually equipped with a carrier, a transport device and a control device. The carrier is used to carry the wafer box storing the wafers, the transport device transports the wafer box, and the control device is used to control the transport device to transport the wafer box according to the control logic. However, a wafer box of one size can only store wafers of one size. When the wafer storage has production requirements for wafers of multiple sizes, wafer boxes of multiple sizes need to be configured accordingly. When a general wafer storage is used to transport wafer boxes of different sizes, a set of control logic needs to be developed for each size of wafer box, which increases the burden on technicians to develop and maintain the control logic and reduces production efficiency. Summary of the invention

[0003] In view of this, the present disclosure provides a wafer storage device to solve the problem that when the wafer storage device carries wafer boxes of different sizes, a set of control logic needs to be developed for each size of wafer box.

[0004] The chip storage device includes a transport device, a carrier and a control device.

[0005] The transport device includes a moving mechanism and a clamping mechanism. The moving mechanism is used to move the clamping mechanism. The clamping mechanism includes a first clamping portion and a second clamping portion arranged in sequence along a first straight line direction. The clamping mechanism can be switched between a clamping state and a release state. When the clamping mechanism is in the clamping state, the first clamping portion and the second clamping portion can clamp a first clamped portion of a first wafer box and a second clamped portion of a second wafer box, respectively. When the clamping mechanism is in the release state, the first clamping portion and the second clamping portion can release the first clamped portion and the second clamped portion, respectively.

[0006] The carrier includes a support platform, a first positioning portion, and a second positioning portion. The support platform is used to support either a first wafer box or a second wafer box. The first positioning portion is used to position the first wafer box on the support platform so that the first clamped portion is located at a first position. The second positioning portion is used to position the second wafer box on the support platform so that the second clamped portion is located at a second position. The first position and the second position are arranged in sequence along the second straight line direction.

[0007] The control device is used to control the moving mechanism to move the clamping mechanism between a plurality of positions including the target position, and is used to control the clamping mechanism to switch between a clamping state and a release state. When the clamping mechanism is located at the target position, the first linear direction and the second linear direction coincide with each other as the same linear direction, and the first clamping portion and the second clamping portion are respectively aligned with the first position and the second position along the same linear direction, so that the first clamping portion and the second clamping portion can respectively clamp or release the first clamped portion located at the first position and the second clamped portion located at the second position.

[0008] As a possible implementation, the clamping mechanism includes a pair of jaws. The pair of jaws are driven to move between a close position and a far position. The close position and the far position correspond to a clamping state and a release state, respectively. Each jaw has a first jaw portion and a second jaw portion arranged in sequence along a first straight line direction. The first clamping portion includes two first jaw portions, and the second clamping portion includes two second jaw portions. When the clamping mechanism is located at the target position, the first clamped portion located at the first position is between the two first jaw portions; the second clamped portion located at the second position is between the two second jaw portions.

[0009] As a possible implementation, the clamping mechanism further includes a base, and the two clamping jaws are supported on the base. The base, the two first clamping jaw parts and the two second clamping jaw parts are arranged in sequence along a first straight line direction. The first straight line direction is perpendicular to the up-down direction.

[0010] As a possible implementation manner, the width of the first clamped portion is smaller than the width of the second clamped portion, and the distance between the two first clamping jaw portions is smaller than the distance between the two second clamping jaw portions.

[0011] As a possible implementation, the first clamped portion includes two first side flanges, and the second clamped portion includes two second side flanges. The two first clamping jaw portions are respectively provided with two first narrow slots, and the two second clamping jaw portions are respectively provided with two second narrow slots. When a pair of clamping jaws are switched from a distant position to a close position, the two first narrow slots can respectively receive the two first side flanges to clamp the first wafer box, and the two second narrow slots can respectively receive the two second side flanges to clamp the second wafer box. When the two clamping jaws are switched from a close position to a distant position, the two first narrow slots can respectively separate from the two first side flanges to release the first wafer box, and the two first narrow slots can respectively separate from the two second side flanges to release the second wafer box.

[0012] As a possible implementation, a plane parallel to both the first straight line direction and the up-down direction is defined as a first symmetry plane. The two first side flanges are arranged symmetrically relative to the first symmetry plane, and the two second side flanges are arranged symmetrically relative to the first symmetry plane. A plane parallel to both the second straight line direction and the up-down direction is defined as a second symmetry plane, and a pair of clamping jaws are arranged symmetrically relative to the second symmetry plane. When the clamping mechanism is located at the target position, the first symmetry plane and the second symmetry plane overlap.

[0013] As a possible implementation, the size of the first wafer box in the second straight direction is D1, the size of the second wafer box in the second straight direction is D2, the distance between the first clamped part and the second clamped part in the second straight direction is D3, D1<D2, D3<D1.

[0014] As a possible implementation, the carrier includes a first convex portion and a second convex portion protruding from the upper surface of the support platform. The first convex portion and the second convex portion are arranged in sequence along the second straight line direction and are spaced from each other. The first convex portion has a first positioning surface facing the second convex portion, and the second convex portion has a second positioning surface facing the first convex portion. The first convex portion is provided with two third positioning surfaces on opposite sides of a third straight line direction perpendicular to the second straight line direction. The first positioning portion includes a first positioning surface, a second positioning surface, and two third positioning surfaces.

[0015] As a possible implementation, the carrier includes a third protrusion protruding from the upper surface of the supporting platform. The third protrusion and the second protrusion are spaced apart in the second straight line direction and are located on the side of the second protrusion facing away from the first protrusion. The third protrusion has a fourth positioning surface facing the second protrusion, and the second protrusion has a fifth positioning surface facing the third protrusion. Two sixth positioning surfaces are also provided on opposite sides of the first protrusion in the third straight line direction. The two sixth positioning surfaces are located on the inner side of the two third positioning surfaces in the third straight line direction, and are closer to the second protrusion than the two third positioning surfaces in the second straight line direction. The second positioning portion includes a fourth positioning surface, a fifth positioning surface and two sixth positioning surfaces.

[0016] As a possible implementation manner, the two sixth positioning surfaces are coplanar with two end surfaces of the second convex portion in the third straight line direction, and are coplanar with two end surfaces of the two third convex portions in the third straight line direction.

[0017] The control device of the chip storage provided in the present application only needs to follow the same set of control logic when controlling the transport device to transport the first chip box and the second chip box, which can reduce the burden of technical personnel on developing and maintaining the control logic and improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be viewed as limiting the scope.

[0019] It should be understood that the same or similar reference numerals are used in the drawings to indicate the same or similar elements.

[0020] It should be understood that the drawings are merely schematic and that the sizes and proportions of elements in the drawings are not necessarily accurate.

[0021] Figure 1 Schematic diagram of the structure of a wafer processing system according to an embodiment of the present disclosure.

[0022] Figure 2 FIG. 4 is a schematic diagram of the structure of a chip memory according to an embodiment of the present disclosure.

[0023] Figure 3 for Figure 2 Schematic diagram of the structure of the clamping mechanism of the chip storage.

[0024] Figure 4 FIG. 1 is a diagram showing a first wafer box and a second wafer box. Figure 2 Schematic diagram of the structure of the position of the chip storage on the carrier.

[0025] Figure 5 The figure shows the state of being at the target position and in the released state. Figure 3 Schematic diagram of the structure of the clamping mechanism.

[0026] Figure 6 for Figure 2 Schematic diagram of the structure of the carrier of the chip storage device.

[0027] Figure 7 for Figure 6 Schematic diagram of the structure of the carrier from another perspective.

[0028] Explanation of reference numerals: 10, chip memory; 100, transport device; 110, moving mechanism; 120, clamping mechanism; 121, first clamping portion; 122, second clamping portion; 123, clamping claw; 1231, first clamping claw portion; 12311, first slot; 1232, second clamping claw portion; 12321, second slot; 124, base; 200, carrier; 210, supporting platform; 220, first convex portion; 221, first positioning surface; 222, third positioning surface; 223, sixth positioning surface; 230, second convex portion; 231, second Positioning surface; 232, fifth positioning surface; 240, third convex portion; 241, fourth positioning surface; 300, control device; 400, first wafer box; 410, first clamped portion; 411, first side flange; 500, second wafer box; 510, second clamped portion; 511, second side flange; L1, first straight line direction; L2, second straight line direction; L3, third straight line direction; H, up and down direction; SP1, first symmetry plane; SP2, second symmetry plane; 1000, wafer processing system; 1100, processing unit; 1200, transmission unit. DETAILED DESCRIPTION

[0029] Numerous specific details will be listed below to provide an understanding of the structure, function, and use of the embodiments described in the specification and shown in the drawings. It is understood that the embodiments described and shown herein are non-limiting examples, so that it can be recognized that the specific structural and functional details disclosed herein may be representative and exemplary. Modifications and changes may be made to these embodiments without departing from the scope of the claims.

[0030] With the development of chip processing technology, the automation level of chip processing system is getting higher and higher. Figure 1 As shown, the wafer processing system 1000 includes a processing unit 1100, a transmission unit 1200 and a wafer storage 10. The processing unit 1100 refers to a cluster of related equipment for one or more processes in the wafer processing process, that is, the wafer can complete the corresponding processing process after passing through the corresponding processing unit 1100. In a wafer processing system 1000, one or more processing units 1100 can be set according to actual needs, and the wafer can be transmitted between multiple processing units 1100 through the transmission unit 1200. Considering that the processing rates of each processing unit 1100 may be different, the wafers to be entered into the processing unit 1100 from the transmission unit 1200 and the wafers to be entered into the transmission unit 1200 from the processing unit 1100 can be stored in the wafer storage 10.

[0031] In the wafer storage 10, the storage and transportation of wafers are inseparable from the wafer box. The main function of the wafer box is to simplify the wafer transportation process and reduce the risk of wafer contamination as much as possible. In order to store and transport the wafer box, the wafer storage 10 is provided with a handling device 100, a carrier 200 and a control device 300. The carrier 200 is used to carry the wafer box. The handling device 100 can carry the wafer box placed on the carrier 200 to achieve the purpose of transporting the wafer box. The handling device 100 includes a clamping mechanism 120 and a moving mechanism 110. The clamping mechanism 120 is used to clamp the wafer box. Specifically, a clamped portion is provided on the wafer box, and the clamping mechanism 120 clamps the wafer box by clamping the clamped portion on the wafer box. The moving mechanism 110 is used to move the clamping mechanism 120 to move the wafer box clamped by the clamping mechanism 120. The control device 300 can control the transport device 100, and through a certain control logic, the transport device 100 can transport the wafer box according to a preset path and method. The control logic of the control device 300 can include, for example, the target position of the transport device 100, the moving path and method of the moving mechanism 110, and the clamping method of the clamping mechanism 120.

[0032] According to relevant standards, wafers have different sizes such as 6 inches and 8 inches, and wafer boxes also have different sizes to accommodate wafers of corresponding sizes. A wafer box of a single size can only accommodate wafers of a single size, for example, a 6-inch wafer box can only accommodate 6-inch wafers, and an 8-inch wafer box can only accommodate 8-inch wafers. Since an 8-inch wafer is larger than a 6-inch wafer, the size of a wafer box for accommodating an 8-inch wafer is usually larger than a wafer box for accommodating a 6-inch wafer. When the wafer storage device 10 needs to process wafers of different sizes, wafer boxes of different sizes need to be configured accordingly.

[0033] However, one type of carrier 200 can usually only carry one size of wafer box, and one type of clamping mechanism 120 can also only clamp one type of wafer box. Wafer boxes of different sizes need to be carried by different types of carriers 200 and clamped by different types of clamping mechanisms. In order to realize the storage and transmission of wafers of different sizes in the same wafer storage 10, some technicians will set different types of carriers 200 and different types of clamping mechanisms 120 in the same wafer storage 10. Doing so not only increases the cost of the wafer storage 10 in terms of hardware, but also requires the development of different control logics for wafer boxes of different sizes in terms of software. For example, one control logic needs to be developed for a 6-inch wafer box, and another control logic needs to be developed for an 8-inch wafer box, so that the control device 300 can carry two different sizes of wafer boxes according to these two different control logics, thereby increasing the burden on technicians. In addition, the increase in control logic will also make the control logic more prone to errors, so that technicians need to spend more time debugging the erroneous control logic, which not only increases the burden on technicians, but also reduces production efficiency.

[0034] Therefore, in order to solve the problem that the wafer storage 10 requires different control logics when transporting wafer boxes of different sizes, the present disclosure improves the wafer storage 10. The wafer storage 10 according to the present disclosure is described below with reference to the accompanying drawings.

[0035] The wafer storage device 10 provided in the present disclosure includes a transport device 100 , a stage 200 , and a control device 300 .

[0036] like Figure 2 and Figure 3As shown, the transport device 100 includes a moving mechanism 110 and a clamping mechanism 120. The moving mechanism 110 is used to move the clamping mechanism 120, and the clamping mechanism 120 is used to clamp the first wafer box 400 and the second wafer box 500 of different sizes. The moving mechanism 110 is, for example, a robotic arm. The clamping mechanism 120 can be connected to a certain position on the moving mechanism 110, and when the position of the moving mechanism 110 moves, the clamping mechanism 120 also moves with the position. The clamping mechanism 120 includes a first clamping portion 121 and a second clamping portion 122 arranged in sequence along the first straight line direction L1. The clamping mechanism 120 can switch between a clamping state and a release state. When the clamping mechanism 120 is in a clamping state, the first clamping portion 121 can clamp the first clamped portion 410 of the first wafer box 400, and the second clamping portion 122 can clamp the second clamped portion 510 of the second wafer box 500. When the clamping mechanism 120 is in the release state, the first clamping portion 121 can release the first clamped portion 410, and the second clamping portion 122 can release the second clamped portion 510. In other words, the structure of the first clamping portion 121 is adapted to the structure of the first clamped portion 410, and the structure of the second clamping portion 122 is adapted to the structure of the second clamped portion 510, so that the clamping mechanism 120 can achieve clamping and releasing of the first wafer box 400 and the second wafer box 500 by switching between the clamping state and the release state.

[0037] like Figure 4 As shown, the carrier 200 includes a supporting platform 210, a first positioning portion, and a second positioning portion. The supporting platform 210 is used to support any one of the first wafer box 400 and the second wafer box 500. The structure of the supporting platform 210 is adapted to the structure of the first wafer box 400 and the second wafer box 500, so that the first wafer box 400 can be placed on the supporting platform 210, and the second wafer box 500 can be placed on the supporting platform 210. The first positioning portion is used to position the first wafer box 400 on the supporting platform 210 so that the first clamped portion 410 is located at the first position. When the second wafer box 500 is placed on the supporting platform 210. The second positioning portion is used to position the second wafer box 500 on the supporting platform 210 so that the second clamped portion 510 is located at the second position, and the first position and the second position are arranged in sequence along the second straight line direction L2. Positioning the first wafer box 400 and the second wafer box 500 on the supporting platform 210 refers to constraining the freedom of the first wafer box 400 and the second wafer box 500 relative to the supporting platform 210 to prevent the positions of the first wafer box 400 and the second wafer box 500 from shifting after being placed on the carrier 200, thereby affecting the clamping mechanism 120 to clamp the first wafer box 400 and the second wafer box 500.

[0038] The control device 300 is used to control the moving mechanism 110 to move the clamping mechanism 120 between multiple positions including the target position, and to control the clamping mechanism 120 to switch between a clamping state and a released state. The control device 300 is, for example, a host computer, and can send a control signal to the controlled object according to the control logic, so that the controlled object works according to the control logic. The position to which the moving mechanism 110 moves the clamping mechanism 120 and whether the clamping mechanism 120 is in a clamping state or a released state are the results of the control device 300 controlling the moving mechanism 110 and the clamping mechanism 120 according to the control logic. Figure 5 As shown, when the clamping mechanism 120 is located at the target position, the first straight line direction L1 and the second straight line direction L2 coincide with each other as the same straight line direction, and the first clamping portion 121 and the second clamping portion 122 are respectively aligned with the first position and the second position along the same straight line direction, so that the first clamping portion 121 can clamp or release the first clamped portion 410 located at the first position, and the second clamping portion 122 can clamp or release the second clamped portion 510 located at the second position.

[0039] During the process of the transport device 100 transporting the first wafer box 400 or the second wafer box 500, each time the clamping mechanism 120 switches from the release state to the clamping state to clamp the first wafer box 400 or the second wafer box 500, or each time the clamping mechanism switches from the clamping state to the release state to release the first wafer box 400 or the second wafer box 500, the target position may be the target position. Taking the process of the transport device 100 clamping the first wafer box 400 or the second wafer box 500 on the target stage 200 as an example, initially, the clamping mechanism 120 is located at an initial position other than the target position and is in a release state. Since the coordinates of the initial position, the coordinates of the target position, the moving path from the initial position to the target position, and the posture and state of the clamping mechanism 120 are all preset in the control logic, the control device 300 can control the transport device 100 according to the preset control logic, so that the moving mechanism 110 moves the clamping mechanism 120 from the initial position to the target position along the preset moving path, and the posture of the clamping mechanism 120 is adjusted so that the first straight line direction L1 and the second direction coincide with each other as the same straight line direction. At this time, in the same straight line direction, the first clamping part 121 is aligned with the first position, and the second clamping part 122 is aligned with the second position. When the control device 300 controls the clamping mechanism 120 to switch from the release state to the clamping state, if the first wafer box 400 is placed on the carrier 200 at this time, the clamping mechanism 120 can clamp the first clamped part 410 located at the first position, and if the second wafer box 500 is placed on the carrier 200 at this time, the clamping mechanism 120 can clamp the second clamped part 510 located at the second position. Since the control logic used by the control device 300 when clamping the first wafer box 400 and the second wafer box 500 on the target carrier 200 does not include any logic for distinguishing the first wafer box 400 and the second wafer box 500, the technicians only need to develop a set of control logic to achieve the clamping of the first wafer box 400 and the second wafer box 500.

[0040] On the contrary, during the process of the handling device 100 releasing the clamped first chip box 400 or the second chip box 500 to the target carrier 200, the control device 300 can still release the first chip box 400 and the second chip box 500 according to the same set of control logic. The principle is the same as the clamping process and will not be repeated here.

[0041] The control device 300 of the chip storage 10 provided in the present application only needs to follow the same set of control logic when controlling the transport device 100 to transport the first chip box 400 and the second chip box 500, which can reduce the burden of technical personnel on developing and maintaining the control logic and improve production efficiency.

[0042] In some embodiments, Figure 3As shown, the specific structure of the clamping mechanism 120 may include a pair of clamping jaws 123. The pair of clamping jaws 123 are driven to move between the approach position and the distance position. The distance between the pair of clamping jaws 123 when they are in the approach position is smaller than the distance between them when they are in the distance position. The approach position and the distance position correspond to the clamping state and the release state respectively. The clamping mechanism 120 clamps and releases the first wafer box 400 and the second wafer box 500 by changing the distance between the pair of clamping jaws 123. The movement mode of the pair of clamping jaws 123 can be that one clamping jaw 123 is stationary and the other clamping jaw 123 moves, or the two clamping jaws 123 move at the same time. Regardless of the movement mode, the pair of clamping jaws 123 can be moved between the approach position and the distance position, that is, switched between the clamping state and the release state, so as to clamp and release the first wafer box 400 and the second wafer box 500. Each clamping jaw 123 has a first clamping jaw portion 1231 and a second clamping jaw portion 1232 arranged in sequence along the first straight line direction L1. The first clamping portion 121 includes two first clamping claw portions 1231, and the second clamping portion 122 includes two second clamping claw portions 1232. When the clamping mechanism 120 is located at the target position, the first clamped portion 410 located at the first position is between the two first clamping claw portions 1231; and the second clamped portion 510 located at the second position is between the two second clamping claw portions 1232. If the first wafer box 400 is placed on the carrier 200, when the first clamping portion 121 moves from the distant position to the close position, the distance between the two first clamping claw portions 1231 also decreases, and finally the first clamped portion 410 located between the two first clamping claw portions 1231 is clamped, thereby clamping the first wafer box 400. If a second wafer box 500 is placed on the carrier 200, when the second clamping portion 122 moves from a distant position to a close position, the distance between the two second clamping jaw portions 1232 also decreases, and eventually the second clamped portion 510 located between the two second clamping jaw portions 1232 is clamped, thereby clamping the second wafer box 500.

[0043] In some embodiments, Figure 3As shown, the clamping mechanism 120 also includes a base 124. Two clamping claws 123 are supported on the base 124. The base 124, two first clamping claw parts 1231 and two second clamping claw parts 1232 are arranged in sequence along the first straight line direction L1. The first straight line direction L1 is perpendicular to the up-down direction H. At this time, the projections of the first clamping claw part 1231, the second clamping claw part 1232 and the base 124 along the first straight line direction L1 on the plane parallel to the up-down direction H will have a large overlap, so that the size of the clamping mechanism 120 in the up-down direction H is small. On the one hand, the space occupied by the clamping mechanism 120 in the chip storage 10 is reduced, thereby improving the space utilization rate; on the other hand, the possibility of interference between the clamping mechanism 120 and other devices in the chip storage 10 when moving along the up-down direction H can be reduced.

[0044] In some embodiments, Figure 3 and Figure 5 As shown, the width of the first clamped portion 410 is smaller than the width of the second clamped portion 510, and the distance between the two first clamping claw portions 1231 is smaller than the distance between the two second clamping claw portions 1232. Since the base 124, the two first clamping claw portions 1231 and the two second clamping claw portions 1232 are arranged in sequence along the first straight line direction L1, the clamping mechanism 120 clamps the first wafer box 400 and the second wafer box 500 on the side of the base 124 facing the first clamping claw portions 1231 and the second clamping claw portions 1232. When the clamping mechanism 120 clamps the larger wafer box of the first wafer box 400 and the second wafer box 500, it will be clamped by the two first clamping claw portions 1231 with a larger distance between them. The two first clamping jaws 1231 with a larger spacing are farther from the base 124 than the two second clamping jaws 1232 with a smaller spacing, which can avoid interference between the two second clamping jaws 1232 with a smaller spacing and a larger wafer box, thereby further improving the adaptability of the clamping mechanism 120 to wafer boxes of different sizes.

[0045] In some embodiments, Figure 5As shown, the first clamped portion 410 includes two first side flanges 411, and the second clamped portion 510 includes two second side flanges 511. The two first clamping jaw portions 1231 are respectively provided with two first narrow grooves 12311, and the two second clamping jaw portions 1232 are respectively provided with two second narrow grooves 12321. When a pair of clamping jaws 123 is switched from the distant position to the close position, the two first narrow grooves 12311 can respectively receive the two first side flanges 411 to clamp the first wafer box 400, and the two second narrow grooves 12321 can respectively receive the two second side flanges 511 to clamp the second wafer box 500. When the two clamping jaws 123 are switched from the close position to the distant position, the two first narrow grooves 12311 can respectively separate from the two first side flanges 411 to release the first wafer box 400, and the two first narrow grooves 12311 can respectively separate from the two second side flanges 511 to release the second wafer box 500. The first wafer box 400 is clamped by the two first slots 12311 receiving the two first side flanges 411 respectively, so that when the first side flange 411 is located in the first slot 12311, it can be supported by the two slot walls and the slot bottom of the first slot 12311, thereby limiting the freedom of the first side flange 411 facing the two side walls and the slot bottom. Due to the support effect of the slot bottoms of the two first slots 12311 on the two first side flanges 411, frictional forces are generated between the slot bottoms of the two first slots 12311 and the two first side flanges 411 in the extending directions of the two first slots 12311 and the two first side flanges 411, thereby limiting the freedom of the two first wafer boxes 400 along the extending directions of the two first side flanges 411. Therefore, the first wafer box 400 is clamped by the two first slots 12311 respectively receiving the two first side flanges 411, so that the clamping mechanism 120 can firmly clamp the first wafer box 400, thereby effectively preventing the first wafer box 400 from falling off the clamping mechanism 120. The second wafer box 500 is clamped by the two second slots 12321 respectively receiving the two second side flanges 511, and the clamping mechanism 120 can also firmly clamp the second wafer box 500. The principle is the same as the principle of clamping the first wafer box 400 by the two first slots 12311 respectively receiving the two first side flanges 411, which will not be repeated here.

[0046] like Figure 5As shown, in some embodiments, a plane parallel to both the first linear direction L1 and the up-down direction H is defined as a first symmetry plane SP1. The two first side flanges 411 are symmetrically arranged relative to the first symmetry plane SP1, and the two second side flanges 511 are symmetrically arranged relative to the first symmetry plane SP1. A plane parallel to both the second linear direction L2 and the up-down direction H is defined as a second symmetry plane SP2, and a pair of clamping jaws 123 are symmetrically arranged relative to the second symmetry plane SP2. When the clamping mechanism 120 is located at the target position, the first symmetry plane SP1 and the second symmetry plane SP2 overlap. At this time, after the clamping mechanism 120 clamps the first chip box 400 and the second chip box 500, the center of gravity of the first chip box 400 and the center of gravity of the second chip box 500 are both located in the middle of a pair of clamping claws 123, so that the gravity of the first chip box 400 and the second chip box 500 can be evenly transmitted to each clamping claw 123, which can avoid the clamping mechanism 120 from deflecting due to uneven force after clamping the first chip box 400 and the second chip box 500, thereby improving the stability of the clamping mechanism 120 when clamping the first chip box 400 and the second chip box 500.

[0047] In some embodiments, Figure 4 As shown, the dimension of the first wafer box 400 in the second linear direction L2 is D1, the dimension of the second wafer box 500 in the second linear direction L2 is D2, the spacing between the first clamped portion 410 and the second clamped portion 510 in the second linear direction L2 is D3, D1<D2, D3<D1. The spacing between the first clamped portion 410 and the second clamped portion 510 in the second linear direction L2 is D3, and the spacing between the first clamping portion 121 and the second clamping portion 122 of the clamping mechanism 120 along the first linear direction L1 can be configured to be D3 accordingly, so as to clamp the first clamped portion 410 and the second clamped portion 510 respectively when the clamping mechanism 120 is located at the target position. Since D3 is less than D1, the space occupied by the first wafer box 400 and the second wafer box 500 on the carrier 200 has an overlapping portion along the first straight line direction L1, thereby reducing the size of the carrier 200 along the first straight line direction L1 while ensuring that both the first wafer box 400 and the second wafer box 500 can be clamped by the clamping mechanism 120. After the size of the carrier 200 is reduced, more carriers 200 or other devices can be arranged in the limited space of the wafer storage 10, thereby improving the space utilization of the wafer storage 10.

[0048] In some embodiments, Figure 6 and Figure 7As shown, the carrier 200 includes a first protrusion 220 and a second protrusion 230 protruding from the upper surface of the support platform 210. The first protrusion 220 and the second protrusion 230 are arranged in sequence along the second linear direction L2 and are spaced from each other. The first protrusion 220 has a first positioning surface 221 facing the second protrusion 230, and the second protrusion 230 has a second positioning surface 231 facing the first protrusion 220. The first protrusion 220 is provided with two third positioning surfaces 222 on opposite sides of the third linear direction L3 perpendicular to the second linear direction L2. The first positioning portion includes a first positioning surface 221, a second positioning surface 231 and two third positioning surfaces 222. The second beam at the bottom of the second wafer box 500 can be placed between the first positioning surface 221 and the second positioning surface 231, and the first positioning surface 221 and the second positioning surface 231 are respectively abutted against the second beam on both sides of the second beam along the second linear direction L2, thereby limiting the translational freedom of the second wafer box 500 on the carrier 200 along the second linear direction L2. The two side walls of the second wafer box 500 that are oppositely arranged along the third straight direction L3 can be respectively located on both sides of the first protrusion 220 along the third straight direction L3 and respectively abut against the two third positioning surfaces 222, thereby limiting the translational freedom of the second wafer box 500 along the third straight direction L3 on the carrier 200. In addition, the first positioning surface 221 and the second positioning surface 231 can limit the rotation of the second crossbeam of the second wafer box 500, and the two third positioning surfaces 222 can limit the rotation of the two side walls of the second wafer box 500 in the second straight direction L2, thereby limiting the rotational freedom of the second wafer box 500 on the carrier 200. The first positioning portion with such a structure can not only limit the movement of the second wafer box 500 on the carrier 200, but also has the characteristics of simple structure, easy processing and convenient use.

[0049] In some embodiments, Figure 6 and Figure 7As shown, the stage 200 includes a third protrusion 240 protruding from the upper surface of the supporting platform 210. The third protrusion 240 and the second protrusion 230 are spaced apart in the second linear direction L2 and are located on the side of the second protrusion 230 facing away from the first protrusion 220. The third protrusion 240 has a fourth positioning surface 241 facing the second protrusion 230, and the second protrusion 230 has a fifth positioning surface 232 facing the third protrusion 240. The first protrusion 220 is also provided with two sixth positioning surfaces 223 on opposite sides in the third linear direction L3. The two sixth positioning surfaces 223 are located on the inner side of the two third positioning surfaces 222 in the third linear direction L3, and are closer to the second protrusion 230 than the two third positioning surfaces 222 in the second linear direction L2. The second positioning portion includes a fourth positioning surface 241, a fifth positioning surface 232 and two sixth positioning surfaces 223. The first crossbeam at the bottom of the first wafer box 400 can be placed between the fourth positioning surface 241 and the fifth positioning surface 232. The fourth positioning surface 241 and the fifth positioning surface 232 respectively contact the first crossbeam on both sides of the first crossbeam along the second straight line direction L2, thereby limiting the translational freedom of the first wafer box 400 on the carrier 200 along the second straight line direction L2. The two side walls of the first wafer box 400 that are oppositely arranged along the third straight line direction L3 can be respectively located on both sides of the first protrusion 220 along the third straight line direction L3 and contact the two sixth positioning surfaces 223, thereby limiting the translational freedom of the first wafer box 400 on the carrier 200 along the third straight line direction L3. In addition, the fourth positioning surface 241 and the fifth positioning surface 232 can limit the rotation of the first crossbeam of the first wafer box 400, and the two sixth positioning surfaces 223 can limit the rotation of the two side walls of the first wafer box 400 in the second straight line direction L2, thereby limiting the rotational freedom of the first wafer box 400 on the carrier 200. The first convex portion 220 is provided with two third positioning surfaces 222 and two sixth positioning surfaces 223 on opposite sides in the third linear direction L3, respectively. The two sixth positioning surfaces 223 are located on the inner side of the two third positioning surfaces 222 in the third linear direction L3, and are closer to the second convex portion 230 than the two third positioning surfaces 222 in the second linear direction L2, so that the first convex portion 220 can be used to limit the freedom of the first wafer box 400 on the stage 200 in the third linear direction L3 and the freedom of the second wafer box 500 on the stage 200 in the third linear direction L3. The first positioning portion and the second positioning portion share the first convex portion 220 and the second convex portion 230, so that the size of the stage 200 can be reduced, thereby achieving the effect of reducing the volume of the wafer storage device 10.

[0050] In some embodiments, Figure 6 and Figure 7As shown, the two sixth positioning surfaces 223 are coplanar with the two end surfaces of the second protrusion 230 in the third straight line direction L3, and are coplanar with the two end surfaces of the two third protrusions 240 in the third straight line direction L3. When the first wafer box 400 is placed on the carrier 200, the two sixth positioning surfaces 223 are respectively in contact with the two side walls of the first wafer box 400 in the third straight line direction L3 to position the first wafer box 400 on the carrier 200. Since the two end faces of the second protrusion 230 in the third straight direction L3 are coplanar with the two sixth positioning faces 223, and are coplanar with the two end faces of the third protrusion 240 in the third straight direction L3, the two end faces of the second protrusion 230 in the third straight direction L3 and the two end faces of the third protrusion 240 in the third straight direction L3 will also respectively abut against the two side walls of the first chip box 400 in the third straight direction L3, thereby forming more constraints on the freedom of the first chip box 400 in the third straight direction L3 on the carrier 200, thereby enhancing the stability of the first chip box 400 when placed on the carrier 200.

[0051] It should be noted that the various elements described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0052] It should be understood that multiple components and / or parts can be provided by a single integrated component or part. Alternatively, a single integrated component or part can be divided into separate multiple components and / or parts. The disclosure "one" or "an" used to describe a component or part is not intended to exclude other components or parts.

[0053] It should be understood that although the terms “first” or “second”, etc. may be used in the present disclosure to describe various elements, these elements are not defined by these terms, and these terms are only used to distinguish one element from another.

[0054] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0055] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A chip memory, characterized in that: include: The transport device comprises a moving mechanism and a clamping mechanism, wherein the moving mechanism is used to move the clamping mechanism, the clamping mechanism comprises a first clamping portion and a second clamping portion sequentially arranged along a first straight line direction, and the clamping mechanism can be switched between a clamping state and a release state; when the clamping mechanism is in the clamping state, the first clamping portion and the second clamping portion can clamp a first clamped portion of a first wafer box and a second clamped portion of a second wafer box, respectively; when the clamping mechanism is in the release state, the first clamping portion and the second clamping portion can release the first clamped portion and the second clamped portion, respectively; A carrier, comprising a support platform, a first positioning portion, and a second positioning portion, wherein the support platform is used to support any one of the first wafer box and the second wafer box; The first wafer box and the second wafer box have different sizes; The first positioning portion is used to position the first wafer box on the supporting platform so that the first clamped portion is located at a first position; the second positioning portion is used to position the second wafer box on the supporting platform so that the second clamped portion is located at a second position, and the first position and the second position are arranged in sequence along a second straight line direction; as well as A control device is used to control the moving mechanism to move the clamping mechanism between a plurality of positions including a target position, and to control the clamping mechanism to switch between the clamping state and the releasing state; when the clamping mechanism is located at the target position, the first straight line direction and the second straight line direction coincide with each other as the same straight line direction, and the first clamping portion and the second clamping portion are respectively aligned with the first position and the second position along the same straight line direction, so that the first clamping portion and the second clamping portion can respectively clamp or release the first clamped portion located at the first position and the second clamped portion located at the second position.

2. The chip memory according to claim 1, characterized in that: The clamping mechanism comprises a pair of clamping jaws, which are driven to move between a close position and a far position, wherein the close position and the far position correspond to the clamping state and the releasing state respectively; each clamping jaw comprises a first clamping jaw portion and a second clamping jaw portion which are sequentially arranged along the first straight line direction; the first clamping portion comprises two first clamping jaw portions, and the second clamping portion comprises two second clamping jaw portions; when the clamping mechanism is located at the target position, the first clamped portion located at the first position is between the two first clamping jaw portions; The second clamped portion located at the second position is between the two second clamping jaw parts.

3. The chip memory according to claim 2, characterized in that: The clamping mechanism also includes a base, the two clamping jaws are supported on the base, the base, the two first clamping jaw parts and the two second clamping jaw parts are arranged in sequence along the first straight line direction, and the first straight line direction is perpendicular to the up and down direction.

4. The chip memory according to claim 3, characterized in that: The width of the first clamped portion is smaller than the width of the second clamped portion, and the distance between the two first clamping jaw portions is smaller than the distance between the two second clamping jaw portions.

5. The chip memory according to claim 4, characterized in that: The first clamped portion includes two first side flanges, the second clamped portion includes two second side flanges, the two first clamping jaw portions are respectively provided with two first slots, and the two second clamping jaw portions are respectively provided with two second slots; When the pair of clamping jaws are switched from the distant position to the close position, the two first slots can respectively receive the two first side flanges to clamp the first wafer box, and the two second slots can respectively receive the two second side flanges to clamp the second wafer box; When the two clamping jaws are switched from the approaching position to the distant position, the two first slots can be separated from the two first side flanges to release the first wafer box, and the two first slots can be separated from the two second side flanges to release the second wafer box.

6. The chip memory according to claim 5, characterized in that: A plane parallel to both the first straight line direction and the up-down direction is defined as a first symmetry plane, the two first side flanges are arranged symmetrically relative to the first symmetry plane, and the two second side flanges are arranged symmetrically relative to the first symmetry plane; a plane parallel to both the second straight line direction and the up-down direction is defined as a second symmetry plane, and the pair of clamps are arranged symmetrically relative to the second symmetry plane; when the clamping mechanism is located at the target position, the first symmetry plane and the second symmetry plane coincide with each other.

7. The chip memory according to claim 3, characterized in that: The size of the first wafer box in the second straight line direction is D1, the size of the second wafer box in the second straight line direction is D2, the distance between the first clamped portion and the second clamped portion in the second straight line direction is D3, D1<D2, D3<D1.

8. The chip memory according to claim 1, characterized in that: The carrier includes a first convex portion and a second convex portion protruding from the upper surface of the supporting platform, the first convex portion and the second convex portion are arranged in sequence along the second straight line direction and spaced from each other, the first convex portion has a first positioning surface facing the second convex portion, the second convex portion has a second positioning surface facing the first convex portion, the first convex portion is provided with two third positioning surfaces on opposite sides of a third straight line direction perpendicular to the second straight line direction, and the first positioning portion includes the first positioning surface, the second positioning surface and the two third positioning surfaces.

9. The chip memory according to claim 8, characterized in that: The carrier includes a third protrusion protruding from the upper surface of the supporting platform, the third protrusion and the second protrusion are spaced apart in the second straight line direction and are located on the side of the second protrusion facing away from the first protrusion, the third protrusion has a fourth positioning surface facing the second protrusion, the second protrusion has a fifth positioning surface facing the third protrusion, the first protrusion is also provided with two sixth positioning surfaces on opposite sides of the third straight line direction, the two sixth positioning surfaces are located on the inner side of the two third positioning surfaces in the third straight line direction, and are closer to the second protrusion than the two third positioning surfaces in the second straight line direction; the second positioning portion includes the fourth positioning surface, the fifth positioning surface and the two sixth positioning surfaces.

10. The chip memory according to claim 9, characterized in that: The two sixth positioning surfaces are coplanar with two end surfaces of the second protrusion in the third straight line direction, and are coplanar with two end surfaces of the two third protrusions in the third straight line direction.

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