Chip packaging structure and chip packaging method

Abstract

The invention provides a chip packaging structure and a chip packaging method. The chip packaging structure comprises a flexible substrate, a rewiring layer and at least two chips. The flexible substrate comprises a first sub-part, a second sub-part and a bending part connected between the first sub-part and the second sub-part; the rewiring layer is located on the first sub-surface of the first sub-part, the second sub-surface of the second sub-part and the third sub-surface of the bending part, and the third sub-surface is connected with the first sub-surface and the second sub-surface to form the first surface of the flexible substrate; the at least two chips are located on the first surface of the flexible substrate and located in the non-bending area of the flexible substrate, and the chips are electrically connected with the rewiring layer. The chip packaging structure is suitable for a 3D packaging process, the process requirement is simplified, and the production cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of chip packaging technology, and in particular, to a chip packaging structure and a chip packaging method. Background Art

[0002] With the development of semiconductor silicon technology, the key dimensions of chips are getting smaller and smaller. In order to reduce costs, more advanced chip manufacturing processes with higher integration levels are tended to be selected during chip manufacturing. This makes the chip size smaller and smaller, and the I / O density on the chip surface higher and higher.

[0003] The multifunctional development trend of terminal products also puts forward more requirements on the functions of chips, so the packaging of single-function chips can no longer meet the needs of terminal products. Multi-chip system integration technology, such as silicon-based fan-out packaging, came into being in this context. However, in some cases, such as 3D packaging, in the process of silicon-based fan-out packaging, it is necessary to open holes and fill metal on the silicon-based substrate, which leads to problems of high process difficulty and high cost. Summary of the invention

[0004] The present disclosure provides a chip packaging structure and a chip packaging method, which realizes the interconnection of chips on the first surface of a flexible substrate by utilizing a rewiring layer on the first surface of a flexible substrate. Although the chips are located on different sides of the flexible substrate, it is not necessary to design opening and filling holes in the flexible substrate, thereby reducing the process difficulty of chip packaging and saving costs.

[0005] The first aspect of the present disclosure provides a chip packaging structure, which includes a flexible substrate, a rewiring layer and at least two chips. The flexible substrate includes a first sub-section, a second sub-section and a bending section connecting the first sub-section and the second sub-section; the rewiring layer is located on a first sub-surface of the first sub-section, a second sub-surface of the second sub-section and a third sub-surface of the bending section, wherein the third sub-surface connects the first sub-surface and the second sub-surface to form a first surface of the flexible substrate; at least two chips are located on the first surface of the flexible substrate and in a non-bending area of ​​the flexible substrate, and the chips are electrically connected to the rewiring layer.

[0006] In the above solution, the rewiring layer located on the first surface of the flexible substrate is used to realize the arcs of the chips located on different sides of the first surface of the flexible substrate, thereby reducing the difficulty of the chip packaging process.

[0007] In a specific embodiment of the first aspect of the present disclosure, the rewiring layer is located between the at least two chips and the flexible substrate.

[0008] In a specific embodiment of the first aspect of the present disclosure, the rewiring layer is located on surfaces of at least two chips facing away from the flexible substrate.

[0009] Optionally, a recessed area is provided on the flexible substrate, and at least part of the chip is located in the recessed area. Thus, at least part of the chip is disposed in the recessed area, which not only improves the integration of the chip packaging structure, but also strengthens the physical protection of the chip.

[0010] In a specific embodiment of the first aspect of the present disclosure, the chip packaging structure further includes a plurality of solder balls, wherein the rewiring layer includes a plurality of signal lines, at least some of the signal lines are electrically connected to the plurality of solder balls, and the solder balls correspond to the signal lines one-to-one.

[0011] Optionally, the first sub-section is arranged perpendicularly or parallel to the second sub-section.

[0012] Optionally, a plurality of the first sub-sections and the second sub-sections are provided, and the plurality of first sub-sections and the second sub-sections are respectively arranged in parallel.

[0013] Optionally, all solder balls are located on the first sub-surface of the first sub-section or the second sub-surface of the second sub-section.

[0014] Optionally, some solder balls are located on the first sub-surface of the first sub-section, and signal lines connected to some solder balls are located on the first sub-surface of the first sub-section, and the remaining solder balls are located on the second sub-surface of the second sub-section, and signal lines connected to the remaining solder balls are located on the second sub-surface of the second sub-section.

[0015] In a specific embodiment of the first aspect of the present disclosure, the chip packaging structure further includes a dielectric layer. The dielectric layer is located between the chip and the rewiring layer, and is provided with vias, and a portion of the rewiring layer fills the vias to form a via connection portion, and the signal line is electrically connected to the chip or the solder ball through the via connection portion. In this way, the chip and the rewiring layer are insulated by the dielectric layer, and the rewiring layer is electrically connected to the chip through the vias formed on the dielectric layer, thereby avoiding a complicated hole opening process and simplifying the process of the chip packaging process.

[0016] Optionally, the chip packaging structure further includes a protective layer, which is located on the surface of the rewiring layer away from the dielectric layer, and has a plurality of openings. The solder balls are respectively located in the openings and protrude out of the protective layer, and the openings correspond one-to-one to the above solder balls.

[0017] A second aspect of the present disclosure provides a chip packaging method, which includes: providing a flexible substrate, including a first sub-portion, a second sub-portion and at least one bending portion, wherein the bending portion connects the first sub-portion and the second sub-portion, and the third sub-surface of the bending portion respectively connects the first sub-surface of the first sub-portion and the second sub-surface of the second sub-portion to form a first surface of the flexible substrate; respectively arranging at least two chips on the first surface of the flexible substrate; forming a rewiring layer on the first surface of the flexible substrate, and the rewiring layer is electrically connected to the at least two chips; and bending the flexible substrate at the bending portion.

[0018] In the above scheme, in the chip packaging method, the rewiring layer located on the first surface of the flexible substrate is first used to realize the electrical connection of the chip located on the first surface of the flexible substrate, and then the chip is bent so that the electrically connected chips are located on different sides of the flexible substrate. During the whole process, there is no need to open and fill holes on the flexible substrate, thereby reducing the process difficulty of chip packaging and saving production costs.

[0019] In a specific embodiment of the second aspect of the present disclosure, the step of respectively arranging at least two chips on the first surface of the flexible substrate includes: forming a first recessed area on the first sub-surface of the first sub-section; arranging at least one chip in the first recessed area; forming a second recessed area on the second sub-surface of the second sub-section; and arranging at least one chip in the second recessed area.

[0020] In a specific embodiment of the second aspect of the present disclosure, a rewiring layer is formed on the first surface of the flexible substrate, and the step of electrically connecting the rewiring layer to the two chips includes: forming a dielectric layer on the side of the chip facing away from the flexible substrate, wherein the dielectric layer forms vias; forming a rewiring layer on the side of the dielectric layer facing away from the flexible substrate, partially filling the vias in the rewiring layer to form via connection portions; and patterning the rewiring layer to form a plurality of signal lines, wherein at least some of the signal lines are connected to the chip through the via connection portions.

[0021] In a specific embodiment of the second aspect of the present disclosure, before the step of bending the bending portion, the step further includes: forming a plurality of solder balls, wherein the plurality of solder balls are respectively connected to at least part of the signal lines, and the solder balls correspond to the signal lines one by one.

[0022] Optionally, the step of forming a plurality of solder balls includes: forming a plurality of solder balls on a first sub-surface of the first sub-portion, or forming a plurality of solder balls on a second sub-surface of the second sub-portion.

[0023] Optionally, the step of forming multiple solder balls includes: forming part of the solder balls on the first sub-surface of the first sub-section, forming the remaining solder balls on the second sub-surface of the second sub-section, and the signal lines connected to the part of the solder balls are located on the first sub-surface of the first sub-section, and the signal lines connected to the remaining solder balls are located on the second sub-surface of the second sub-section.

[0024] In a specific embodiment of the second aspect of the present disclosure, before the step of forming the solder balls, the step also includes: forming a protective layer on the side of the rewiring layer away from the flexible substrate; forming openings on the surface of the protective layer away from the flexible substrate, the openings are used to accommodate the solder balls, and the openings correspond to the solder balls one by one. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic cross-sectional view of a chip packaging structure provided in one embodiment of the present disclosure.

[0026] Figure 2 for Figure 1 An enlarged view of point A of a chip packaging structure shown.

[0027] Figure 3 for Figure 1 An enlarged view of point A of another chip packaging structure is shown.

[0028] Figure 4 for Figure 1 An enlarged view of point A of another chip packaging structure is shown.

[0029] Figure 5 for Figure 1 The chip packaging structure shown is a plan view of a structure.

[0030] Figure 6 for Figure 1 A plan view of another chip packaging structure is shown.

[0031] Figure 7 A schematic cross-sectional view of a chip packaging structure provided in one embodiment of the present disclosure.

[0032] Figure 8 A schematic cross-sectional view of a chip packaging structure provided in one embodiment of the present disclosure.

[0033] Fig. 9 A schematic cross-sectional view of a chip packaging structure provided in accordance with another embodiment of the present disclosure.

[0034] Fig.10 A schematic cross-sectional view of a chip packaging structure provided in one embodiment of the present disclosure.

[0035] Fig.11 A schematic cross-sectional view of a chip packaging structure provided in one embodiment of the present disclosure.

[0036] Fig.12 A schematic diagram of a chip packaging method according to an embodiment of the present disclosure

[0037] Fig.13A partial flow chart of a chip packaging method provided in one embodiment of the present disclosure.

[0038] Fig.14 A partial flow chart of a chip packaging method provided in one embodiment of the present disclosure.

[0039] Fig.15 A schematic flow chart of a chip packaging method provided in accordance with another embodiment of the present disclosure.

[0040] Fig.16 A schematic flow chart of a chip packaging method provided in accordance with another embodiment of the present disclosure.

[0041] Description of reference numerals:

[0042] 100-flexible substrate; 110-first sub-portion; 111-first sub-surface; 120-second sub-portion; 121-second sub-surface; 130-bending portion; 131-third sub-surface; 132-first sub-bending portion; 133-second sub-bending portion; 134-bending connection portion; A1-first surface; S-recessed area; 200-chip; 210-first chip; 220-second chip; 230-third chip; 300-rewiring layer; 310-signal line; 311-chip connection line; 312-pin lead; 400-solder ball; 500-dielectric layer; 510-via; 520-via connection portion; 600-protective layer; 610-opening. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Fan-out Silicon Based Packaging is an advanced integrated circuit packaging technology. This packaging technology is to package chips on a silicon base (wafer), and re-layout and package the single chip originally cut from the silicon base at the wafer level, so that the pin leads of the chip are extended from the original chip area to the entire wafer area, just like "fanning out" the connection of the chip to a larger range, hence the name "fan-out". In the packaging process, a redistribution layer (RDL, Redistribution Layer) is formed on the silicon base through special processes and materials. For example, insulating materials are first deposited on the silicon base, and then a redistribution layer (including new packaging pins) is formed through processes such as photolithography and etching; then, the I / O port of the chip is connected to the new packaging pin to realize signal redistribution and lead-out. However, in some packaging requirements such as 3D packaging, in order to realize the interconnection between the chips on the opposite sides of the silicon base, complex hole opening and hole filling processes are required, which increases the difficulty and cost of the chip packaging process.

[0045] In view of this, the embodiments of the present disclosure provide a chip packaging structure and a chip packaging method, wherein the chip packaging structure includes a flexible substrate, a rewiring layer and at least two chips. The flexible substrate includes a first sub-section, a second sub-section and a bending section connecting the first sub-section and the second sub-section; the rewiring layer is located on the first sub-surface of the first sub-section, the second sub-surface of the second sub-section and the third sub-surface of the bending section, wherein the third sub-surface respectively connects the first sub-surface and the second sub-surface to form the first surface of the flexible substrate; at least two chips are located on the first surface of the flexible substrate and located in the non-bending area of ​​the flexible substrate, and the chips are electrically connected to the rewiring layer. In this way, the rewiring layer located only on the first surface of the flexible substrate can interconnect the chips located on different sides of the flexible substrate on the chip packaging structure, without the need to design opening and filling holes on the flexible substrate, thereby reducing the process difficulty and saving costs.

[0046] Hereinafter, a chip packaging method and a chip packaging structure according to at least one embodiment of the present disclosure will be described in conjunction with the accompanying drawings.

[0047] For example, Figure 1 As shown, the chip packaging structure includes a flexible substrate 100 , a plurality of chips 200 disposed on the flexible substrate 100 , for example, three chips 200 , namely a first chip 210 , a second chip 220 and a third chip 230 , and a rewiring layer 300 disposed on surfaces of the plurality of chips 200 facing away from the flexible substrate 100 .

[0048] The flexible substrate 100 includes a first sub-portion 110, a second sub-portion 120 and a bending portion 130 located therebetween. The bending portion 130 connects the first sub-portion 110 and the second sub-portion 120 so that the first sub-portion 110 and the second sub-portion 120 are arranged opposite to each other, and a third sub-surface 131 of the bending portion 130 connects the first sub-surface 111 of the first sub-portion 110 and the second sub-surface 121 of the second sub-portion 120 to form a first surface A1 of the flexible substrate 100.

[0049] The disclosed embodiments do not specifically limit the parameters such as the material of the flexible substrate 100. The flexible substrate 100 can withstand a certain degree of bending, folding, stretching and twisting without breaking or being damaged. For example, in a wearable device, the chip 200 may be constantly deformed with the movement of the human body, and the flexible substrate 100 needs to ensure that it can still maintain good performance and integrity in such a dynamic environment. In addition, the flexible substrate 100 also needs to meet other requirements of chip packaging, such as electrical, thermal, chemical and processing performance requirements, so as to ensure the performance, reliability and durability of the chip 200 using the flexible substrate 100.

[0050] The plurality of chips 200 are respectively located in the non-bending area of ​​the flexible substrate 100, that is, other areas of the flexible substrate 100 except the bending portion 130. For example, the chips 200 are located on the first sub-portion 110 and the second sub-portion 120 of the flexible substrate 100. Specifically, the first chip 210 and the second chip 220 are located on the first sub-surface 111 of the first sub-portion 110, and the third chip 230 is located on the second sub-surface 121 of the second sub-portion 120, that is, the three chips 200 are all located on the first surface A1 of the flexible substrate 100. And, referring to Figure 1 It can be seen that the first chip 210 and the second chip 220 are respectively located on the same side of the flexible substrate 100 , and the second chip 220 and the third chip 230 are respectively located on different sides of the flexible substrate 100 .

[0051] The rewiring layer 300 is located on the side of the first chip 210, the second chip 220 and the third chip 230 away from the flexible substrate 100, and the rewiring layer 300 is located on the first sub-surface 111 of the first sub-portion 110, the second sub-surface 121 of the second sub-portion 120 and the third sub-surface 131 of the bending portion 130, that is, the rewiring layer 300 is located on the first surface A1 of the flexible substrate 100, and is not formed on different surfaces of the flexible substrate 100, which also explains that the process of forming the rewiring layer 300 does not involve the process of opening and filling holes in the flexible substrate 100. The rewiring layer 300 is electrically connected to the chip 200, referring to Figure 1 It can be seen that the rewiring layer 300 realizes the electrical connection between the second chip 220 and the third chip 230 located on different sides of the flexible substrate 100 .

[0052] It should be noted that the chip packaging structure in the embodiment of the present disclosure is not limited to the above examples and illustrations. For example, the number of the plurality of chips 200 is not limited to the above examples and illustrations. Figure 1 The three shown in the figure may be two, four, five or more. For example, the distribution of the chips 200 is not limited to the example in the figure, and the chips 200 may all be located on the first sub-surface 111 of the first sub-section 110 or the second sub-surface 121 of the second sub-section 120, or more chips 200 may be distributed on the second sub-surface 121 of the second sub-section 120. All of the above can be designed according to actual needs and will not be described in detail here.

[0053] In a chip packaging structure provided by an embodiment of the present disclosure, Figure 2 As shown, the rewiring layer 300 is located between at least two chips 200 and the flexible substrate 100. Specifically, the chip 200, such as the third chip 230, is located on the flexible substrate 100, and the rewiring layer 300 is disposed between the third chip 230 and the flexible substrate 100. In this way, the rewiring layer 300 is disposed below the chip 200, which can reduce signal interference and improve signal integrity and accuracy.

[0054] In a chip packaging structure provided in another embodiment of the present disclosure, Figure 3 As shown, the rewiring layer 300 is located on the surface of at least two chips 200 away from the flexible substrate 100. For example, the chip 200, such as the third chip 230, is located on the flexible substrate 100, and the rewiring layer 300 is arranged on the side of the third chip 230 away from the flexible substrate 100. In this way, the rewiring layer 300 can achieve new functions or optimize performance by adjusting the wiring without changing the core circuit of the chip 200. Therefore, the rewiring layer 300 is arranged above the chip 200, which can make the design of the chip 200 more flexible and facilitate subsequent upgrades and improvements.

[0055] In the chip packaging structure provided by at least one embodiment of the present disclosure, Figure 4 As shown, a recessed area S is provided on the flexible substrate 100, and at least a portion of the chip 200 is located in the recessed area S. For example, the chip 200 is located in the recessed area S, and the surface of the chip 200 is exposed to the opening of the recessed area S and is electrically connected to the rewiring layer 300. Specifically, refer to Figure 1 and Figure 4It can be seen that all the chips 200, namely the first chip 210, the second chip 220 and the third chip 230, are located in the recessed area S and are flush with the opening of the recessed area S. The rewiring layer 300 is located on the surface of the chip 200 on the side away from the flexible substrate 100 and is electrically connected to the chip 200. In this way, embedding the chip 200 in the flexible substrate 100 can not only reduce the influence of external environmental factors such as mechanical stress, moisture, dust, etc. on the chip 200, improve the mechanical strength of the chip packaging structure, thereby enhancing the reliability of the chip packaging structure, but also help to achieve the miniaturization design of the chip packaging structure and improve the integration of the packaging structure. In addition, the flexible substrate 100 usually has good thermal conductivity. Embedding the chip 200 in the flexible substrate 100 can make the heat generated by the chip 200 more effectively transferred, which is conducive to reducing the operating temperature of the chip 200, improving the reliability and stability of the chip 200, and extending the service life of the chip 200.

[0056] It should be noted that the present disclosure does not specifically define the recessed area S. The recessed areas S located in different areas, namely the first sub-section 110 and the second sub-section 120, are not the same, and the recessed areas S in the same area, namely the first sub-section 110 or the second sub-section 120, can be one or more. And the specific structure, size and other information about the recessed area S can be defined according to actual needs, and will not be elaborated here.

[0057] Based on the above embodiments, in the chip packaging structure, in addition to defining the specific relationship between the flexible substrate 100, the chip 200 and the rewiring layer 300, the embodiment of the present disclosure also introduces how the rewiring layer 300 realizes signal transmission, i.e., electrical connection with the chip 200.

[0058] For example, in a chip packaging structure provided by an embodiment of the present disclosure, the chip packaging structure also includes a plurality of solder balls 400, wherein the rewiring layer 300 includes a plurality of signal lines 310, at least some of the signal lines 310 are electrically connected to the plurality of solder balls 400, and the solder balls 400 correspond one-to-one to the signal lines 310.

[0059] For example, Figure 5 and Figure 6As shown, the chip packaging structure includes a flexible substrate 100, a plurality of chips 200, and a rewiring layer 300. The rewiring layer 300 is disposed on the flexible substrate 100, and is located on the same surface of the flexible substrate 100 as the plurality of chips 200. Some of the plurality of chips 200 are disposed on the first sub-surface 111 of the first sub-portion 110, and the remaining portion of the chips 200 are disposed on the second sub-surface 121 of the second sub-portion 120. The rewiring layer 300 includes a plurality of signal lines 310, such as a chip connection line 311 and a pin lead 312, the two ends of the chip connection line 311 are respectively connected to different chips 200 to realize electrical connection between the two chips 200, and one end of the pin lead 312 is connected to the chip 200, and the other end is connected to the solder ball 400, thereby realizing electrical connection between the chip 200 and the external circuit. Specifically, a plurality of pin leads 312 are provided, each pin lead 312 is connected to a corresponding solder ball 400 , and one end of each pin lead 312 is connected to a chip 200 , but a chip 200 can be connected to a plurality of pin leads 312 .

[0060] It should be noted that the above examples and illustrations of the present disclosure only show the connection relationship between some of the signal lines 310 formed by the rewiring layer 300 and the chip 200, and do not limit the layout and planning of the multiple signal lines 310 set in the rewiring layer 300 in the chip packaging structure, which can be designed according to actual needs and will not be elaborated here.

[0061] Based on the above embodiments, the embodiments of the present disclosure further introduce various structures of the chip packaging structure and demonstrate the applicability of the chip packaging structure.

[0062] For example, in a chip packaging structure provided by an embodiment of the present disclosure, the first sub-portion 110 is disposed vertically or parallel to the second sub-portion 120 .

[0063] For example, Figure 1 As shown, in the chip packaging structure, the flexible substrate 100 includes a bending portion 130, a first sub-portion 110 and a second sub-portion 120, wherein the bending portion 130 connects the first sub-portion 110 and the second sub-portion 120 to form the overall structure of the flexible substrate 100, and at the same time, due to the bending of the bending portion 130, the first sub-portion 110 and the second sub-portion 120 are perpendicular to each other.

[0064] For example, Figure 7As shown, in the chip packaging structure, the flexible substrate 100 includes a bending portion 130, a first sub-portion 110 and a second sub-portion 120. The bending portion 130 includes a first sub-bending portion 132, a second sub-bending portion 133 and a bending connection portion 134 connecting the first sub-bending portion 132 and the second sub-bending portion 133. At the same time, under the influence of the bending of the bending portion 130, the first sub-portion 110 and the second sub-portion 120 are parallel to each other.

[0065] In the chip packaging structure provided by an embodiment of the present disclosure, all solder balls 400 are located on the first sub-surface 111 of the first sub-portion 110 or the second sub-surface 121 of the second sub-portion 120 .

[0066] For example, Figure 6 and Figure 8 As shown, all solder balls 400 are located on the second sub-section 120 of the flexible substrate 100. In this way, the solder balls 400 are arranged on the same side of the flexible substrate 100, such as the upper side in the figure, and no solder balls 400 are arranged on the first sub-section 110 of the flexible substrate 100, and the bending portion 130 can be bent at various angles so that the first sub-section 110 and the second sub-section 120 do not fit each other, thereby improving the applicability of the solution.

[0067] It should be noted that all solder balls 400 can also be located on the first sub-section 110, and the angle formed by the surface where the first sub-section 110 is located and the surface where the first sub-section 110 is located is not limited to 90° as shown in the example in the figure, but can also be other angles such as 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110°, 120°, 130°, 140°, 150°, 160°, 170°, 175°, etc.

[0068] In a chip packaging structure provided in another embodiment of the present disclosure, Figure 5 and Fig. 9 As shown, part of the solder balls 400 are located on the first sub-surface 111 of the first sub-portion 110, and the signal lines 310 connected to part of the solder balls 400 are located on the first sub-surface 111 of the first sub-portion 110, and the remaining part of the solder balls 400 are located on the second sub-surface 121 of the second sub-portion 120, and the signal lines 310 connected to the remaining part of the solder balls 400 are located on the second sub-surface 121 of the second sub-portion 120. In this way, there are solder balls 400 on both sides of the flexible substrate 100, and the solder balls 400 are connected to the corresponding signal lines 310 on both sides of the flexible substrate 100, such as pin leads 312, and the pin leads 312 do not need to pass through the bending portion 130, so that the number of metal wirings at the bending position, i.e., the bending portion 130, can be reduced, and the yield loss caused by folding the metal wiring can be reduced.

[0069] In addition to limiting the relative positional relationship between the first sub-section 110 and the second sub-section 120 , the embodiment of the present disclosure also limits the number of the first sub-section 110 and the second sub-section 120 .

[0070] For example, in a chip packaging structure provided by an embodiment of the present disclosure, a plurality of first sub-portions 110 and second sub-portions 120 are provided, and the plurality of first sub-portions 110 and second sub-portions 120 are respectively arranged in parallel.

[0071] For example, Fig.10 As shown, in the chip packaging structure, the first sub-section 110 and the second sub-section 120 are respectively provided with two, and the corresponding bending section 130 connecting the first sub-section 110 and the second sub-section 120 is provided with multiple, and the structure of each bending section 130 can refer to Figure 7 , that is, each bending portion 130 includes a first sub-bending portion 132 , a second sub-bending portion 133 , and a bending connection portion 134 connecting the first sub-bending portion 132 and the second sub-bending portion 133 .

[0072] In addition, the number of the first sub-section 110, the second sub-section 120 and the bending section 130 is not limited to the above examples and illustrations, and may include more first sub-sections 110 and second sub-sections 120, such as three, four, etc. This can be designed according to actual needs and will not be elaborated here.

[0073] In a chip packaging structure provided by an embodiment of the present disclosure, Fig.11 As shown, the chip packaging structure further includes a dielectric layer 500 located between the chip 200 and the rewiring layer 300. A plurality of vias 510 are provided on the dielectric layer 500, and a portion of the rewiring layer 300 fills the vias 510 to form via connecting portions 520, through which the signal line 310 is electrically connected to the chip 200 or the solder ball 400.

[0074] In a chip packaging structure provided in an embodiment of the present disclosure, continue to refer to Fig.11 The chip packaging structure further includes a protective layer 600 located on the surface of the rewiring layer 300 away from the dielectric layer 500. The protective layer 600 is provided with a plurality of openings 610, and the solder balls 400 are respectively located in the openings 610 and protrude from the protective layer 600, and the openings 610 correspond to the above solder balls 400 one by one.

[0075] The present disclosure also provides a chip packaging method, illustratively, as follows: Fig.12 As shown, the chip packaging method includes the following steps:

[0076] Step S100: Provide a flexible substrate, including a first sub-section, a second sub-section and at least one bending section, wherein the bending section connects the first sub-section and the second sub-section, and the third sub-surface of the bending section respectively connects the first sub-surface of the first sub-section and the second sub-surface of the second sub-section to form a first surface of the flexible substrate.

[0077] Step S200: Dispose at least two chips on the first surface of the flexible substrate respectively.

[0078] Step S300: forming a rewiring layer on a first surface of the flexible substrate, wherein the rewiring layer is electrically connected to at least two chips.

[0079] Step S400: bending the flexible substrate at the bending portion.

[0080] In the chip packaging method of the embodiment of the present disclosure, the bending portion is bent, and the bending angle can be 90° or 180°. During the bending process, the first sub-portion of the flexible substrate in which the chip is arranged approaches the second sub-portion of the flexible substrate along the bending direction; after the bending is completed, the first sub-portion and the second sub-portion are arranged relative to each other, for example, perpendicularly or parallel to each other, and the rewiring layer connecting the chip is formed on the first surface of the flexible substrate. Therefore, the electrical connection between the chip located on the first sub-surface of the first sub-portion of the flexible substrate and the chip located on the second sub-surface of the second sub-portion of the flexible substrate is realized without the need for opening and filling holes on the flexible substrate.

[0081] It should be noted that the packaging method of the chip disclosed in the present invention is not limited to the above examples, and it may also include other design schemes. For example, step S200 and step S300 may be swapped in order. For example, the packaging method of the chip may also include fixing the bent chip mounting structure after bending to prevent it from rebounding or deforming during subsequent use. Specifically, a clamp, adhesive or other fixing device may be used. For example, the bent portion is protected, such as by coating a protective layer, adding reinforcements, etc., to improve its durability. For another example, a comprehensive quality inspection is performed on the chip packaging structure obtained using the chip packaging method to check whether there are problems such as cracks, delamination, short circuits, etc., to ensure the reliability and stability of the packaging structure. In addition, the embodiment of the present disclosure does not specifically limit the bending process. During the bending process, the bending radius, bending speed, etc. can be designed according to actual needs, which will not be elaborated here.

[0082] In a chip packaging method provided by an embodiment of the present disclosure, as Fig.13 As shown, in step S200, the step of respectively placing at least two chips on the first surface of the flexible substrate includes:

[0083] Step S210: forming a first recessed area on a first sub-surface of a first sub-portion.

[0084] Step S220: disposing at least one chip in the first recessed area.

[0085] Step S230: forming a second recessed area on the second sub-surface of the second sub-portion.

[0086] Step S240: disposing at least one chip in the second recessed area.

[0087] Among them, step S210 and step S220 may be performed in any order or simultaneously, and step S230 and step S240 may be performed in any order or simultaneously. These can be selected according to actual needs and will not be described in detail here.

[0088] In a chip packaging method provided by an embodiment of the present disclosure, as Fig.14 As shown, in step S300, a rewiring layer is formed on the first surface of the flexible substrate, and the step of electrically connecting the rewiring layer to the two chips includes:

[0089] Step S310: A dielectric layer is formed on the side of the chip away from the flexible substrate, wherein the dielectric layer forms vias. For example, the dielectric layer is made by coating, photolithography and then developing technology or by depositing silicon dioxide by chemical vapor deposition (CVD), and a portion of the dielectric layer on the surface of the chip is opened by mechanical opening, dry and wet etching, photolithography, etc. to form vias, thereby reserving space for the subsequent production of a rewiring layer.

[0090] Step S320: forming a rewiring layer on the side of the dielectric layer away from the flexible substrate, and partially filling the vias with the rewiring layer to form via connection portions. For example, the rewiring layer is manufactured by sputtering, gluing, photolithography, developing, electroplating, degumming, etching and other manufacturing processes, and the metal types used in the rewiring layer can be copper, aluminum, nickel, gold, tin, tin-silver and the like.

[0091] Step S330: patterning the rewiring layer to form a plurality of signal lines, at least some of which are connected to the chip through via connection portions.

[0092] In a chip packaging method provided by an embodiment of the present disclosure, before the step of bending the bending portion, the method further includes: forming a plurality of solder balls, wherein the plurality of solder balls are respectively connected to at least part of the signal lines, and the solder balls correspond to the signal lines one by one.

[0093] For example, Fig.15 As shown, the chip packaging method includes:

[0094] Step S100: Provide a flexible substrate, including a first sub-section, a second sub-section and at least one bending section, wherein the bending section connects the first sub-section and the second sub-section, and the third sub-surface of the bending section respectively connects the first sub-surface of the first sub-section and the second sub-surface of the second sub-section to form a first surface of the flexible substrate.

[0095] Step S200: Dispose at least two chips on the first surface of the flexible substrate respectively.

[0096] Step S300: forming a rewiring layer on a first surface of the flexible substrate, wherein the rewiring layer is electrically connected to at least two chips.

[0097] Step S400a: forming a plurality of solder balls, wherein the plurality of solder balls are respectively connected to at least part of the signal lines, and the solder balls correspond to the signal lines one by one. For example, the solder balls can be made of tin, tin-silver, copper+tin-silver, copper+nickel+tin-silver, etc.

[0098] Step S400: bending the flexible substrate at the bending portion.

[0099] Regarding step S100 , step S200 , step S300 , and step S400 , reference may be made to the above embodiments, and no further details are given here.

[0100] In the chip packaging method provided by at least one embodiment of the present disclosure, the step of forming a plurality of solder balls includes: forming a plurality of solder balls on a first sub-surface of a first sub-portion, or forming a plurality of solder balls on a second sub-surface of a second sub-portion.

[0101] In the chip packaging method provided by at least one embodiment of the present disclosure, the step of forming multiple solder balls includes: forming some solder balls on the first sub-surface of the first sub-section, forming the remaining solder balls on the second sub-surface of the second sub-section, and the signal lines connected to some of the solder balls are located on the first sub-surface of the first sub-section, and the signal lines connected to the remaining solder balls are located on the second sub-surface of the second sub-section.

[0102] In a chip packaging method provided by an embodiment of the present disclosure, before the step of forming solder balls, it also includes: forming a protective layer on the side of the rewiring layer away from the flexible substrate; forming openings on the surface of the protective layer away from the flexible substrate, the openings are used to accommodate solder balls, and the openings correspond to the solder balls one by one.

[0103] For example, Fig.16 As shown, the chip packaging method includes:

[0104] Step S100: Provide a flexible substrate, including a first sub-section, a second sub-section and at least one bending section, wherein the bending section connects the first sub-section and the second sub-section, and the third sub-surface of the bending section respectively connects the first sub-surface of the first sub-section and the second sub-surface of the second sub-section to form a first surface of the flexible substrate.

[0105] Step S200: Dispose at least two chips on the first surface of the flexible substrate respectively.

[0106] Step S300: forming a rewiring layer on a first surface of the flexible substrate, wherein the rewiring layer is electrically connected to at least two chips.

[0107] Step S300a: forming a protection layer on a side of the re-distribution layer away from the flexible substrate.

[0108] Step S400b: forming an opening on the surface of the protection layer facing away from the flexible substrate, wherein the opening is used to accommodate the solder balls, and the openings correspond to the solder balls one by one.

[0109] Step S400: bending the flexible substrate at the bending portion.

[0110] Regarding step S100 , step S200 , step S300 , and step S400 , reference may be made to the above embodiments, and no further details are given here.

[0111] In a chip packaging method provided by an embodiment of the present disclosure, the flexible substrate is bent at a bending portion at an angle greater than 0° and less than or equal to 180°.

[0112] In the chip packaging method provided by at least one embodiment of the present disclosure, or, the bending angle is greater than or equal to 90° and less than or equal to 180°. For example, Figure 1 As shown, the bending angle is 90°, or as Figure 7 As shown, the bending angle is 180°.

[0113] It should be noted that the bending angle is not limited to the two angles in the above examples, and the value of the bending angle includes but is not limited to 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 100°, 110°, 120°, 130°, 140°, 150°, 160°, 170°, etc. In this way, the packaging structure formed by the packaging method is bent at multiple angles, and the folded flexible substrate can be attached to each other or not, and can be applied to more application scenarios, and can be designed according to actual needs, which will not be elaborated here.

[0114] The chip packaging structure in the embodiment of the present disclosure or the chip packaging structure obtained by using the chip packaging method can be applied to electronic devices.

[0115] In an embodiment of the present disclosure, the electronic device may be an organic light emitting diode display device or the like.

[0116] For example, the electronic device in the embodiments of the present disclosure may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, or the like.

[0117] It should be noted that the embodiments of the present disclosure do not describe all structures of the above-mentioned chip packaging structure. Those skilled in the art may set other structures according to specific application scenarios.

[0118] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A chip packaging structure, characterized in that: include: A flexible substrate, comprising a first sub-portion, a second sub-portion, and a bending portion connecting the first sub-portion and the second sub-portion; a rewiring layer, located on a first sub-surface of the first sub-portion, a second sub-surface of the second sub-portion, and a third sub-surface of the bending portion, wherein the third sub-surface is respectively connected to the first sub-surface and the second sub-surface to form a first surface of the flexible substrate; as well as At least two chips are located on the first surface of the flexible substrate and in a non-bending area of ​​the flexible substrate, and the chips are electrically connected to the rewiring layer.

2. The chip packaging structure according to claim 1, characterized in that: The rewiring layer is located between at least two of the chips and the flexible substrate; or The rewiring layer is located on surfaces of at least two of the chips facing away from the flexible substrate; preferably, a recessed area is provided on the flexible substrate, and at least part of the chip is located in the recessed area.

3. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a plurality of solder balls, wherein the rewiring layer includes a plurality of signal lines, at least some of the signal lines are electrically connected to the plurality of solder balls, and the solder balls correspond to the signal lines one by one; Preferably, the first sub-section is arranged perpendicularly or parallel to the second sub-section; Preferably, the first sub-section and the second sub-section are provided in plurality, and the plurality of the first sub-sections and the second sub-sections are respectively arranged in parallel; Preferably, all of the solder balls are located on the first sub-surface of the first sub-section or the second sub-surface of the second sub-section; Preferably, part of the solder balls are located on the first sub-surface of the first sub-section, and the signal lines connected to part of the solder balls are located on the first sub-surface of the first sub-section, and the remaining part of the solder balls are located on the second sub-surface of the second sub-section, and the signal lines connected to the remaining part of the solder balls are located on the second sub-surface of the second sub-section.

4. The chip packaging structure according to claim 3, characterized in that: The chip packaging structure further includes: a dielectric layer, located between the chip and the rewiring layer, and provided with a via, a portion of the rewiring layer fills the via to form the via connection portion, and the signal line is electrically connected to the chip or the solder ball through the via connection portion; Preferably, the chip packaging structure also includes a protective layer, which is located on the surface of the rewiring layer away from the dielectric layer, and has multiple openings. The solder balls are respectively located in the openings and protrude from the protective layer, and the openings correspond one-to-one to the above solder balls.

5. A chip packaging method, characterized in that: include: Providing a flexible substrate, comprising a first sub-portion, a second sub-portion and at least one bending portion, wherein the bending portion connects the first sub-portion and the second sub-portion, and a third sub-surface of the bending portion respectively connects a first sub-surface of the first sub-portion and a second sub-surface of the second sub-portion to form a first surface of the flexible substrate; Disposing at least two chips on the first surface of the flexible substrate respectively; forming a rewiring layer on the first surface of the flexible substrate, wherein the rewiring layer is electrically connected to at least two of the chips; The flexible substrate is bent at the bending portion.

6. The chip packaging method according to claim 5, characterized in that: The step of respectively arranging at least two chips on the first surface of the flexible substrate comprises: forming a first recessed area on the first sub-surface of the first sub-portion; placing at least one of the chips in the first recessed area; forming a second recessed area on the second sub-surface of the second sub-portion; At least one of the chips is disposed in the second recessed area.

7. The chip packaging method according to claim 6, characterized in that: The step of forming a rewiring layer on the first surface of the flexible substrate, wherein the rewiring layer is electrically connected to the two chips comprises: forming a dielectric layer on a side of the chip facing away from the flexible substrate, wherein the dielectric layer forms a via hole; forming a rewiring layer on a side of the dielectric layer away from the flexible substrate, wherein a portion of the rewiring layer fills the via hole to form a via hole connection portion; The rewiring layer is patterned to form a plurality of signal lines, at least part of which is connected to the chip through the via connection portion.

8. The chip packaging method according to claim 7, characterized in that: Before the step of bending the bending portion, the method further comprises: forming a plurality of solder balls, wherein the plurality of solder balls are respectively connected to at least a portion of the signal lines, and the solder balls correspond to the signal lines one by one; Preferably, the step of forming a plurality of solder balls comprises: forming a plurality of the solder balls on the first sub-surface of the first sub-section, or forming a plurality of the solder balls on the second sub-surface of the second sub-section; Preferably, the step of forming a plurality of solder balls includes: forming part of the solder balls on the first sub-surface of the first sub-section, forming the remaining part of the solder balls on the second sub-surface of the second sub-section, and the signal lines connected to part of the solder balls are located on the first sub-surface of the first sub-section, and the signal lines connected to the remaining part of the solder balls are located on the second sub-surface of the second sub-section.

9. The chip packaging method according to claim 8, characterized in that: Before the step of forming solder balls, the following steps are also included: forming a protective layer on a side of the rewiring layer facing away from the flexible substrate; An opening is formed on the surface of the protection layer facing away from the flexible substrate. The opening is used to accommodate the solder balls, and the openings correspond to the solder balls one by one.

10. The chip packaging method according to any one of claims 5 to 9, characterized in that: The bending angle of the flexible substrate at the bending portion is greater than 0° and less than or equal to 180°; Preferably, the bending angle is 90° or 180°.

Images