Design method of high-speed dual-channel parallel 16b18b encoder based on HDMI2.1 protocol

Abstract

The invention provides a design method of a high-speed two-channel parallel 16b18b encoder based on an HDMI2.1 protocol, and the method comprises the steps: carrying out the pre-analysis and calculation of a 16b18b encoding table, obtaining an optimized code table, designing a control module based on a BMG, replacing a conventional 9b / 7b encoding module and an RD calculation module, and carrying out the design of a high-speed two-channel parallel 16b18b encoder based on the HDMI2.1 protocol. Therefore, the 16b18b coding module can output a result in one clock delay. Besides, a dual-channel parallel redundancy encoder architecture is designed based on the novel 16b18b encoding module, internal RD dependence is eliminated, real parallel work is realized, and internal work clock frequency multiplication operation is not needed. And after 32-bit data passes through the improved double-channel 16b18b encoder, 36-bit coded data can be output. Compared with the prior art, the method has the advantages that 1) the clock frequency required by the interior of the encoder is reduced, so that the encoder works more stably; 2) under the clock frequency of 400 MHz, the coding rate can reach 14.4 Gbps; and 3) the coding module saves the intermediate calculation process and simplifies the development difficulty.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, in particular to a design method of a high-speed dual-channel parallel 16b18b encoder based on an HDMI2.1 protocol, which is suitable for encoding HDMI2.1 video signals. Background Art

[0002] With the popularity of 4K and 8K ultra-high-definition TVs, high dynamic range (HDR) content, and higher refresh rates (such as 120Hz), the bandwidth limitations of the original HDMI 2.0 standard began to emerge. In order to support these new technological trends, the HDMI Forum launched the HDMI 2.1 standard in 2017. Compared with HDMI2.0, its transmission rate has been greatly improved, from 18Gbps to 48Gbps. Whether it is HDMI 2.1 or HDMI 2.0, such high-speed transmission protocols must consider some problems in the information transmission process when designing, such as electromagnetic interference, clock offset, and DC balance. In a serial data transmission system, continuous "1" or "0" on the data transmission line will cause errors in the serial transmission line. In this case, a coding with no DC or only a constant DC component is required. Before HDMI2.1, 8b10b encoding and decoding were used, while HDMI2.1 uses 16b18b encoding and decoding.

[0003] There are usually two ways to implement a 16b18b encoder: one is based on a lookup table, and the other is based on a combination of logical codes. The first implementation is relatively simple, but it occupies a large chip area and is not suitable for encoders with large code tables. The performance of the encoder will be affected by data reading delays. The second implementation is more complicated, and the final output data may have severe jitter, resulting in unstable encoder operation. At present, more research and improvement work has been done on method one than method two.

[0004] In order to increase the encoding rate of the encoder, most encoders are designed as multi-channel encoders. However, general multi-channel encoders do not work completely in parallel, because the operation of a certain encoding module often depends on the RD value output by the encoding module last time. Therefore, the multiple channel encoding modules inside the multi-channel encoder will depend on each other, resulting in a large delay. To address this problem, the operating clock frequency of the multi-channel encoder is usually higher than the clock frequency of the data input. Because the frequency of the internal working clock is several times the frequency of the external data clock, the encoder allows multi-channel data to be transmitted. However, this operation of multiplying the working clock is limited by chip performance and is not suitable for larger and more complex 16b18b encoding and decoding.

[0005] In order to truly realize a low-latency multi-channel parallel encoder in engineering applications, it is necessary to solve the delay problem caused by the strong dependence of the encoding and RD changes of the traditional encoder on the previous RD. Secondly, it is necessary to overcome the delay problem caused by the RD dependence between channels in the multi-channel encoder. Summary of the invention

[0006] The purpose of the present invention is to provide a design method for a high-speed dual-channel parallel 16b18b encoder, aiming to solve the 16b18b encoding problem of the new HDMI2.1 protocol signal transmission, and to implement a 32-bit data parallel input encoder on an existing FPGA using a lookup table for encoding.

[0007] The design method of the high-speed dual-channel parallel 16b18b encoder based on the HDMI2.1 protocol of the present invention includes a novel 16b18b encoding module for encoding table optimization, encoding table storage optimization, and fast RD generation, and includes the following steps:

[0008] 1. A design method for a high-speed dual-channel parallel 16b18b encoder based on the HDMI2.1 protocol, comprising the following steps:

[0009] Step 1, in the dual-channel parallel redundant 16b18b encoding method, a new 16b18b encoding module generated by fast RD is placed in channel 1 of the dual-channel encoder; two new 16b18b encoding modules generated by fast RD are placed in channel 2 of the dual-channel encoder; channel 1 is used to receive the upper 16 bits of the incoming 32-bit data, and channel 2 is used to receive the lower 16 bits of the incoming 32-bit data;

[0010] Step 2, define RD+ as 1'b1 value; define RD- as 1'b0 value, the two encoding modules of channel 2 can be named RD- encoding module and RD+ encoding module, and input RD- and RD+ signals to them respectively;

[0011] Step 3: After a delay, the three encoding modules in the two channels simultaneously output new RD values ​​and 18-bit data. The RD output by the encoding module of channel 1 is used as the selection condition for the output of the encoding module of channel 2: if the RD value output by the encoding module of channel 1 is RD+, the RD+ encoding module in channel 2 is selected as the data outputter of the channel; if the RD value output by the encoding module of channel 1 is RD-, the RD- encoding module in channel 2 is selected as the data outputter of the channel;

[0012] Step 4: store the RD data of the data outputter in channel 2 into the global RD register, and combine its output 18-bit data with the 18-bit data output by the encoding module of channel 1 into a 36-bit data as the final encoded data output of the overall system.

[0013] The new 16b18b encoding module generated by fast RD is designed based on the storage optimized encoding table and uses a lookup table for encoding. It includes a BMG data reading module, a data flag selection module, and a coding transformation calculation module, which includes the following steps:

[0014] Step 1: After the optimized code table is stored in the RAM storage space created by the Block Memory Generator, the BMG data reading module reads data from the storage space according to the enable signal and input data, and then passes the data to the data flag selection module and the coding transformation calculation module;

[0015] Step 2: After inputting 16-bit data, use the 16-bit data as the value address of BMG to obtain 22-bit data from RAM;

[0016] Step 3: After receiving the 22-bit data from the BMG data reading module, the data flag selection module selects each flag in the 22-bit data according to the current RD value;

[0017] Step 4: After receiving the flag and data, the coding transformation calculation module performs transformation calculation on the 10-bit data and the 8-bit data respectively according to the flag;

[0018] Step 5. Finally, the 18-bit data and the new RD value are outputted by combining the 10-bit data and the 8-bit data.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The 16b18b encoder can complete 38-bit data output after one clock delay, which greatly reduces the working clock frequency required by the encoder;

[0021] 2. The encoder is simple in design. Under 400MHz clock conditions, the encoder rate can reach 14.4Gbps;

[0022] 3. The new coding table breaks the RD dependency of coding and reduces the calculation steps in the coding process;

[0023] 4. The new coding table after storage optimization effectively reduces the storage requirement of the code table. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the design framework of a dual-channel parallel redundant encoder

[0025] Figure 2 Schematic diagram of the working process of dual-channel parallel redundant encoder

[0026] Figure 3Schematic diagram of the design framework of traditional single-channel encoder and multi-channel encoder

[0027] Figure 4 Schematic diagram of the design framework of the new 16b18b encoding module for fast RD generation

[0028] Figure 5 Schematic diagram of the workflow of the new 16b18b encoding module generated for fast RD DETAILED DESCRIPTION

[0029] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings.

[0030] The design method of high-speed dual-channel parallel 16b18b encoder based on HDMI2.1 protocol is shown in the design block diagram. Figure 1 As shown, its workflow is as follows Figure 2 As shown, it includes the following steps:

[0031] Step 1: When 32-bit data is input, it first passes through the data splitting module and is divided into two 16-bit data. The first 16-bit data is transmitted to the encoding module of channel one, and the second 16-bit data is transmitted to the encoding module of channel two;

[0032] Step 2: In view of the fact that each channel in a traditional multi-channel encoder depends on the RD value of the previous channel, and the RD value has only two cases, two new 16b18b encoding modules are placed in channel 2, and fixed RD- and RD+ are input to these two encoding modules respectively. In this way, the two encoding modules of channel 2 do not depend on the RD result of the encoding module of channel 1;

[0033] Step 3: After a clock delay, the three encoding modules output the results at the same time. Then, the RD value output by the encoding module of channel 1 is used to determine which encoding module in channel 2 should be used. If the RD value output by channel 1 is RD-, the result output by the RD- encoding module in channel 2 is selected; if the RD value output by channel 1 is RD+, the result output by the RD+ encoding module in channel 2 is selected;

[0034] Step 4: Input the RD value of channel 2 into the global RD register. At the beginning of the next round of encoding, the value in the RD register will be input into the encoding module of channel 1, and the dual-channel parallel 16b18b encoding will be completed in a cycle.

[0035] Traditional 16b18b encoding modules such as Figure 3 As shown in (a), it includes a 9b encoding module, a 7b encoding module and two RD calculation modules. The operation of the second RD calculation module of the encoding module depends on the RD value output by the first RD calculation module

[21] . Figure 3 As shown in (b), the operation of each encoding module and RD calculation module depends on the output of the encoder RD of another channel. This dependency ensures the balance of "0" and "1" in the encoded data stream, but also leads to an increase in the encoder clock delay.

[0036] In order to save the RD calculation step of the 16b18b encoding module, the encoding table needs to be optimized. The optimization steps are as follows:

[0037] Step 1: Optimize the encoding table to save encoding steps:

[0038] 1) There are 65536 possible 16-bit input data, and each input depends on the current RD state to determine the corresponding output code. Each encoding calculation requires splitting 16 bits into 9 bits and 7 bits, and then encoding according to the 9b10b code table and 7b8b code table. After each encoding, an RD calculation is required. These steps cause the encoder to have a high clock delay;

[0039] 2) According to the 16b18b encoding principle, the input data, output data and RD transformation are matched one by one in advance to form a coding table as shown in Table A, with a total of 65536 entries, each of which corresponds to two output data. The output data bit width of a single column is 19 bits, of which the lower 18 bits [17:0] of any output data are the encoded data, and the highest bit is the flag bit, indicating that the encoder needs to be updated to the RD value corresponding to the flag bit after selecting the encoding;

[0040] Table A Coding table with RD auxiliary information

[0041]

[0042] 3) The 16b18b encoder implemented based on the coding table saves the process of calculating the 9b coding, 7b coding and the intermediate RD value, and can directly output the 18b coding and the encoded RD value after inputting the 16b data.

[0043] Step 2: Reduce the storage space required for the encoding table:

[0044] 1) The coding table described in step 1 is still a code table based on theoretical construction. Although the coding table saves multiple calculation steps of the coding module, it occupies 2.375Mb of storage space in actual development;

[0045] 2) In order to reduce storage requirements, by analyzing the 18-bit codes output by RD- and RD+, it can be found that after splitting the 18-bit code into 10b and 8b data, the 10b data of RD- and the 10b data of RD+ have the same or opposite relationship, and the 8b data has a similar pattern. Therefore, two 1-bit flags can be used to indicate this same or opposite relationship;

[0046] 3) Use 0 to indicate the same, and 1 to indicate the opposite. The final optimized code table is shown in Table B. Each table entry has 22 bits of data, of which the 21st bit is recorded as flag10b and the 20th bit is recorded as flag8b, which respectively mark whether the 10b and 8b data need to be inverted; the 19th bit is recorded as RD+_new, and the 18th bit is recorded as RD-_new. If the current RD value is RD+, RD+_new is selected as the new RD output of the encoding module; otherwise, RD-_new is selected. The remaining 18 bits [17:0] are used as temporary output data, and the bit segment [17:8] is recorded as temp10b as temporary 10b output data, and the bit segment [7:0] is recorded as temp8b as temporary 8b output data.

[0047] Table B stores the optimized encoding table with RD auxiliary information

[0048]

[0049] The design block diagram of the new 16b18b encoding module with fast RD generation in the high-speed dual-channel parallel 16b18b encoder design method is shown in the figure. Figure 4 As shown, the coding module workflow is as follows Figure 5 As shown, it includes the following steps:

[0050] Step 1: After the optimized code table is stored in the RAM storage space created by the Block Memory Generator, the BMG data reading module reads data from the storage space according to the enable signal and input data, and then passes the data to the data flag selection module and the coding transformation calculation module;

[0051] Step 2: After inputting 16-bit data, use the 16-bit data as the value address of BMG to obtain 22-bit data from RAM;

[0052] Step 3: After receiving the 22-bit data from the BMG data reading module, the data flag selection module selects each flag in the 22-bit data according to the current RD value;

[0053] Step 4: After receiving the flag and data, the coding transformation calculation module performs transformation calculation on the 10-bit data and the 8-bit data respectively according to the flag;

[0054] Step 5. Finally, the 18-bit data and the new RD value are outputted by combining the 10-bit data and the 8-bit data.

Claims

1. A design method for a high-speed dual-channel parallel 16b18b encoder based on the HDMI2.1 protocol, comprising the following steps: Step 1, in the dual-channel parallel redundant 16b18b encoding method, a new 16b18b encoding module generated by fast RD is placed in channel 1 of the dual-channel encoder; two new 16b18b encoding modules generated by fast RD are placed in channel 2 of the dual-channel encoder; channel 1 is used to receive the upper 16 bits of the incoming 32-bit data, and channel 2 is used to receive the lower 16 bits of the incoming 32-bit data; Step 2, define RD+ as 1'b1 value; define RD- as 1'b0 value, name the two encoding modules of channel 2 as RD- encoding module and RD+ encoding module, and input RD- and RD+ signals to them respectively; Step 3: After a delay, the three encoding modules in the two channels simultaneously output new RD values ​​and 18-bit data. The RD output by the encoding module of channel 1 is used as the selection condition for the output of the encoding module of channel 2: if the RD value output by the encoding module of channel 1 is RD+, the RD+ encoding module in channel 2 is selected as the data outputter of the channel; if the RD value output by the encoding module of channel 1 is RD-, the RD- encoding module in channel 2 is selected as the data outputter of the channel; Step 4: store the RD data of the data outputter in channel 2 into the global RD register, and combine its output 18-bit data with the 18-bit data output by the encoding module of channel 1 into a 36-bit data as the final encoded data output of the overall system.

2. The design method of a high-speed dual-channel parallel 16b18b encoder based on the HDMI2.1 protocol according to claim 1, characterized in that: Includes a new 16b18b encoding module for fast RD generation, The new 16b18b encoding module generated by fast RD modifies the traditional 9b encoding module, 7b encoding module and RD calculation module into BMG data reading module, data mark selection module and encoding transformation calculation module; The new 16b18b encoding module generated by fast RD will receive 16-bit input data. There are 65536 possible 16-bit input data. Each input depends on the current RD state to determine the corresponding output encoding. In order to reduce the delay of the encoding module, according to the 16b18b encoding principle, the input data, output data and RD transformation are matched one by one in advance to form a new encoding table, which omits the calculation in the middle of the encoding module and directly outputs the final encoding result and the new RD value; In order to reduce the storage requirements of the coding table, the 18-bit codes output by RD- and RD+ are split into 10b and 8b data respectively for analysis. The 10b data of RD- and the 10b data of RD+ have the same or opposite relationship, and the 8b data also has the same rule. Two 1-bit flags are used to indicate this same or opposite relationship, and finally a storage-optimized code table is formed; Each entry in the optimized encoding table has 22 bits of data, of which the 21st bit is recorded as flag10b and the 20th bit is recorded as flag8b, which respectively mark whether the 10b and 8b data need to be inverted; The 19th bit is recorded as RD+_new, and the 18th bit is recorded as RD-_new. If the current RD value is RD+, RD+_new is selected as the new RD output of the encoding module; otherwise, RD-_new is selected. The remaining 18 bits [17:0] are used as temporary output data, and the bit segment [17:8] is recorded as temp10b as temporary 10b output data, and the bit segment [7:0] is recorded as temp8b as temporary 8b output data.

3. The design method of a high-speed dual-channel parallel 16b18b encoder based on the HDMI2.1 protocol according to claim 1, characterized in that: Two new 16b18b encoding modules with fast RD generation are placed in channel 2 to break the RD dependency between channels in the traditional multi-channel parallel encoding method; After resolving the RD dependency between channels, there is no need to multiply the operating clock frequency within the encoder, so that the maximum data clock frequency can reach several times that of a common encoder.

4. The novel 16b18b encoding module for fast RD generation according to claim 2, characterized in that: The following steps are included: Step 1: After the optimized code table is stored in the RAM storage space created by the Block Memory Generator, the BMG data reading module reads data from the storage space according to the enable signal and input data, and then passes the data to the data flag selection module and the coding transformation calculation module; Step 2: After inputting 16-bit data, use the 16-bit data as the value address of BMG to obtain 22-bit data from RAM; Step 3: After receiving the 22-bit data from the BMG data reading module, the data flag selection module selects each flag in the 22-bit data according to the current RD value; Step 4: After receiving the flag and data, the coding transformation calculation module performs transformation calculation on the 10-bit data and the 8-bit data respectively according to the flag; Step 5. Finally, the 18-bit data and the new RD value are outputted by combining the 10-bit data and the 8-bit data.

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