Test circuit, test system and storage system

Abstract

The invention discloses a test circuit, a test system and a storage system. The test circuit comprises an asynchronous control module which is configured to receive a plurality of groups of initialization address information; the logical algorithm vector generation module is coupled with the asynchronous control module, asynchronously acquires the plurality of groups of initialization address information from the asynchronous control module, processes each group of initialization address information to asynchronously output a plurality of groups of test address information, and transmits the test address information to the asynchronous control module; each group of test address information corresponds to one group of initialization address information; and the error information storage module is configured to receive test data information responding to each group of test address information. The test circuit, the test system and the storage system can shorten the test speed of the chip test system.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor and integrated circuit technology, and in particular to a test circuit, a test system and a storage system. Background Art

[0002] A chip tester is a device used to detect the functions and performance of integrated circuits (ICs) and other semiconductor devices. Chip testers can use different technologies to implement tests according to different application requirements, including but not limited to tests for microcontrollers, field programmable gate arrays (FPGAs), single-chip microcomputers, etc. as core control units. In recent years, there have been many new technical trends in chip testers for high-density and complex function integrated circuits, including the following technical points.

[0003] Embedded test technology, with the increasing complexity of system-on-chip (SoC), traditional test methods are no longer applicable. Embedded test technology allows the integration of test functions in the chip design stage, which can not only improve product quality, but also significantly shorten the time of system verification, detection and debugging.

[0004] Low power design,As integrated circuits develop towards ultra-deep submicron technology, traditional dynamic power consumption has become a major challenge.,The low power design idea is achieved by reducing the number of circuit node flips during the test,,which is particularly important for maintaining low power consumption while improving fault coverage.

[0005] Parallel testing and test scheduling,In order to deal with the long test time and resource conflicts of high-density integrated circuits, parallel testing technology and effective test scheduling algorithms are used.,These technologies can reasonably allocate test resources and reduce the overall test time while ensuring test efficiency.

[0006] However, the test speed of existing chip test systems still needs to be improved. Summary of the invention

[0007] The main purpose of the present invention is to provide a test module, a test system and a storage system, aiming to shorten the test speed of the chip test system.

[0008] To achieve the above-mentioned purpose, the technical solution of the present invention proposes a test circuit, including: an asynchronous control module, configured to receive several groups of initialization address information; a logic algorithm vector generation module, coupled to the asynchronous control module, asynchronously obtaining the several groups of initialization address information from the asynchronous control module, processing each group of the initialization address information, and asynchronously outputting several groups of test address information, each group of the test address information corresponds to a group of the initialization address information; an error information storage module, configured to receive test data information in response to each group of the test address information.

[0009] In some implementations, the number of the several groups of initialization address information is N; the several groups of initialization address information include the i-th group of initialization address information and the i+1-th group of initialization address information, wherein i and N are natural numbers, and i+1≤N; the logic algorithm vector generation module is configured to sequentially obtain the N groups of initialization address information from the asynchronous control module, process each group of the initialization address information, and sequentially output test address information corresponding to each group of initialization address information, including: obtaining the i-th group of initialization address information from the asynchronous control module, processing the i-th group of initialization address information, and outputting the i-th group of test address information; after outputting the i-th test address information, obtaining the i+1-th group of initialization address information from the asynchronous control module, processing the i+1-th group of initialization address information, and outputting the i+1-th group of test address information.

[0010] In some implementations, the error information storage module is configured to: receive the i-th group of test data information when the logic algorithm vector generation module processes the i+1-th group of initialization address information.

[0011] In some implementations, the asynchronous control module also includes a logic unit and an asynchronous cache unit, the asynchronous cache unit is used to store the initialization address information, and the logic unit is configured to: output an interrupt signal when the asynchronous cache unit stores greater than or equal to M groups of initialization address information, where M is the limited number of groups of initialization address information that can be stored in the asynchronous cache unit; after the logic unit outputs the interrupt signal, the asynchronous cache unit receives the next batch of initialization address information.

[0012] In some implementations, the error information storage module is configured to: when the asynchronous control module receives the next batch of the initialization address information, output at least one group of the test data information corresponding to the M groups of initialization address information.

[0013] In some implementations, the error information storage module is also configured to receive test address information corresponding to each group of the test data information; the error information storage module also includes: an address information storage unit, coupled to the asynchronous control module, configured to receive or output the test address information; an error data storage unit, configured to receive or output test data information in response to each group of the test address information.

[0014] In some implementations, the number of the error information storage modules is at least 2, and the error information storage module is further configured to: when receiving the i+1th group of test data information and the i+1th group of test address information, output the i-th group of test data information and the i-th group of test address information.

[0015] In some implementations, the asynchronous control module further includes a latch, which is coupled to the logic algorithm vector generation module, and is configured to sequentially receive several groups of the test address information from the logic algorithm vector generation module.

[0016] In some implementations, the asynchronous control module further includes an interface unit, which is coupled to the error information storage module, and the interface unit is configured to: transmit several groups of the test address information to the error information storage module in sequence.

[0017] Correspondingly, the technical solution of the present invention also proposes a test system, comprising: a control module, configured to output several groups of initialization address information; a test circuit as described in any of the above items, coupled to the control module, configured to receive several groups of initialization address information, asynchronously process several groups of the initialization address information, so as to output test address information corresponding to each group of the initialization address information; a module to be tested, coupled to the test circuit, configured to asynchronously receive several groups of the test address information, process based on each group of the test address information, so as to asynchronously output test data information corresponding to each group of the test address information; the test circuit is also configured to feed back each group of the test data information and the corresponding test address information to the control module.

[0018] Correspondingly, the technical solution of the present invention also proposes a storage system, comprising: a control module, configured to output several groups of initialization address information; a test circuit as described in any of the above items, coupled to the control module, configured to receive several groups of initialization address information, asynchronously process several groups of the initialization address information, so as to output test address information corresponding to each group of the initialization address information; a storage module, coupled to the test circuit, configured to asynchronously receive several groups of the test address information, process based on each group of the test address information, so as to asynchronously output test data information corresponding to each group of the test address information; the test circuit is also configured to feed back each group of the test data information and the corresponding test address information to the control module.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0020] In the test circuit of the technical solution of the present application, an asynchronous control module coupled to a logic algorithm vector module is provided, so that the asynchronous control module stores multiple groups of initialization address information, so that the logic algorithm vector generation module can directly obtain the next group of initialization address information from the asynchronous control module for processing after outputting the previous group of test address information, which is beneficial to reducing the idle time of the logic algorithm vector generation module, thereby shortening the test time and improving the test efficiency. On the other hand, the error information storage module is enabled to store the previous group of test data information and the next group of test data information at the same time, so that the error information storage module can output the previous group of test data information to the control module while receiving the next group of test data information, so that the test circuit forms a data pipeline in the process from the logic algorithm vector generation module receiving the initialization address information to the error information storage module outputting the test data information, thereby reducing the idle time of each module in the test circuit, thereby shortening the test time and improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0022] Figure 1 is a schematic diagram of the structure of an embodiment of a test system;

[0023] Figure 2 is a structural diagram of a test circuit according to an embodiment of the present invention;

[0024] Figure 3 yes Figure 2 A schematic diagram of the structure of the asynchronous control module 210;

[0025] Figure 4 yes Figure 2 A schematic diagram of the structure of the error information storage module 230;

[0026] Figure 5 is a structural diagram of another test circuit according to an embodiment of the present invention;

[0027] Figure 6 is a structural schematic diagram of a test system according to an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the structure of a storage system according to an embodiment of the present application.

[0029] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0030] As described in the background art, the response time of the read and write instructions of the existing multi-cycle instruction memory still needs to be shortened.

[0031] Figure 1 The present invention is a schematic diagram of a structure of a test system embodiment, comprising:

[0032] The control module 100 is configured to output a set of initialization address information;

[0033] The test circuit 110 includes a logic algorithm vector generation module 111, coupled to the control module 100, and configured to receive the initialization address information, process the initialization address information, and then output the test address information;

[0034] The module to be tested 120 is coupled to the logic algorithm vector generating module 111, and is used to receive the test address information, and perform processing based on the test address information to output the test data information;

[0035] The test circuit 110 further includes an error information storage module 112 for receiving and storing the test data information and feeding back the test data information to the control module 100 .

[0036] In the test system, after the logic algorithm vector generation module 111 outputs the test address information, it needs to be idle (Idle) to wait for the module to be tested 120 to complete the test according to the test address information to output the test data information. After the error information storage module 112 feeds back the test data information to the control module 100, the control module 100 will send the next set of initialization address information to the logic algorithm vector generation module 111 for the next round of processing.

[0037] It can be seen that the idle time between the output of the test address information by the logic algorithm vector generation module 111 and the acquisition of the next set of initialization address information is relatively long, resulting in a mismatch between the test duration and the theoretical duration, thereby hindering the improvement of the test speed and test efficiency. Moreover, as the test complexity increases, the communication between the logic algorithm vector generation module 111 and the control module 100 becomes more frequent, and the mismatch between the theoretical duration and the actual test duration caused by the idle time of the logic algorithm vector generation module 111 is also increasing.

[0038] In order to solve the above problems, the present application embodiment proposes a test circuit, please refer to Figure 2 , Figure 2 is a structural diagram of a test circuit according to an embodiment of the present invention, comprising:

[0039] The asynchronous control module 210 is configured to receive several groups of initialization address information Init;

[0040] a logic algorithm vector generation module 220, coupled to the asynchronous control module 210, asynchronously acquiring the plurality of groups of initialization address information Init from the asynchronous control module 210, processing each group of the initialization address information Init, and asynchronously outputting a plurality of groups of test address information Addr, each group of the test address information Addr corresponding to a group of the initialization address information Init;

[0041] The error information storage module 230 is configured to receive the test data information Data in response to each set of the test address information Addr.

[0042] By setting an asynchronous control module 210 coupled to the logic algorithm vector generation module 220, the asynchronous control module 210 stores multiple groups of initialization address information Init, so that the logic algorithm vector generation module 220 can directly obtain the next group of initialization address information Init from the asynchronous control module 210 for processing after outputting the previous group of test address information Addr, which is beneficial to reducing the idle time of the logic algorithm vector generation module 220, thereby shortening the test time and improving the test efficiency. On the other hand, the error information storage module 230 can store the previous group of test data information Data and the next group of test data information Data at the same time, so that the error information storage module 230 can output the previous group of test data information Data to the control module while receiving the next group of test data information Data, so that the test circuit forms a data pipeline in the process from the logic algorithm vector generation module 220 receiving the initialization address information Init to the error information storage module 230 outputting the test data information Data, thereby reducing the idle time of each module in the test circuit, thereby shortening the test time and improving the test efficiency.

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0045] The asynchronous control module 210 includes a storage unit for receiving and storing at least two groups of initialization address information Init, so that the logic algorithm vector generation module 220 can directly obtain the next group of initialization address information Init from the asynchronous control module 210 for processing after outputting the previous group of test address information Addr. Since the logic algorithm vector generation module 220 does not need to wait for the control module to obtain and parse the test data information Data before obtaining the next group of initialization address information Init, the idle time of the logic algorithm vector generation module 220 can be reduced, thereby shortening the test time and improving the test efficiency.

[0046] The logic algorithm vector generation module 220 is used to generate a test pattern according to the acquired information to test the module to be tested. Taking the high-speed memory test as an example, the logic algorithm vector generation module 220 can provide a comprehensive functional direct access test for the embedded memory, making it easy to perform a complete functional direct access test on the embedded memory with different data widths.

[0047] The logic algorithm vector generation module 220 is used to output a test mode according to the acquired initialization configuration information and a plurality of sets of initialization address information Init, and the module to be tested coupled to the test circuit is tested according to the test mode. The initialization address information Init is used to configure the address to be tested for the module to be tested. The initialization configuration information includes various types of configuration information for configuring the initialization state of the module to be tested.

[0048] In some embodiments, the initialization address information Init includes: an initial address and an address increment. The initial address is used to point to the initial address bit in the test address information Addr; the address increment information is used to point to each actual address bit that needs to be tested after the initial address bit. The logic algorithm vector generation module 220 is used to calculate the initial address and the address increment to obtain the initial address actually used for testing, that is, the test address information Addr.

[0049] After the logic algorithm vector generation module 220 obtains the initialization configuration information, it can obtain several groups of initialization address information Init; the number of the several groups of initialization address information Init is N; the several groups of initialization address information Init include the i-th group of initialization address information Init_i and the i+1-th group of initialization address information Init_i+1, where i and N are natural numbers, and i+1≤N. In this embodiment, the number of the initialization address information Init is 2, and the several groups of initialization address information Init include the first group of initialization address information Init_1 and the second group of initialization address information Init_2.

[0050] The logic algorithm vector generation module 220 is configured to sequentially obtain the N groups of initialization address information Init from the asynchronous control module 210, process each group of the initialization address information Init, and sequentially output the test address information Addr corresponding to each group of the initialization address information Init, including:

[0051] The asynchronous control module 210 obtains the i-th group of initialization address information Init_i, processes the i-th group of initialization address information Init_i, and outputs the i-th group of test address information Addr_i;

[0052] After outputting the i-th test address information Addr_i, the i+1-th group of initialization address information Init_i+1 is obtained from the asynchronous control module 210, and after processing the i+1-th group of initialization address information Init_i+1, the i+1-th group of test address information Addr_i+1 is output.

[0053] In some embodiments, during the process in which the logic algorithm vector generation module 220 outputs the i-th group of test address information Addr_i and until the error information storage module 230 receives the i-th group of test data information Data_i, the logic algorithm vector generation module 220 obtains the i+1-th group of initialization address information Init_i+1 and processes the i+1-th group of initialization address information Init_i+1; wherein the i-th group of test data information Data_i is test data in response to the i-th group of test address information Addr_i.

[0054] Since the logic algorithm vector generation module 220 can directly obtain the i+1th group of initialization address information Init_i+1 from the asynchronous control module 210 for processing after outputting the i-th group of test address information Addr_i, the time for the logic algorithm vector generation module 220 to wait for the test data information Data to be transmitted back to the control module via the error information storage module 230 is avoided, which is beneficial to reduce the idle time of the logic algorithm vector generation module 220, thereby shortening the test time and improving the test efficiency.

[0055] In this embodiment, the logic algorithm vector generation module 220 is configured as follows:

[0056] The asynchronous control module 210 obtains the first group of initialization address information Init_1, processes the first group of initialization address information Init_1, and outputs the first group of test address information Addr_1;

[0057] After the first test address information Addr_1 is output, the second group of initialization address information Init_2 is obtained from the asynchronous control module 210, and after the second group of initialization address information Init_2 is processed, the second group of test address information Addr_2 is output.

[0058] Moreover, during the process from the logic algorithm vector generation module 220 outputting the first group of test address information Addr_1 to the time when the error information storage module 230 receives the first group of test data information Data_1, the logic algorithm vector generation module 220 obtains the second group of initialization address information Init_2 and processes the second group of initialization address information Init_2, and the first group of test data information Data_1 is the test data in response to the first group of test address information Addr_1.

[0059] The error information storage module 230 is configured to receive test data information Data in response to each set of the test address information Addr, including:

[0060] receiving the i-th group of test data information Data_i in response to the i-th group of test address information Addr_i;

[0061] The i+1th group of test data information Data_i+1 is received in response to the i+1th group of test address information Addr_i+1.

[0062] In this embodiment, the error information storage module 230 is configured to receive the first group of test data information Data_1 and the second group of test data information Data_2; the first group of test data information Data_1 is the test data of the module under test in response to the first group of test address information Addr_1; the second group of test data information Data_2 is the test data of the module under test in response to the second group of test address information Addr_2.

[0063] In some embodiments, the error information storage module 230 is further configured to: receive the i-th group of test data information Data_i when the logic algorithm vector generation module 220 processes the i+1-th group of initialization address information Init_i+1. In this embodiment, the error information storage module 230 receives the first group of test data information Data_1 when processing the second group of initialization address information Init_2.

[0064] Since the error information storage module 230 can store the i-th group of test data information Data_i and the i+1-th group of test data information Data_i+1 at the same time, the error information storage module 230 can output the previous group of test data information Data to the control module while receiving the latter group of test data information Data. Therefore, a data pipeline is formed in the process from the logic algorithm vector generation module 220 receiving the initialization address information Init to the error information storage module 230 outputting the test data information Data, which is conducive to reducing the idle time of each module in the test circuit, thereby shortening the test time and improving the test efficiency.

[0065] In some embodiments, please refer to the reference Figure 2 and Figure 3 , Figure 3 yes Figure 2 The structure diagram of the asynchronous control module 210 is shown in FIG. 2 , wherein the asynchronous control module 210 further includes: a logic unit 212, which is configured to output an interrupt signal Inter after the asynchronous control module 210 receives M groups of initialization address information Init, wherein M is a limited number of groups of the initialization address information that can be stored in the storage space of the asynchronous control module 210, wherein M is a natural number and M≥N, and wherein N is the number of groups of the initialization address information Init.

[0066] Specifically, after the asynchronous control module 210 obtains and stores M groups of initialization address information Init, the storage space of the asynchronous control module 210 is saturated; when the storage space of the asynchronous control module 210 is saturated, the logic unit 212 is used to output an interrupt signal Inter to the control unit to interrupt the control unit from outputting the initialization address information Init to the asynchronous control module 210.

[0067] In some embodiments, the asynchronous control module 210 includes an asynchronous cache unit 211, and the asynchronous cache unit 211 is used to store the initialization address information Init.

[0068] The asynchronous control module 210 is further configured to receive the next batch of initialization configuration information and N groups of initialization address information Init after the logic unit 212 outputs the interrupt signal Inter.

[0069] The error information storage module 230 is configured to output at least one of the first group of test data information Data_1 to the Mth group of test data information Data_m when the asynchronous control module 210 receives the next batch of N groups of initialization address information Init. In this embodiment, when the asynchronous control module 210 receives the next batch of 2 groups of initialization address information Init, the error information storage module 230 outputs the second group of test data information Data_2.

[0070] In some embodiments, please refer to Figure 3 The asynchronous control module 210 further includes a latch 213, which is coupled to the logic algorithm vector generation module 220, and the latch 213 is configured to sequentially receive a plurality of groups of the test address information Addr from the logic algorithm vector generation module 220.

[0071] The asynchronous control module 210 further includes an interface unit 214, which is coupled to the error information storage module 230, and is configured to sequentially transmit a plurality of groups of the test address information Addr to the error information storage module 230. In this embodiment, the interface unit 214 is coupled to the latch 213, and is used to sequentially transmit the test address information Addr received by the latch 213 to the error information storage module 230.

[0072] In some embodiments, the error information storage module 230 is further configured to receive the test address information Addr corresponding to each group of the test data information Data. Figure 4 , Figure 4 yes Figure 2 The structural diagram of the error information storage module 230 is shown in FIG. 2 , wherein the error information storage module 230 further includes:

[0073] The address information storage unit 231 is coupled to the asynchronous control module 210 and is configured to receive the test address information Addr;

[0074] The error data storage unit 232 is configured to receive the test data information Data in response to each set of the test address information Addr.

[0075] In this embodiment, the interface unit 214 is further coupled to the address information storage unit 231 for transmitting the test address information Addr received from the latch 213 to the address information storage unit 231 in sequence.

[0076] The error information storage module 230 is further configured as follows: when the address information storage unit 231 outputs the i-th group of test address information Addr_i, the error data storage unit 232 outputs the corresponding i-th group of test data information Data_i, where i and N are natural numbers, and i+1≤N, and N is the number of groups of the initialization address information Init.

[0077] In this embodiment, when the address information storage unit 231 outputs the first group of test address information Addr_1, the error data storage unit 232 outputs the corresponding first group of test data information Data_1; when the address information storage unit 231 outputs the second group of test address information Addr_2, the error data storage unit 232 outputs the corresponding second group of test data information Data_2.

[0078] The number of the error information storage modules 230 is at least 2, and the error information storage module 230 is further configured to: when receiving the i+1th group of test data information Data_i+1 and the i+1th group of test address information Addr_i+1, output the i-th group of test data information Data_i and the i-th group of test address information Addr_i.

[0079] In this embodiment, the number of the error information storage modules 230 is 2. When the second error information storage module 230 receives the second group of test data information Data_2 and the second group of test address information Addr_2, the first error information storage module 230 outputs the first group of test data information Data_1 and the first group of test address information Addr_1.

[0080] In some embodiments, please refer to Figure 5 , Figure 5 It is a structural diagram of another test circuit of an embodiment of the present invention, the test circuit also includes an interface module 206 coupled between the logic algorithm vector generation module 220 and the module to be tested, and is configured to output an interface signal Cs_n to the module to be tested according to the test address information Addr.

[0081] Since the interface signal Cs_n corresponds to the test address information Addr, the module to be tested can perform a test on the corresponding discrete address pointed to by the corresponding test address information Addr according to the interface signal Cs_n, and feed back corresponding test data information Data.

[0082] In some embodiments, the interface module 206 includes:

[0083] The timing generator 260 is configured to output a timing signal according to the control signal output by the control module;

[0084] The waveform generator 262 is coupled to the timing generator and the logic algorithm vector generation module 220, and is configured to output an address waveform signal according to the test address information Addr and the timing signal;

[0085] A driving type unit 261, coupled to the timing generator, and configured to output a driving type signal according to the timing signal;

[0086] An interface driver 263, coupled to the waveform generator 262 and the drive type unit 261, and configured to output the interface signal Cs_n according to the address waveform signal and the drive type signal;

[0087] The input signal latch 264 is coupled to the error information storage module 230 and is configured to receive and store the test data information Data, where the test data information Data is a signal output by the module under test when the module under test is tested based on the interface signal Cs_n.

[0088] In summary, by setting up an asynchronous control module 210 coupled to the logic algorithm vector generation module 220, the asynchronous control module 210 stores multiple groups of initialization address information Init, so that after the logic algorithm vector generation module 220 outputs the previous group of test address information Addr, it can directly obtain the next group of initialization address information Init from the asynchronous control module 210 for processing, which is beneficial to reducing the idle time of the logic algorithm vector generation module 220, thereby shortening the test time and improving the test efficiency.

[0089] On the other hand, the error information storage module 230 is enabled to store the previous set of test data information Data and the next set of test data information Data at the same time, so that the error information storage module 230 can output the previous set of test data information Data to the control module while receiving the next set of test data information Data, so that the test circuit forms a data pipeline in the process from the logic algorithm vector generation module 220 receiving the initialization address information Init to the error information storage module 230 outputting the test data information Data, thereby reducing the idle time of each module in the test circuit, thereby shortening the test time and improving the test efficiency.

[0090] Accordingly, the embodiment of the present invention also provides a test system, please refer to Figure 6 , Figure 6 : is a structural diagram of a test system according to an embodiment of the present application, comprising:

[0091] The control module 300 is configured to output a plurality of groups of initialization address information;

[0092] The test circuit 200 is coupled to the control module 300 and is configured to receive a plurality of sets of initialization address information Init, and asynchronously process the plurality of sets of the initialization address information Init to output test address information Addr corresponding to each set of the initialization address information Init;

[0093] The module to be tested 400 is coupled to the test circuit 200 and is configured to asynchronously receive a plurality of groups of the test address information Addr, and perform processing based on each group of the test address information Addr to asynchronously output test data information Data corresponding to each group of the test address information Addr;

[0094] The test circuit 200 is further configured to feed back each set of the test data information Data and the corresponding test address information Addr to the control module 300 .

[0095] The following is a detailed description with reference to the accompanying drawings.

[0096] The test circuit is as follows Figures 2 to 5 And related embodiments are described, which will not be repeated here.

[0097] The control module 300 is a central processing unit (CPU) or an enhanced RISC (Reduced Instruction Set Computing) architecture processor (Advanced RISC Machines, ARM).

[0098] The module to be tested 400 includes a field programmable gate array (FPGA) or a memory array, etc.; the memory array includes a phase change memory (PCM).

[0099] The control module 300 is used to output the initialization address information Init, and the test circuit 200 processes the initialization address Init into the test address information Addr and outputs it to the module to be tested 400; after the module to be tested 400 performs a test according to the test address information Addr, it outputs the test data information Data, and the test data information Data is fed back to the control module 300 through the test circuit 200, so that the control module 300 can parse the test data information Data to obtain the test result.

[0100] In this embodiment, when the test circuit 200 outputs the test data information Data, it also outputs the corresponding test address information Addr, so that the control module 300 can perform analysis based on the test data information Data and the test address information Addr at any time.

[0101] Correspondingly, the embodiment of the present invention also proposes a storage system, please refer to Figure 7 , Figure 7 A schematic diagram of a storage system according to an embodiment of the present application includes:

[0102] The control module 300 is configured to output a plurality of groups of initialization address information;

[0103] The test circuit 200 is coupled to the control module 300 and is configured to receive a plurality of sets of initialization address information Init, and asynchronously process the plurality of sets of the initialization address information Init to output test address information Addr corresponding to each set of the initialization address information Init;

[0104] The storage system 500 is coupled to the test circuit 200 and is configured to asynchronously receive a plurality of groups of the test address information Addr, and perform processing based on each group of the test address information Addr to asynchronously output the test data information Data corresponding to each group of the test address information Addr;

[0105] The test circuit 200 is further configured to feed back each set of the test data information Data and the corresponding test address information Addr to the control module 300 .

[0106] The following is a detailed description with reference to the accompanying drawings.

[0107] The test circuit is as follows Figures 2 to 5 And related embodiments are described, which will not be repeated here.

[0108] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A test circuit, characterized in that: include: The asynchronous control module is configured to receive a plurality of groups of initialization address information; a logic algorithm vector generation module, coupled to the asynchronous control module, asynchronously acquiring the plurality of groups of initialization address information from the asynchronous control module, processing each group of the initialization address information, and asynchronously outputting a plurality of groups of test address information, each group of the test address information corresponding to a group of the initialization address information; The error information storage module is configured to receive test data information in response to each group of test address information.

2. The test circuit according to claim 1, characterized in that: The number of the several groups of initialization address information is N; the several groups of initialization address information include the i-th group of initialization address information and the i+1-th group of initialization address information, wherein i and N are natural numbers, and i+1≤N; The logic algorithm vector generation module is configured to sequentially obtain N groups of initialization address information from the asynchronous control module, process each group of the initialization address information, and sequentially output test address information corresponding to each group of the initialization address information, including: Acquire the i-th group of initialization address information from the asynchronous control module, process the i-th group of initialization address information, and output the i-th group of test address information; After outputting the i-th test address information, the i+1-th group of initialization address information is obtained from the asynchronous control module, and after processing the i+1-th group of initialization address information, the i+1-th group of test address information is output.

3. The test circuit according to claim 2, characterized in that: The error information storage module is configured to receive the i-th group of test data information when the logic algorithm vector generation module processes the i+1-th group of initialization address information.

4. The test circuit according to claim 1, characterized in that: The asynchronous control module further includes a logic unit and an asynchronous cache unit, wherein the asynchronous cache unit is used to store the initialization address information, and the logic unit is configured as follows: When the asynchronous cache unit stores more than or equal to M groups of initialization address information, an interrupt signal is output, where M is a limited number of groups of the initialization address information that can be stored in the asynchronous cache unit; After the logic unit outputs the interrupt signal, the asynchronous cache unit receives the next batch of initialization address information.

5. The test circuit according to claim 4, characterized in that: The error information storage module is configured to output at least one group of the test data information corresponding to the M groups of initialization address information when the asynchronous control module receives the next batch of initialization address information.

6. The test circuit according to claim 1, characterized in that: The error information storage module is further configured to receive test address information corresponding to each group of the test data information; The error information storage module also includes: An address information storage unit, coupled to the asynchronous control module, configured to receive or output the test address information; The error data storage unit is configured to receive or output test data information in response to each set of the test address information.

7. The test circuit according to claim 6, characterized in that: The number of the error information storage modules is at least 2, and the error information storage module is further configured to output the i-th group of test data information and the i-th group of test address information when receiving the i+1-th group of test data information and the i+1-th group of test address information.

8. The test circuit according to claim 1, characterized in that: The asynchronous control module further includes a latch, which is coupled to the logic algorithm vector generation module and is configured to sequentially receive a plurality of groups of the test address information from the logic algorithm vector generation module.

9. The test circuit according to claim 8, characterized in that: The asynchronous control module further includes an interface unit, which is coupled to the error information storage module, and the interface unit is configured as follows: A plurality of groups of the test address information are sequentially transmitted to the error information storage module.

10. A testing system, characterized in that: include: A control module is configured to output a plurality of groups of initialization address information; The test circuit according to any one of claims 1 to 9, coupled to the control module, and configured to receive a plurality of groups of initialization address information, asynchronously process the plurality of groups of the initialization address information, and output test address information corresponding to each group of the initialization address information; A module to be tested, coupled to the test circuit, and configured to asynchronously receive a plurality of groups of the test address information, perform processing based on each group of the test address information, and asynchronously output test data information corresponding to each group of the test address information; The test circuit is further configured to feed back each set of the test data information and the corresponding test address information to the control module.

11. A storage system, characterized in that: include: A control module is configured to output a plurality of groups of initialization address information; The test circuit according to any one of claims 1 to 9, coupled to the control module, and configured to receive a plurality of groups of initialization address information, asynchronously process the plurality of groups of the initialization address information, and output test address information corresponding to each group of the initialization address information; a storage module, coupled to the test circuit, configured to asynchronously receive a plurality of groups of the test address information, perform processing based on each group of the test address information, and asynchronously output test data information corresponding to each group of the test address information; The test circuit is further configured to feed back each set of the test data information and the corresponding test address information to the control module.

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