Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell which comprises a silicon substrate, the surface of at least one side of the silicon substrate is provided with a micro-suede of a sand dune-like structure, and a tunneling oxide layer is laminated on the micro-suede; the sand dune-like structure is provided with at least one vertex, and 3-6 curved side edges pass through each vertex; and the side edges are sunken towards the inner part of the sand dune-like structure. The invention also provides a preparation method of the solar cell. According to the solar cell, the surface reflectivity of the solar cell can be effectively reduced, and the characteristics of surface passivation, surface contact and the like are improved, so that the transmission efficiency and the collection efficiency of carriers are improved, and the short-circuit current density and the conversion efficiency of the solar cell are further improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaics, and specifically to a solar cell and a method for preparing the same, as well as a photovoltaic module. Background Art

[0002] Texturing the surface of silicon wafers is an important step in the manufacture of crystalline silicon solar cells. A good velvet structure can not only reduce the reflectivity of sunlight and increase light absorption, but also improve surface passivation and electrode contact properties, thereby improving the collection efficiency of carriers. It is known to those in the field that a polished surface will lead to more full-band spectral reflections, which will further escape through the front surface of the silicon wafer, causing serious optical losses and reducing battery efficiency. Although the velvet surface structure has a gain in battery optics compared to the polished surface structure, there is also a problem of mismatch with the passivation contact structure, which affects the further improvement of battery performance. Summary of the invention

[0003] In summary, the textured surface of the prior art cannot meet the requirements of optical absorption and passivation effect under the structure of SiOx / n-poly. In view of the problems existing in the prior art, the present application provides a solar cell with a micro-textured surface on a semiconductor substrate.

[0004] Specifically, this application involves the following aspects:

[0005] The present application provides a solar cell, which includes a silicon substrate, at least one side of which has a micro-suede surface with a dune-like structure, and a tunneling oxide layer is stacked on the micro-suede surface;

[0006] The dune-like structure has at least one vertex, and each vertex has 3 to 6 curved side edges;

[0007] The side edges are recessed toward the interior of the dune-like structure.

[0008] Furthermore, a doped polysilicon layer is stacked on the tunnel oxide layer.

[0009] Furthermore, the height difference between the top and bottom of the dune-like structure is 0.1 to 5 μm, preferably 0.5 to 2 μm; and / or

[0010] The curvature radius of the lowest point of the side edge is 0.1 to 20 μm; and / or

[0011] The included angle between two adjacent side edges passing through the same vertex of the dune-like structure is 40 to 160°, preferably 40 to 85°;

[0012] Furthermore, the specific surface area of ​​the micro-suede surface is 1.1 to 1.4; and / or

[0013] The reflectivity of the micro-suede surface is 10% to 45%.

[0014] Furthermore, the height difference between the vertices of two adjacent dune-like structures is 0.1 to 4 μm; and / or

[0015] The height difference between the bottom points of two adjacent dune-like structures is 0 to 2 μm;

[0016] Furthermore, the thickness of the tunnel oxide layer is 0.2-2 nm.

[0017] Furthermore, the thickness of the doped polysilicon layer is 50-200 nm; and / or

[0018] The doping concentration of polysilicon in the doped polysilicon layer is 0.05E20-9E20 / cm 3 , preferably 0.1E20~3E20 / cm 3 .

[0019] Furthermore, a transparent conductive layer is stacked on the doped polysilicon layer;

[0020] Preferably, the thickness of the transparent conductive layer is 20 to 200 nm, preferably 35 to 65 nm;

[0021] Preferably, the surface reflectivity of the transparent conductive layer on a side facing away from the silicon substrate is 8% to 18%.

[0022] Further, the surface of the silicon substrate has a first area and a second area;

[0023] The first region has the micro-texture surface, and a tunneling oxide layer and a doped polysilicon layer are sequentially stacked on the micro-texture surface;

[0024] A second semiconductor layer is stacked on the second region;

[0025] The first areas and the second areas are alternately distributed;

[0026] Preferably, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped layer stacked on a surface of the intrinsic amorphous silicon layer facing away from the silicon substrate, wherein the second doped layer is a doped amorphous silicon layer, a doped microcrystalline silicon layer or a doped nanocrystalline silicon layer.

[0027] The present application also provides a method for preparing a solar cell, which comprises:

[0028] The silicon substrate is textured to obtain a micro-texture surface with a dune-like structure;

[0029] forming a tunneling oxide layer on the micro-fleece surface;

[0030] Among them, the method for texturing a silicon substrate includes: alkaline polishing to prepare a velvet surface with a pyramid structure, and then acid treatment with a mixed solution of nitric acid and hydrofluoric acid to obtain a micro-velvet surface with a dune-like structure, wherein the volume ratio of hydrofluoric acid to nitric acid is 1:8-20.

[0031] Furthermore, the preparation method of the present application further comprises: forming a doped polysilicon layer on a surface of the tunnel oxide layer on a side away from the silicon substrate.

[0032] Furthermore, the concentration of the nitric acid used is 30% to 50%; and / or

[0033] The concentration of hydrofluoric acid used is 1% to 5%; and / or

[0034] The acid treatment temperature is 10 to 30°C, preferably 10 to 20°C; and / or

[0035] The acid treatment time is 10 to 1500 s, preferably 100 to 800 s.

[0036] Furthermore, after the acid treatment, the method further comprises the step of washing with potassium hydroxide and hydrogen peroxide; and / or

[0037] The concentration of potassium hydroxide is 0.1% to 1%, and the concentration of hydrogen peroxide is 1% to 5%; and / or

[0038] The cleaning temperature is 25-80°C and the cleaning time is 60-300s.

[0039] Further, a tunneling oxide layer is deposited on the micro-suede surface by chemical vapor deposition or physical vapor deposition;

[0040] Preferably, the chemical vapor deposition method is a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method;

[0041] Preferably, the deposition temperature of the low pressure chemical vapor deposition method is 400-700° C., preferably 500-600° C., and / or the deposition time is 1-50 min, preferably 5-25 min.

[0042] The present application also provides a photovoltaic assembly, which includes any of the aforementioned solar cells, wherein the solar cells are electrically connected into a solar cell string in the form of a whole piece or multiple pieces.

[0043] At least one side of the silicon substrate of the solar cell provided by the present application has a micro-velvet surface with a dune-like structure, and a tunneling oxide layer is stacked on the micro-velvet surface. Compared with the polished structure, firstly, the micro-velvet surface can effectively reduce the reflection loss of the available spectrum, increase light absorption, and improve the short-circuit current density; secondly, the surface area of ​​the micro-velvet surface is larger, and the contact area with the tunneling oxide layer is larger, which can not only effectively increase the carrier transmission path, but also the dune-like structure is more conducive to the tunneling effect of the carrier, reduce the transmission loss of the carrier, and improve the filling factor; combined with the tunneling passivation contact structure formed by doping polycrystalline silicon, it can effectively improve the passivation effect of the silicon substrate surface, improve the minority carrier lifetime and majority carrier collection efficiency, and increase the open circuit voltage, thereby improving the photoelectric conversion efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 The figure is a schematic diagram of the structure of a hybrid back contact battery in the prior art.

[0045] Figure 2 A schematic diagram of the structure of a hybrid back-contact battery according to a specific embodiment of the present application.

[0046] Figure 3(A) to Figure 3(D) They are schematic structural diagrams of a micro-suede surface according to a specific implementation scheme of the present application.

[0047] Figure 4 : is the reflectivity curve of the silicon substrate surface structure formed by different processes (the reflectivity value is the weighted average value of the reflectivity curve and the AM1.5G spectrum).

[0048] Figure 5 SEM images of the surface structure of a silicon substrate formed using different processes (the first to fourth columns are a top view magnified 50,000 times, a top view magnified 5,000 times, a stereoscopic view magnified 10,000 times, and a side view magnified 20,000 times, respectively).

[0049] Explanation of symbols

[0050] 1 Anti-reflection layer 2 Third passivation layer 3 Tunneling oxide layer 4 Doped polysilicon layer

[0051] 5 intrinsic amorphous silicon layer 6 second doping layer 7 transparent conductive layer 8 second electrode

[0052] 9 first electrode 10 first region 11 second region 12 Gap region DETAILED DESCRIPTION

[0053] The following is a description of the exemplary embodiments of the present application, including various details of the embodiments of the present application to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. Similarly, for clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0054] As used in this specification, "a" or "an" may mean one or more. As used in the claims, when used with the word "comprising", the word "a" or "an" may mean one or more than one.

[0055] The term "or" is used in the claims to mean "and / or" unless explicitly stated to refer only to alternatives or the alternatives are mutually exclusive, although the present disclosure supports a definition referring only to alternatives and "and / or." As used herein, "another" may mean at least a second or more.

[0056] In a first aspect, the present application provides a solar cell comprising a silicon substrate, at least one side surface of the silicon substrate having a micro-velvet surface with a dune-like structure, and a tunneling oxide layer 3 stacked on the micro-velvet surface; the dune-like structure has at least one vertex, and each vertex has 3 to 6 curved side edges; the side edges are recessed toward the interior of the dune-like structure.

[0057] In some embodiments, as shown in FIG3(A), the dune-like structure has two vertices A and A', and there are 3 to 6 curved side edges through vertex A, and there are 3 to 6 curved side edges through vertex A'. In some embodiments, as shown in FIG3(B) and FIG3(C), the dune-like structure has one vertex A, and there are 3 to 6 curved side edges through vertex A. The side edges are recessed toward the interior of the dune-like structure. The multiple side edge structures that are recessed inward can increase the number of reflections of the incident light in the dune-like structure, increase the optical path, and thus enhance light absorption.

[0058] In some embodiments, such as Figure 2 As shown, a doped polysilicon layer 4 is stacked on the tunnel oxide layer 3. The tunnel oxide layer and the doped polysilicon form a tunnel passivation contact structure, which is beneficial to the passivation effect of the silicon substrate.

[0059] The micro-velvet surface of the present application refers to a velvet surface composed of multiple dune-like structures, which is a surface different from a polished surface or a conventional pyramid velvet surface. The polished surface is composed of multiple tower bases, which include similar horizontal end faces and side surfaces. The polished surface will cause more long-wave spectral reflections, reduce the photoelectric conversion efficiency of the battery, and has a small specific surface area and a small contact area with the passivation layer, which is not conducive to the tunneling effect of carriers. The conventional velvet structure is composed of multiple pyramids, which are square pyramid structures. Although they can increase the absorption of light to a certain extent, they are not conducive to the uniform deposition of the film layer and have a poor passivation effect. The micro-velvet surface of the present application refers to a plurality of dune-like structures, which have at least one vertex and multiple inwardly concave side edges passing through the vertex. This dune-like structure can not only effectively reduce the reflection loss of the available spectrum, increase the number of reflections of the incident light, and enhance light absorption, but also has a larger specific surface area than the polished surface, which is beneficial to the contact with the tunneling oxide layer and can effectively increase the carrier transmission path. Its dune-like structure is also more conducive to the tunneling effect of carriers, reducing the transmission loss of carriers and improving the filling factor; combined with the formation of a tunneling passivation contact structure of doped polysilicon, it can effectively improve the passivation effect of the silicon substrate surface.

[0060] In some embodiments, such as Figures 3(A) to 3(D) As shown, the dune-like structure includes at least one vertex away from the surface of one side of the silicon substrate and a bottom point (lowest point) close to the side surface of the silicon substrate. The height difference between the vertex and the bottom point of the dune-like structure refers to the height difference between the vertex and the bottom point of the dune-like structure in a direction perpendicular to the side surface of the silicon substrate. The height difference between the vertex and the bottom point of the dune-like structure is 0.1 to 5 μm, preferably 0.5 to 2 μm, for example, 0.1 μm, 0.2 μm, 0. .3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, 3μm, 3.2μm, 3.4μm, 3.7μm, 4μm, 4.2μm, 4.5μm, 4.8μm, 5μm, etc. The height difference of the dune-like structure can further increase the probability of scattering of light and increase light absorption within the scope of the present application.

[0061] In some embodiments, the radius of curvature of the lowest point of the side edge is 0.1 to 20 μm. In the present application, the radius of curvature of the lowest point of the side edge represents the radius of the tangent circle of the curved side edge at the lowest point, and this tangent circle is also called the close circle. As shown in FIG. 3 (D), the radius of curvature of the lowest point B of the side edge is the radius r of the close circle of the side edge at point B. For example, the radius of curvature of the side edge of the present application may be 0.1 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm, 21 μm, etc. In some embodiments, a scanning electron microscope can be used to obtain a SEM image of a dune-like structure, and the curvature radius of the lowest point on the side edge of the dune-like structure can be obtained by constructing a rectangular coordinate system based on the SEM image and the metric scale on the image. The micro-suede surface with a dune-like structure can increase the chance of light scattering in a solar cell, reduce light reflection, and increase light absorption.

[0062] In some embodiments, as shown in FIG. 3(A) to (B), tangents to any two adjacent side edges of the dune-like structure are drawn through the vertex of the dune-like structure, and the angle α between the two tangents is the angle between two adjacent side edges passing through the same vertex of the dune-like structure. In some embodiments, the angle between two adjacent side edges of the dune-like structure is 40-160°, preferably 40-85°, for example, 40°, 42°, 44°, 45°, 46°, 48°, 50°, 52°, 54°, 55°, 56°, 58°, 60°, 62°, 64°, 65°, 66°, 68°, 70°, 72°, 74°, 76°, 78°, 80°, 82°, 85°, 87°, 90°, 92°, 94°, 96°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145°, 150°, 155° or 160°, etc. In some embodiments, the angle between two adjacent side edges of the dune-like structure can be directly measured by a scanning electron microscope. The angle of the dune-like structure within the scope of the present application is more conducive to the absorption of multi-angle incident light and reduces reflection.

[0063] In the present application, the specific surface area of ​​the micro-velvet surface refers to the ratio of the surface area after the micro-velvet surface is formed on the corresponding surface of the silicon substrate to the initial (before velvet) surface area of ​​the corresponding surface of the silicon substrate. In some embodiments, the specific surface area of ​​the micro-velvet surface is 1.1 to 1.4, for example, it can be 1.1, 1.15, 1.2, 1.25, 1.3, 1.35, 1.4, etc. In some embodiments, the specific surface area can be calculated by optical profilometer, atomic force microscope AFM or scanning electron microscope SEM measurement. The appropriate specific surface area can not only increase the number of reflections of the incident light and improve light absorption, but also increase the contact area with the tunneling oxide layer, effectively increasing the carrier transmission path.

[0064] In some embodiments, the reflectivity of the micro-suede surface is 10% to 45%, for example, it can be 10%, 12%, 15%, 18%, 20%, 22%, 25%, 27%, 30%, 32%, 34%, 36%, 38%, 40%, 42%, 45%, etc. The reflectivity of the present application refers to the weighted average of the reflectivity curve (300 to 1200nm) and the AM1.5G spectrum, that is, the reflectivity at each wavelength between 300nm and 1200nm is first obtained, and then the reflectivity is obtained by weighted summation with the sunlight spectrum of the AM1.5G standard. The present application can measure the reflectivity by QE, D8 reflectometer or spectrophotometer. The reflectivity range of the micro-suede surface can ensure that the structure can effectively reduce the reflection loss of the available spectrum and increase the short-circuit current density.

[0065] In some embodiments, the height difference between the vertices of two adjacent dune-like structures is 0.1-4 μm, for example, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, 3.2 μm, 3.4 μm, 3.7 μm, 4 μm, etc. The height difference between the vertices of two adjacent dune-like structures refers to the height difference between the vertices of the two adjacent dune-like structures in the direction perpendicular to the surface of the silicon substrate. In some embodiments, the height difference between the bottom points (lowest points) of two adjacent dune-like structures is 0 to 2 μm, for example, 0, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2 μm, etc. The height difference between the bottom points of two adjacent dune-like structures refers to the height difference between the bottom points of two adjacent dune-like structures in the direction perpendicular to the surface of the silicon substrate. In some embodiments, the height difference between the vertices of two adjacent dune-like structures and the height difference between the bottom points of two adjacent dune-like structures can be directly measured by a scanning electron microscope. The height difference between the vertices of two adjacent dune-like structures and the height difference between the bottom points of the micro-suede surface are within the above range, so that the undulation of the micro-suede surface is more conducive to increasing the reflection path of light and improving light absorption.

[0066] In some embodiments, the tunnel oxide layer 3 may be selected from at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer.

[0067] In some embodiments, the thickness of the tunneling oxide layer 3 is 0.2 to 2 nm, for example, 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, etc. The thickness of the appropriate tunneling oxide layer 3 can ensure carrier tunneling, and the dune-like structural design is more conducive to the tunneling effect of carriers, and can also improve the passivation effect of the silicon substrate. The thickness of the tunneling oxide layer 3 is too large, which is not conducive to reducing the contact resistance of the tunneling oxide layer 3. By controlling the thickness of the tunneling oxide layer 3, the reduction of the filling factor caused by the contact resistance can be suppressed. In some embodiments, the thickness of the tunneling oxide layer 3 can be measured by a transmission electron microscope.

[0068] In some embodiments, the thickness of the doped polysilicon layer 4 is 50 to 200 nm, for example, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, etc. Suitable polysilicon thickness can improve field passivation performance and ensure passivation effect. In some embodiments, the thickness of the doped polysilicon layer 4 can be measured by a transmission electron microscope.

[0069] In some embodiments, the doping concentration of polysilicon in the doped polysilicon layer 4 is 0.05E20-9E20 / cm 3 , preferably 0.1E20~3E20 / cm 3 , for example, 0.05E20 / cm 3 , 0.1E20 / cm 3 , 0.2E20 / cm 3 , 0.3E20 / cm 3 , 0.5E20 / cm 3 , 0.6E20 / cm 3 , 0.7E20 / cm 3 , 0.8E20 / cm 3 , 0.9E20 / cm 3 , 1E20 / cm 3 , 2E20 / cm 3 、3E20 / cm 3 , 4E20 / cm 3 , 5E20 / cm 3 、6E20 / cm 3 、7E20 / cm 3 , 8E20 / cm 3 、9E20 / cm 3 Etc. Appropriate doping concentration has a good effect on reducing contact resistance and improving passivation performance.

[0070] In some embodiments, a transparent conductive layer 7 is stacked on the doped polysilicon layer 4. In some embodiments, the thickness of the transparent conductive layer 7 is 20 to 200 nm, preferably 35 to 65 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm, 160 nm, 165 nm, 170 nm, 175 nm, 180 nm, 185 nm, 190 nm or 200 nm. The thickness of the transparent conductive layer 7 within the above range can significantly improve the effect of incident light absorption.

[0071] In some embodiments, the reflectivity of the surface of the transparent conductive layer 7 facing away from the silicon substrate is 8% to 18%, for example, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, etc. In some embodiments, the reflectivity can be measured by a QE, D8 reflectometer or a spectrophotometer. The reflectivity within the above range can improve light absorption, reduce light reflection, and improve photoelectric conversion efficiency.

[0072] Those skilled in the art will understand that silicon wafers generally refer to raw material bare silicon wafers, and silicon substrates generally refer to the part formed by silicon wafers in a battery. Those skilled in the art will understand that silicon substrates can be recycled from batteries, and the silicon substrates of the present application can be obtained by peeling off different laminated structures.

[0073] As an optional technical solution of the present application, the silicon substrate is an N-type or P-type crystalline silicon substrate (or silicon wafer), and any one or more processes of high temperature diffusion, slurry doping or ion implantation can be used. In some embodiments, the silicon substrate can be one of a single crystal silicon substrate, a polycrystalline silicon substrate, a microcrystalline silicon substrate or a silicon carbide substrate.

[0074] In some embodiments, the formed solar cell is a single-sided cell, the front surface can be referred to as the light-receiving side, and the rear surface can be referred to as the backlight side. In some embodiments, the formed solar cell is a bifacial cell, and both the front surface and the rear surface can be the light-receiving side.

[0075] In some embodiments, a micro-fleece surface having a dune-like structure is provided on one side surface of the silicon substrate, and a first passivation layer, a P-type doped amorphous silicon layer and an anti-reflection layer are stacked on the micro-fleece surface. The present application does not limit the first passivation layer, as long as it can play a passivation role. In some embodiments, the first passivation layer can be selected from at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer, an intrinsic amorphous silicon, etc. In some embodiments, the anti-reflection layer is a composite anti-reflection structure composed of silicon nitride, silicon oxide, magnesium fluoride, etc. or silicon nitride, silicon oxide, and magnesium fluoride. In some embodiments, a micro-fleece surface having a dune-like structure is provided on one side surface of the silicon substrate, and an intrinsic a-Si:H passivation layer, a P-type doped a-Si:H layer, a TCO layer, and a metal layer are sequentially stacked on the micro-fleece surface.

[0076] In some embodiments, the solar cell of the present application may be a TOPCon cell, a partial TOPCon cell, or a BC cell (for example, a hybrid BC, a low-temperature HBC, an IBC, an ABC, a TBC, a POLO-IBC cell, etc.).

[0077] In some embodiments, the solar cell of the present application is a TOPCon cell, the silicon substrate is an N-type crystalline silicon substrate, the rear surface of the silicon substrate has a micro-fleece surface with a dune-like structure, and a tunneling oxide layer and an N-type doped polysilicon layer are sequentially stacked on the micro-fleece surface. In some embodiments, the solar cell of the present application is a TOPCon cell, the silicon substrate is a P-type crystalline silicon substrate, the rear surface of the silicon substrate has a micro-fleece surface with a dune-like structure, and a tunneling oxide layer and a P-type doped polysilicon layer are sequentially stacked on the micro-fleece surface.

[0078] In some embodiments, such as Figure 2 As shown, the solar cell is a BC cell, and the rear surface of the BC solar cell includes a first area 10, a second area 11, and a gap area 12 located between the first area 10 and the second area 11, and the first area and the second area are alternately distributed. At least one of the first area 10, the second area 11, and the gap area 12 is provided with a micro-suede surface with a dune-like structure.

[0079] In some embodiments, the solar cell is a BC cell, the silicon substrate is an N-type crystalline silicon substrate, the first region of the silicon substrate has a micro-suede surface with a dune-like structure, and a tunneling oxide layer 3 and a doped polysilicon layer 4 are sequentially stacked on the micro-suede surface. Figure 2 As shown, a transparent conductive layer 7 is stacked on the doped polysilicon layer 4. The present application does not limit the material of the transparent conductive layer 7. For example, the transparent conductive layer 7 can be a TCO layer. For example, the TCO can be selected from one of ITO, AZO, IOH, ICO, ZnOx, SnOx, SCOT and FTO. Optionally, Figure 2As shown, an intrinsic amorphous silicon layer 5 and a second doped layer 6 are sequentially stacked on the silicon substrate of the second region. The second doped layer 6 is a doped amorphous silicon layer, a doped microcrystalline silicon layer or a doped nanocrystalline silicon layer. In the present application, the doping type of the doped polycrystalline silicon layer 4 is opposite to that of the second doped layer 6. When the doped polycrystalline silicon layer 4 is p-type doped, the second doped layer 6 is n-type doped. When the doped polycrystalline silicon layer 4 is n-type doped, the second doped layer 6 is p-type doped.

[0080] In some embodiments, such as Figure 2 As shown, the solar cell is a BC cell, the silicon substrate is an N-type crystalline silicon substrate, and the front surface of the silicon substrate is sequentially stacked with a third passivation layer 2 and an anti-reflection layer 1. Specifically, the anti-reflection layer 1 is a composite anti-reflection structure composed of silicon nitride, silicon oxide, magnesium fluoride, etc. or silicon nitride, silicon oxide, and magnesium fluoride. Further, the third passivation layer 2 can be selected from at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.

[0081] Optionally, the solar cell further includes a first electrode 9 and a second electrode 8. The first electrode 9 and the second electrode 8 can be formed by applying a metal conductive paste and then sintering. In some embodiments, the material of the first electrode 9 or the second electrode 8 includes a metal material such as silver, aluminum, copper, nickel, etc. Other materials and preparation methods of the first electrode 9 or the second electrode 8 are not described in detail here.

[0082] In some embodiments, such as Figure 2As shown, the surface of the silicon substrate has a first area 10 and a second area 11; the first area 10 has the micro-suede surface as described above, and a tunneling oxide layer 3 and a doped polysilicon layer 4 are sequentially stacked on the micro-suede surface; a second semiconductor layer is stacked on the second area 11, wherein the second semiconductor layer includes an intrinsic amorphous silicon layer 5 and a second doped layer 6 stacked on the surface of the intrinsic amorphous silicon layer 5 on the side away from the silicon substrate, and the second doped layer 6 can be, for example, a doped amorphous silicon layer, a doped microcrystalline silicon layer or a doped nanocrystalline silicon layer. In the above embodiment, one side surface of the silicon substrate has the first area 10 and the second area 11, or one side surface of the silicon substrate has the first area 10 and the other side surface has the second area 11. In some embodiments, the backlight side of the battery has the first area 10 and the second area 11, the first area is stacked with a tunneling oxide layer 3 and a doped polysilicon layer 4, and the second area is stacked with an intrinsic amorphous silicon layer 5 and a doped amorphous silicon layer 6, and the solar cell is a hybrid back contact battery. For hybrid back-contact cells, the first zone adopts a micro-suede design that matches the tunneling passivation contact structure. Compared with the polished surface design of the prior art, on the one hand, it can reduce spectral reflection and enhance light absorption. On the other hand, the contact area between the micro-suede surface and the tunneling oxide layer is larger, which can not only effectively increase the carrier transmission path, but also the dune-like structure is more conducive to the tunneling effect of carriers, reducing carrier transmission losses and improving the fill factor. Combined with the tunneling passivation contact structure formed by doped polysilicon, it can effectively improve the passivation effect of the silicon substrate surface in the first zone, improve the minority carrier lifetime and majority carrier collection efficiency, and increase the open circuit voltage, thereby improving the photoelectric conversion efficiency of solar cells.

[0083] In a second aspect, the present application provides a method for preparing a solar cell, comprising the following steps:

[0084] The silicon substrate is textured to obtain a micro-texture surface with a dune-like structure;

[0085] Forming a tunneling oxide layer 3 on the micro-suede surface;

[0086] Among them, the method for texturing a silicon substrate includes: alkaline polishing to prepare a velvet surface with a pyramid structure, and then acid treatment with a mixed solution of nitric acid and hydrofluoric acid to obtain a micro-velvet surface with a dune-like structure, wherein the volume ratio of hydrofluoric acid to nitric acid is 1:8-20.

[0087] In the prior art solar cell preparation process, the silicon substrate is either polished to obtain a polished surface, or the silicon substrate is polished to obtain a conventional pyramid structure velvet surface. However, after the pyramid structure is formed, the solar cell of the present application uses an acid treatment to treat the pyramid structure to form a micro-velvet surface with a dune-like structure.

[0088] As an optional technical solution of the present application, the silicon substrate is an N-type or P-type crystalline silicon substrate, and any one or more processes of high temperature diffusion, slurry doping or ion implantation can be used. In some embodiments, the silicon substrate can be one of a single crystal silicon substrate, a polycrystalline silicon substrate, a microcrystalline silicon substrate or a silicon carbide substrate.

[0089] In some embodiments, the method for preparing a solar cell of the present application includes:

[0090] The silicon substrate is textured to obtain a micro-texture surface with a dune-like structure;

[0091] Forming a tunneling oxide layer 3 on the micro-suede surface;

[0092] forming a doped polysilicon layer 4 on a surface of the tunnel oxide layer 3 which is away from the silicon substrate;

[0093] Among them, the method for texturing a silicon substrate includes: alkaline polishing to prepare a velvet surface with a pyramid structure, and then acid treatment with a mixed solution of nitric acid and hydrofluoric acid to obtain a micro-velvet surface with a dune-like structure, wherein the volume ratio of hydrofluoric acid to nitric acid is 1:8-20.

[0094] In the present application, a mixed solution of nitric acid and hydrofluoric acid refers to a mixed solution obtained by mixing nitric acid and hydrofluoric acid, and a volume ratio of hydrofluoric acid to nitric acid refers to a mixture of nitric acid and hydrofluoric acid in the volume ratio.

[0095] In some embodiments, nitric acid and hydrofluoric acid are used for acid treatment, and the concentration of nitric acid used is 10% to 65%, preferably 30% to 50%, for example, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, etc.; the concentration of hydrofluoric acid used is 1% to 20%, preferably 1% to 5%, for example, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, etc. The concentration here refers to the mass percentage concentration. If the concentration of nitric acid and hydrofluoric acid used is too high, it is volatile, dangerous, and may damage other film layers; if the concentration of nitric acid and hydrofluoric acid is too low, the etching time will be too long, resulting in excessive etching.

[0096] In some embodiments, the volume ratio of hydrofluoric acid to nitric acid is 1:8-20, for example, 1:8, 1:10, 1:12, 1:14, 1:16, 1:18, 1:20, etc. The volume ratio of nitric acid to hydrofluoric acid is controlled within the scope of the present application so that excessive etching is not performed, which is more conducive to forming a micro-suede surface with a dune-like structure that is different from a pyramid structure.

[0097] In some embodiments, the acid treatment temperature is 10 to 30°C, preferably 10 to 20°C, for example, 10°C, 12°C, 14°C, 15°C, 16°C, 18°C, 20°C, 22°C, 24°C, 25°C, 26°C, 28°C, 30°C, etc. If the acid treatment temperature is too high, it is easy to over-etch and cause damage; if the acid treatment temperature is too low, the etching efficiency is low, resulting in a long treatment time. In some embodiments, the acid treatment time is 10 to 1500s, preferably 100 to 800s, for example, it can be 10s, 20s, 40s, 50s, 60s, 80s, 100s, 150s, 200s, 250s, 300s, 350s, 400s, 450s, 500s, 550s, 600s, 650s, 700s, 750s, 800s, etc. If the acid treatment time is too long, it will lead to excessive etching and damage the micro-suede structure; if the acid treatment time is too short, it will lead to incomplete etching.

[0098] The prior art also uses HF and HNO3 for the rounding treatment of the pyramid, but it is completely different from the acid treatment of the present application. First, the purpose of the rounding treatment in the prior art is to make the top or bottom of the tower rounded, that is, to flatten the tip. The rounding treatment is relatively gentle, while the acid treatment in the present application is larger, and its range is between polishing and rounding treatment. Therefore, the acid treatment in the present application is different from the reagent concentration, ratio and treatment time used in the rounding treatment in the prior art. Specifically, the volume ratio of HF to HNO3 in the rounding treatment of the prior art is 1:600-1000, while the ratio of HF to HNO3 used in the acid treatment of the present application is 1:8-20, and the ratio of HF to HNO3 in the two treatment methods differs by about 100 times; in addition, the temperature and time of the acid treatment in the present application are also higher than the temperature and time of the rounding treatment, so that the side edges of the pyramid structure can be rounded into arcs, forming a dune-like structure, which not only improves the absorption of light, but also facilitates the matching with the passivation contact structure.

[0099] In some embodiments, the tunneling oxide layer 3 may be selected from at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer. In some embodiments, the thickness of the tunneling oxide layer 3 is 0.2 to 2 nm, for example, 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, etc. If the thickness of the tunneling oxide layer 3 is too large, it is not conducive to reducing the contact resistance of the tunneling oxide layer 3. By controlling the thickness of the tunneling oxide layer 3, the reduction of the fill factor caused by the contact resistance can be suppressed. In some embodiments, the tunnel oxide layer 3 may be formed by ozone oxidation, high temperature thermal oxidation, nitric acid oxidation, chemical vapor deposition (eg, low pressure chemical vapor deposition LPCVD, plasma enhanced chemical vapor deposition PECVD), or physical vapor deposition PVD.

[0100] In some embodiments, the thickness of the doped polysilicon layer 4 is 50-200 nm, for example, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, etc. The appropriate thickness of the doped polysilicon layer can match the tunneling oxygen to form a passivation contact structure and improve the passivation effect.

[0101] In some embodiments, the method for preparing the solar cell of the present application includes the following steps: alkaline polishing of one side surface of the silicon substrate, SC1 cleaning, treatment with an alkaline solution and an additive to prepare a velvet surface with a pyramid structure, SC1 cleaning, acid treatment, HF cleaning, slow pulling and drying to form a micro-velvet surface with a dune-like structure.

[0102] In some embodiments, the method for preparing the solar cell of the present application includes the following steps: alkaline polishing of one side surface of the silicon substrate, SC1 cleaning, co-treatment of the alkaline solution and the additive to prepare a velvet surface with a pyramid structure, SC1 cleaning, acid treatment, SC1 cleaning, SC2 cleaning, HF cleaning, slow pulling and drying to form a micro-velvet surface with a dune-like structure.

[0103] In some embodiments, the method for preparing the solar cell of the present application includes the following steps: alkaline polishing of one side surface of the silicon substrate, SC1 cleaning, co-treatment of the alkaline solution and the additive to prepare a velvet surface with a pyramid structure, SC1 cleaning, CP treatment, acid treatment, SC1 cleaning, SC2 cleaning, HF cleaning, slow pulling and drying to form a micro-velvet surface with a dune-like structure.

[0104] In some embodiments, a tunneling oxide layer 3 is deposited on the micro-velvet surface by chemical vapor deposition or physical vapor deposition. Preferably, the chemical vapor deposition method is a low-pressure chemical vapor deposition method or a plasma-enhanced chemical vapor deposition method. In some embodiments, in the process of depositing the tunneling oxide layer 3 on the micro-velvet surface by low-pressure chemical vapor deposition, the deposition temperature is 400-700°C, preferably 500-600°C, for example, 400°C, 420°C, 440°C, 460°C, 480°C, 500°C, 520°C, 540°C, 560°C, 580°C, 600°C, 620°C, 640°C, 660°C, 680°C, 700°C, etc. In some embodiments, in the process of depositing the tunneling oxide layer 3 on the micro-suede surface by low pressure chemical vapor deposition, the deposition time is 1 to 50 minutes, preferably 5 to 25 minutes, for example, 1 minute, 2 minutes, 4 minutes, 5 minutes, 6 minutes, 8 minutes, 10 minutes, 12 minutes, 15 minutes, 18 minutes, 20 minutes, 22 minutes, 25 minutes, 28 minutes, 30 minutes, 32 minutes, 34 minutes, 36 minutes, 38 minutes, 40 minutes, 42 minutes, 44 minutes, 46 minutes, 48 ​​minutes, 50 minutes, etc. Controlling the deposition temperature and deposition time within the above range can effectively ensure the passivation contact characteristics.

[0105] In some embodiments, after the acid treatment, the method of the present application further comprises the step of cleaning with potassium hydroxide and hydrogen peroxide; the concentration of potassium hydroxide is 0.1% to 1%, for example, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, etc., and the concentration of hydrogen peroxide is 1% to 5%, for example, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, etc. Cleaning with a mixed solution of potassium hydroxide and hydrogen peroxide of the above concentrations can better remove pollutants. In some embodiments, the cleaning temperature for cleaning with potassium hydroxide and hydrogen peroxide is 25-80°C, for example, 25°C, 30°C, 35°C, 40°C, 45°C, 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C, etc., and the cleaning time is 60-300s, for example, 60s, 80s, 100s, 120s, 140s, 160s, 180s, 200s, 220s, 240s, 260s, 280s, 300s, etc. Controlling the cleaning time and temperature within the above range can further remove pollutants.

[0106] In some embodiments, the micro-fleece is any one of the micro-fleece described in the first aspect above.

[0107] In some embodiments, the solar cell prepared by the preparation method of the present application is any one of the solar cells in the aforementioned first aspect.

[0108] In the third aspect, the present application also provides a photovoltaic assembly, which includes any one of the solar cells in the aforementioned first aspect, which can improve the battery conversion efficiency of the photovoltaic assembly; the solar cell is electrically connected in the form of a whole piece or multiple pieces (for example, 1 / 2 equal pieces, 1 / 3 equal pieces, 1 / 4 equal pieces, etc.) to form a plurality of battery strings. In some embodiments, the multiple battery strings are electrically connected in series and / or in parallel. In some embodiments, the photovoltaic assembly also includes a packaging material layer and a cover plate, wherein the packaging material layer is used to seal the multiple solar cell strings and the cover plate covers the packaging material layer. For example, the material of the packaging material layer can be an organic material such as EVA, POE or PET, and the cover plate can be a glass cover plate, a plastic cover plate, or the like with a light-transmitting function.

[0109] Example

[0110] The experimental methods used in the following examples are all conventional methods unless otherwise specified.

[0111] Unless otherwise specified, the materials and reagents used in the following examples can be obtained from commercial sources.

[0112] Example 1-1

[0113] The method for preparing the silicon wafer with micro-texture surface in this embodiment is as follows:

[0114] An N-type single crystal silicon wafer is provided as a silicon substrate; the rear surface of the N-type single crystal silicon substrate is subjected to KOH pre-cleaning, SC1 cleaning, KOH+additive preparation of a velvet surface with a pyramid structure, SC1 cleaning, CP treatment, acid treatment, SC1 cleaning, SC2 cleaning, HF cleaning, slow pulling and drying to form a micro-velvet surface with a dune-like structure; wherein, a 40% nitric acid solution and a 3% hydrofluoric acid solution are used for acid treatment at 15°C for 200s; a 0.7% KOH solution and a 1.85% hydrogen peroxide solution are used for the SC1 cleaning step after the acid treatment, the cleaning time is 180s, and the cleaning temperature is 65°C; wherein, the base length of the pyramid structure is about 1.5 to 3μm.

[0115] Example 1-2

[0116] The difference between this embodiment and embodiment 1-1 is that the acid treatment time is 400 s.

[0117] Examples 1-3

[0118] The difference between this embodiment and embodiment 1-1 is that the acid treatment time is 600 s.

[0119] Examples 1-4

[0120] The difference between this embodiment and embodiment 1-2 is that the length of the base side of the pyramid structure on the velvet surface with pyramid structure prepared by KOH+additive is about 0.5-1.5 μm.

[0121] Comparative Example 1

[0122] The difference between this comparative example and Example 1-1 is that the rear surface of the N-type single crystal silicon substrate is subjected to SC1 cleaning, KOH+additive treatment, ozone treatment, SC1 cleaning, SC2 cleaning, HF cleaning, Dip treatment and drying to form a polished surface with a reflectivity of 47.61%.

[0123] The surface morphology of the silicon substrate prepared in the above-mentioned Examples 1-1 to 1-4 and Comparative Example 1 was characterized by reflectivity, and the results are shown in Tables 1 and Figure 4 As shown, it can be found that for the velvet of a larger pyramid structure (Example 1-1 to Example 1-3), a short acid treatment can form a micro-velvet with a dune-like structure with lower reflectivity, that is, the original velvet characteristics can be better guaranteed. As the acid treatment time increases, the reflectivity gradually increases, close to the polished surface (Comparative Example 1). For the velvet of a smaller pyramid structure (Example 1-4), only a short acid treatment is required, and the reflectivity of the obtained micro-velvet can be close to the reflectivity of the micro-velvet obtained after a longer acid treatment (Example 1-3) of the larger pyramid structure. It can be seen that the small-sized pyramid velvet is more susceptible to the influence of acid treatment, which further highlights the importance of matching the micro-velvet structure with the acid treatment process. In addition, the reflectivity of Example 1-1 to Example 1-4 is much lower than the polished structure of the comparative example, indicating that the dune-like structure of the micro-velvet can effectively reduce the reflection loss of the available spectrum, improve the absorption of light, and have a gain effect on optical performance.

[0124] In order to ensure the smooth progress of the subsequent battery process, the surface morphology characteristics of the uncoated film were tested by SEM. The test results are as follows: Figure 5 As shown in the figure, the extension of the acid treatment time leads to a decrease in the height of the dune-like structure, the curved side edges become smooth, and the surface morphology gradually approaches the polished state. For the velvet surface with small-sized pyramid structures, a shorter acid treatment time can form a micro-velvet surface with a dune-like structure close to the polished state. Figure 5 The SEM bars in the same column are the same.

[0125] The sizes of the micro-fleece prepared in Examples 1-1 to 1-4 are shown in Table 1. The width of the dune-like structure refers to the distance between the lowest points of two adjacent dune-like structures in a direction parallel to the surface of the silicon substrate.

[0126] Table 1

[0127]

[0128] Example 2 Preparation of BC Solar Cell

[0129] (1) Prepare a silicon wafer with a micro-texture surface according to the method of Examples 1-3;

[0130] (2) A tunnel oxide layer is deposited on the micro-texture surface by low pressure chemical vapor deposition (LPCVD) with a thickness of 0.5 to 2 nm, a deposition temperature of 500 to 600° C., and a deposition time of 5 to 25 min. An N-type doped polysilicon layer is deposited by LPCVD on the side of the tunnel oxide layer away from the silicon substrate with a thickness of 50 to 200 nm.

[0131] (3) Laser etching is performed on the tunneling oxide layer and the N-type doped polysilicon layer to remove the tunneling oxide layer and the N-type doped polysilicon layer in the second region, exposing the N-type single crystal silicon substrate to form a second opening.

[0132] (4) The front surface and the second area of ​​the rear surface of the N-type single crystal silicon substrate are subjected to texturing and cleaning. The specific steps are: KOH solution polishing, SC1 cleaning, KOH+additive texturing, SC1 cleaning, CP smoothing, SC2 cleaning, HF cleaning, slow pulling and drying, so that the second area of ​​the front surface and the rear surface forms a velvet surface with a pyramid structure.

[0133] (5) The second semiconductor layer is prepared on the rear surface by full-area coverage of PECVD, that is, a 3-10 nm intrinsic amorphous silicon layer and a 5-20 nm P-type doped amorphous silicon layer are formed in sequence, and a third passivation layer and an anti-reflection layer are prepared in sequence on the front surface by PECVD. The third passivation layer is 2-20 nm intrinsic amorphous silicon or aluminum oxide, and the anti-reflection layer is 50-200 nm silicon nitride.

[0134] (6) Laser etching is performed on the second semiconductor layer to remove the second semiconductor layer in the first region, exposing the N-type doped polysilicon layer, and forming a first opening.

[0135] (7) A TCO layer is prepared on the rear surface to fully cover the entire surface, with a thickness of 20 to 200 nm, and then the TCO layer is laser etched to remove portions of the TCO layer at intervals to form insulating grooves.

[0136] (8) Using screen printing, a first electrode is formed on the surface of the first opening, and a second electrode is formed on the surface of the second opening.

[0137] The efficiency of the BC solar cell prepared in this embodiment can reach more than 26.3%, V OC Can rise to over 740mV. Figure 1 The hybrid back contact cell structure of the prior art adopts a polished surface design in the first area, matching the tunneling oxide layer and the doped polysilicon structure. The polished surface will cause more long-wave spectrum reflections, further escaping through the front surface of the silicon wafer, so as to cause serious optical losses. In addition, the specific surface area of ​​the polished surface is small, and the contact area with the passivation layer is small. Its structure is not conducive to the tunneling effect of carriers. The first area of ​​the hybrid back contact cell structure of this embodiment adopts a micro-suede surface design with a dune-like structure, which can not only effectively reduce the reflection loss of the available spectrum, increase the number of reflections of the incident light, and improve light absorption, but also has a larger specific surface area than the polished surface, which is also conducive to the uniform deposition of the contact with the tunneling oxide layer silicon, and can effectively increase the carrier transmission path. Its dune-like structure is also more conducive to the tunneling effect of carriers, reducing the transmission loss of carriers and improving the filling factor; combined with the tunneling passivation contact structure formed by doped polysilicon, it can effectively improve the passivation effect of the silicon substrate surface in the first area, thereby improving the conversion efficiency of the battery.

[0138] Although the embodiments of the present application are described above in conjunction with the accompanying drawings, the present application is not limited to the above specific embodiments and application fields, and the above specific embodiments are merely illustrative and instructive, rather than restrictive. A person of ordinary skill in the art can also make many forms under the guidance of this specification and without departing from the scope of protection of the claims of the present application, all of which belong to the protection of the present application.

Claims

1. A solar cell comprising a silicon substrate, wherein at least one side of the silicon substrate has a micro-suede surface with a dune-like structure, and a tunneling oxide layer is stacked on the micro-suede surface; The dune-like structure has at least one vertex, and each vertex has 3 to 6 curved side edges; The side edges are recessed toward the interior of the dune-like structure.

2. The solar cell according to claim 1, wherein: A doped polysilicon layer is stacked on the tunnel oxide layer.

3. The solar cell according to claim 1, wherein: The height difference between the top and bottom of the dune-like structure is 0.1 to 5 μm, preferably 0.5 to 2 μm; and / or The curvature radius of the lowest point of the side edge is 0.1 to 20 μm; and / or The included angle between two adjacent side edges passing through the same vertex of the dune-like structure is 40 to 160°, preferably 40 to 85°.

4. The solar cell according to claim 1, wherein: The specific surface area of ​​the micro-suede surface is 1.1 to 1.4; and / or The reflectivity of the micro-suede surface is 10% to 45%.

5. The solar cell according to claim 1, wherein: The height difference between the vertices of two adjacent dune-like structures is 0.1 to 4 μm; and / or The height difference between the bottom points of two adjacent dune-like structures is 0 to 2 μm.

6. The solar cell according to claim 1, wherein: The thickness of the tunnel oxide layer is 0.2-2 nm.

7. The solar cell according to claim 2, wherein: The thickness of the doped polysilicon layer is 50-200 nm; and / or The doping concentration of polysilicon in the doped polysilicon layer is 0.05E20-9E20 / cm 3 , preferably 0.1E20~3E20 / cm 3 .

8. The solar cell according to claim 2, wherein: A transparent conductive layer is stacked on the doped polysilicon layer; Preferably, the thickness of the transparent conductive layer is 20 to 200 nm, preferably 35 to 65 nm; Preferably, the surface reflectivity of the transparent conductive layer on a side facing away from the silicon substrate is 8% to 18%.

9. The solar cell according to any one of claims 1 to 8, wherein The surface of the silicon substrate has a first area and a second area; The first region has the micro-texture surface, and a tunneling oxide layer and a doped polysilicon layer are sequentially stacked on the micro-texture surface; A second semiconductor layer is stacked on the second region; The first areas and the second areas are alternately distributed; Preferably, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped layer stacked on a surface of the intrinsic amorphous silicon layer facing away from the silicon substrate, wherein the second doped layer is a doped amorphous silicon layer, a doped microcrystalline silicon layer or a doped nanocrystalline silicon layer.

10. A method for preparing a solar cell, comprising: The silicon substrate is textured to obtain a micro-texture surface with a dune-like structure; forming a tunneling oxide layer on the micro-fleece surface; Among them, the method for texturing a silicon substrate includes: alkaline polishing to prepare a velvet surface with a pyramid structure, and then acid treatment with a mixed solution of nitric acid and hydrofluoric acid to obtain a micro-velvet surface with a dune-like structure, wherein the volume ratio of hydrofluoric acid to nitric acid is 1:8-20.

11. The preparation method according to claim 10, further comprising: A doped polysilicon layer is formed on a surface of the tunnel oxide layer that is away from the silicon substrate.

12. The preparation method according to claim 10, wherein: The concentration of nitric acid used is 30% to 50%; and / or The concentration of hydrofluoric acid used is 1% to 5%; and / or The acid treatment temperature is 10 to 30°C, preferably 10 to 20°C; and / or The acid treatment time is 10 to 1500 s, preferably 100 to 800 s.

13. The preparation method according to claim 10, wherein: After the acid treatment, the method further comprises a step of washing with a mixed solution of potassium hydroxide and hydrogen peroxide; and / or The concentration of potassium hydroxide is 0.1% to 1%, and the concentration of hydrogen peroxide is 1% to 5%; and / or The cleaning temperature is 25-80°C and the cleaning time is 60-300s.

14. The preparation method according to claim 10, wherein: Depositing a tunneling oxide layer on the micro-suede surface by chemical vapor deposition or physical vapor deposition; Preferably, the chemical vapor deposition method is a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method; Preferably, the deposition temperature of the low pressure chemical vapor deposition method is 400-700° C., preferably 500-600° C., and / or the deposition time is 1-50 min, preferably 5-25 min.

15. A photovoltaic module comprising the solar cell according to any one of claims 1 to 9, wherein the solar cell is electrically connected into a solar cell string in the form of a whole piece or multiple pieces.

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