Epitaxial silicon channel growth

Abstract

A three-dimensional NAND flash memory structure may include an epitaxial silicon solid channel core grown directly from a silicon substrate reference (reference). Alternating oxide-nitride material layers may be formed in a stack, and channel holes may be etched through the material layers extending down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layer, and an epitaxial silicon core may be grown upward through the channel hole from the silicon substrate. In some implementations, a support structure may be formed in a channel hole or in a slit of a memory array to provide physical support as an epitaxial silicon core grows through the channel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 343,437, filed on May 18, 2022, entitled “EPITAXIAL SILICON CHANNEL GROWTH,” the contents of which are hereby incorporated by reference in their entirety for all purposes. Technical Field

[0003] The present disclosure generally describes memory cells having an epitaxial silicon channel core. More specifically, the present disclosure describes techniques for fabricating a 3D NAND flash memory structure having an epitaxial channel core grown from a silicon substrate. Background Art

[0004] The memory design called NAND memory is a non-volatile flash memory storage architecture that does not require power to maintain its stored data. NAND flash memory is used in many products, such as solid-state devices and portable electronics. In order to improve the density of NAND memory and reduce its size, the traditional two-dimensional NAND architecture has transitioned to three-dimensional NAND stacking. Unlike 2D planar NAND technology where individual memory cells are stacked together on different horizontal substrates, 3D NAND uses multiple layers of alternating conductive and dielectric materials with intersecting vertical channels for vertical stacking. Summary of the invention

[0005] In some embodiments, a three-dimensional (3D) NAND memory structure may include a silicon substrate and a plurality of alternating material layers arranged vertically stacked on the silicon substrate. A channel hole may extend through the plurality of alternating material layers to the silicon substrate, and the channel hole may be perpendicular to the plurality of alternating material layers. The memory structure may also include a channel in the channel hole, the channel may include a tunneling layer and an epitaxial silicon core, the tunneling layer surrounds the interior of the channel hole and contacts the plurality of alternating material layers, and the epitaxial silicon core contacts the silicon substrate in the tunneling layer.

[0006] In some embodiments, a method of manufacturing a 3D NAND memory structure may include the following steps: forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate; etching a channel hole extending through the plurality of alternating material layers to the silicon substrate; forming a tunneling layer surrounding the channel hole and contacting the plurality of alternating material layers; and epitaxially growing an epitaxial silicon core from the silicon substrate in the tunneling layer through the channel hole.

[0007] In some embodiments, a 3D NAND memory array may include a silicon substrate and a plurality of alternating material layers arranged vertically stacked on the silicon substrate. A plurality of channel holes may extend through the plurality of alternating material layers. The memory array may also include a plurality of support structures extending through the plurality of alternating material layers into the silicon substrate.

[0008] In any embodiment, any and all of the following features may be implemented in any combination and are not limited. The silicon substrate may include single crystal silicon, and the epitaxial silicon core is grown from the single crystal silicon through the channel hole. The alternating material layer may include alternating layers of oxide material and nitride material. The alternating material layer may include alternating layers of oxide material and metal, wherein the metal may form a gate electrode of each memory cell in the memory structure. The epitaxial silicon core may extend into the silicon substrate. The memory structure may also include an epitaxial silicon layer extending beyond the channel hole, wherein the epitaxial silicon layer may be between the silicon substrate and multiple alternating material layers, and the epitaxial silicon layer may connect the epitaxial silicon core to multiple other channels in the memory structure. The memory structure may also include a support structure extending through multiple alternating material layers and epitaxial silicon layers and extending into the silicon substrate. A slit may be etched in the memory structure, the slit extending through multiple alternating material layers to a sacrificial nitride layer above the silicon substrate. The sacrificial nitride layer may be exposed to an etching process configured to selectively etch the sacrificial nitride layer. A portion of the tunneling layer that is exposed after removing the sacrificial nitride layer may be removed. An epitaxial silicon layer may be epitaxially grown from the silicon substrate to replace the sacrificial nitride layer. A second channel hole may be etched, the second channel hole extending through the plurality of alternating material layers into the silicon substrate, and the second channel hole may be filled with a gap filling material as a support structure. The plurality of support structures may include a metal that fills one or more of the plurality of channel holes. The plurality of support structures may include a gap filling material in a slit in a memory array. Alternating slits in a memory array may form a support structure. The plurality of support structures may include a combination of a gap filling material in one or more slits in the memory array and / or a metal that fills one or more of the plurality of channel holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of the various embodiments may be obtained by reference to the remainder of the specification and the drawings, wherein the same reference numerals are used in the various drawings to refer to similar components. In some cases, a sub-label associated with a reference numeral is used to denote one of a plurality of similar components. When a reference numeral is referenced without specifying an existing sub-label, it is intended to refer to all such plurality of similar components.

[0010] 1 illustrates a top view of one embodiment of a processing system of deposition, etch, bake, and cure chambers according to some embodiments.

[0011] 2A-2P illustrate incremental stages for producing an array of 3D NAND flash memory cells with epitaxial silicon channels, according to some embodiments.

[0012] FIG. 3A illustrates a portion of a memory array according to some embodiments.

[0013] 3B illustrates a portion of a memory array when some channels have been used for support structures to facilitate epitaxial silicon channel cores, according to some embodiments.

[0014] 4A-4L illustrate progressive steps in the fabrication process of a memory structure according to some embodiments that use slits separating memory blocks as support structures when growing epitaxial silicon channels for individual memory cells.

[0015] 5 illustrates a top view of a portion of a memory array according to some embodiments.

[0016] 6A-6H illustrate progressive steps for forming a stack including support structures in both channel holes and slots, according to some embodiments.

[0017] 7 illustrates a top view of a portion of a memory array in accordance with some embodiments.

[0018] 8 is a flow chart illustrating a method for fabricating a 3D NAND memory structure according to some embodiments. DETAILED DESCRIPTION

[0019] Conventional three-dimensional (3D) NAND flash memory structures use channel cores made of oxide materials or polysilicon. However, epitaxial silicon exhibits much higher mobility than polysilicon or other similar materials. The present disclosure describes a 3D NAND flash memory structure using epitaxial silicon cores grown directly from a silicon substrate. Alternating oxide-nitride material layers may be formed as a stack, and channel holes may be etched through the material layers extending downward to the silicon substrate. Tunneling layers may be formed around the channel holes to contact the alternating material layers, and the epitaxial silicon cores may be grown upward from the silicon substrate through the channel holes. In some implementations, support structures may be formed in the channel holes or in the slits of the memory array to provide physical support as the epitaxial silicon cores grow through the channels.

[0020] FIG. 1 depicts a top view of one embodiment of a processing system 100 of deposition, etching, baking and curing chambers according to embodiments. In this figure, a pair of front-opening standard bins 102 supply substrates of various sizes, which are received by a robot 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-108f located in a tandem section 109a-109c. A second robot 110 can be used to transport substrates from the holding area 106 to the substrate processing chambers 108a-108f and back. Each substrate processing chamber 108a-108f can be equipped to perform a variety of substrate processing operations, including dry etching processes described herein in addition to cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation and other substrate treatments.

[0021] The substrate processing chambers 108a-108f may include one or more system components for depositing, annealing, curing and / or etching material films on substrate wafers. In one configuration, two pairs of processing chambers (such as 108c-108d and 108e-108f) may be used to deposit materials on substrates, and a third pair of processing chambers (such as 108a-108b) may be used to cure, anneal or treat the deposited film. In another configuration, all three pairs of chambers (such as 108a-108f) may be configured to deposit and cure films on substrates. Any one or more of the described processes may be performed in an additional chamber separate from the manufacturing system shown in different embodiments. It should be understood that the processing system 100 may consider additional configurations for deposition, etching, annealing and curing chambers for material films. In addition, any number of other processing systems may be used with the present technology, which may be incorporated into a chamber for performing any particular operation. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining vacuum environments in various portions (such as the mentioned holding and transfer areas) can allow operations to be performed in multiple chambers while maintaining a specific vacuum environment between discrete processes.

[0022] The processing system 100 or (more specifically) more chambers incorporated into the processing system 100 or other processing systems can be used to produce structures according to some embodiments of the present technology. For example, the processing system 100 can be used to produce memory arrays by performing operations such as deposition, etching, sputtering, grinding, cleaning, etc. in various substrate processing chambers 108.

[0023] 2A-2P illustrate incremental stages for producing an array of 3D NAND flash memory cells with epitaxial silicon channels according to some embodiments. FIG. 2A illustrates a partial stack of alternating oxide-nitride layers that may be formed for a 3D NAND flash memory array. Each layer shown in FIG. 2A may be formed incrementally in a layer-by-layer manner using any deposition or layer formation technique. In this example, the layers may be formed on a substrate 200 of silicon material, such as epitaxial silicon or a single crystal silicon wafer. A silicon oxide layer 202 may be formed above the substrate 200, followed by a silicon nitride layer 204. In some embodiments, the silicon oxide layer 202 and the silicon nitride layer 204 may represent initial layers on the substrate 200, and these layers may be thicker than the alternating oxide-nitride layers formed thereon. Next, alternating layers of silicon oxide 206 and silicon nitride 208 may be formed in a stacked manner.

[0024] The progressive formation of substrate 200, silicon oxide layer 206, silicon nitride layer 208, and other materials described below in FIGS. 2A-2P may be collectively referred to as stack 224. As shown in FIG. 2A, stack 224 may initially have a limited height. For example, the completed stack may have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, forming all of these layers from the beginning may result in a stack 224 with an aspect ratio that is too high to reliably form narrow channel holes and other vias that pass through the entire stack 224. Therefore, stack 224 may be partially formed first. Then, the partial stack may have a channel hole etched in the partial stack. Additional alternating oxide and nitride layers may be added to the top of the partial stack, and these additional layers may be etched at the same location to form a channel hole that continuously passes through all the alternating oxide and nitride layers with a more uniform width, thereby maintaining a high aspect ratio and the sidewalls of the channel hole are not formed with excessive angling.

[0025] FIG. 2B illustrates how a portion of the stack is etched to form a hole 203 through the alternating silicon oxide layers 206 and silicon nitride layers 208. The hole 203 may be formed by layering a mask over the portion of the stack and performing an etching process to remove the material exposed by the mask. Any etching process, such as a dielectric etch, may be used. In general, the depth of the hole 203 may be controlled based on the number of silicon oxide layers 206 and the number of silicon nitride layers 208 to be etched. For example, the time allowed to run the etching process may be determined by the number of silicon oxide layers 206 and the number of silicon nitride layers 208 along the thickness of these layers. As an alternative to stopping the etching process after reaching the final silicon oxide layer 202, some embodiments may continue the etching process so that the hole 203 extends into the substrate 200. This additional etching, referred to herein as a "bottom punch" etch, for the bottom of the hole may allow silicon material of the substrate 200 to be exposed at the bottom of the hole 203. The bottom punch etch may represent an etch separate from the etch used to form the hole, or may be an extension of this etch until a depth inside the substrate is reached. The exposed silicon material of substrate 200 may be used in a subsequent step to epitaxially grow silicon through the channels that form the 3D NAND flash memory cells.

[0026] FIG. 2C illustrates how, according to some embodiments, stack 224 can be extended by adding additional silicon oxide layers 207 and silicon nitride layers 209 on top of a partial stack. These additional layers can be formed progressively on top of the partial stack. Alternatively, these layers can be formed separately and placed on top of the partial stack. It should be understood that the partial stacks shown in these figures are greatly simplified for clarity. In practice, the stack may include a large number of layers, a large number of channel holes, and can be used to form hundreds of 3D NAND flash memory cells. However, these figures have been simplified to represent the formation of a single epitaxial silicon channel and adjacent support structures or slits in the memory array. For example, an actual stack may include thousands of channels, more than 100 alternating oxide and nitride layers, and multiple slits and support structures. These layers can be formed in multiple processes, with etching operations being performed progressively on each batch of layers as each batch of layers is added to the partial stack. Therefore, although FIG. 2C only illustrates two combined partial stacks, it should be understood that many additional partial stacks can be layered and etched to form holes 203 through stack 224. For example, for a total of 256 alternating oxide-nitride layers, some embodiments may include a combination of two partial stacks, each having approximately 128 alternating oxide-nitride layers.

[0027] FIG. 2D illustrates a stack 224 formed of multiple partial stacks, wherein the multiple partial stacks are each etched separately, according to some embodiments. After the additional silicon oxide layer 207 and silicon nitride layer 209 of the second partial stack are added, holes 211, 219 can be etched in these layers as shown. Note that these holes 211, 219 can be formed using a mask similar to the mask previously used to etch the holes 203 in the first partial stack. Progressively etching these layer sets can achieve very high aspect ratios regardless of the depth of the holes 211, 219 in the full stack 224.

[0028] FIG. 2E illustrates a support feature 210 according to some embodiments, which may be formed in one of the holes to provide support during subsequent steps of processing. The support feature 210 may be selectively deposited in one of the holes to form a rigid structure. For example, some embodiments may use a metal such as tungsten to form the support feature 210. Some embodiments may use a dielectric filler such as SiOx or a metal-aluminum oxide-nitride-oxide-silicon (MANOS) stack as the support feature 210. Any deposition process may be used to form the support feature 210. Note that the support member 210 may extend downward into the substrate 200 by virtue of the etching process described above that overshoots the last silicon oxide layer 202. As will be demonstrated later in this disclosure, the support member 210 prevents the layers of the stack 224 from collapsing when the sacrificial nitride layer 204 is removed. In addition, extending the support feature 210 downward into the substrate 200 prevents any movement of the upper layers of the stack 224 when the nitride layer 204 is subsequently removed.

[0029] FIG. 2F depicts an initial layer of epitaxial silicon 212 formed in one of the holes 219 according to some embodiments. As described above, the additional depth of the bottom punch etching into the substrate 200 exposes the silicon material of the substrate 200 to the channel hole 219. Because the single crystal silicon of the substrate 200 is exposed, a layer of epitaxial silicon 212 may be grown in the channel hole using a process such as epitaxial deposition of silicon or epitaxy to grow a thin layer of single crystal silicon over the single crystal silicon substrate 200. For example, some embodiments may perform the epitaxial process by chemical vapor deposition. Materials such as silicon tetrachloride, trichlorosilane, dichlorosilane, silane, and other silicon chemical sources may be provided to the deposition chamber to progressively form the epitaxial silicon 212 grown on top of the substrate 200. The height of the epitaxial silicon 212 may be above the silicon oxide layer 202, but below the next silicon oxide layer in the stack 224. For example, the height of the epitaxial silicon 212 may be within the sacrificial nitride layer 204.

[0030] FIG. 2G illustrates depositing a tunneling layer 214 in the hole 219 according to some embodiments. Since the hole 219 can now be used to form a channel for the vertical column of the 3D NAND memory cell, the hole 219 may also be referred to herein as a channel hole 219. The tunneling layer 214 may be formed by depositing a blocking dielectric or oxide, a charge trap nitride (such as silicon nitride), and a tunneling dielectric or oxide. In the present disclosure, these three layers may be collectively referred to as a "tunneling layer" 214. The oxide layer in the tunneling layer 214 may provide an offset for the conduction band and the valence band of the transistor device of the memory cell.

[0031] For example, a silicon nitride layer may be wrapped within an inner and outer layer of silicon oxide. The various layers of tunneling layer 214 may be formed using atomic layer deposition, and thus these layers of tunneling layer 214 may be relatively thin compared to the alternating oxide-nitride layers of stack 224. This process may cause tunneling layer 214 to grow on the sidewalls of channel hole 219 over the top of epitaxial silicon 212 and along the bottom of the channel hole. Note that because epitaxial silicon 212 stops before the alternating silicon oxide layer 206 and silicon nitride layer 208, the interior of the channel of the 3D NAND memory cell may be covered by tunneling layer 214.

[0032] 2H illustrates how the channel hole 219 may be filled with a sacrificial gap fill material 216 according to some embodiments. To protect the tunneling layer 214 for subsequent etching processes, the channel hole 219 may be filled with a sacrificial gap fill material 216, such as carbon.

[0033] FIG. 2I illustrates a slit 218 that may be etched in a stack 224 according to some embodiments. The slit 218 may represent a relatively long trench etched in the stack 224 such that the slit 218 is adjacent to a plurality of individual channel holes along the length of the slit 218. See FIG. 2R below for a top view of the slit relative to the channel holes in a memory array. In contrast to the etching process used to form the channel holes, the slit 218 may be etched using a single process that penetrates all layers of the stack 224. A single process may be used because the slit 218 may be wider than the channel holes. Therefore, the aspect ratio may be smaller and may therefore be achieved in a single process. In some embodiments, a carbon liner 220 may be deposited on the interior of the slit 218 to protect the inner silicon oxide layer 206 and the silicon nitride layer 208 from subsequent chemical etching processes using the slit 218. For example, a carbon liner 220 may be deposited on the sidewalls and bottom of the slit 218, and a subsequent etch may be used to remove the carbon liner 220 from the bottom of the slit 218 to expose the silicon nitride layer 204. The slit 218 may be used for two separate different memory blocks in a memory array. In subsequent processing, the slit 218 may also provide access to all nitride layers in the stack 224 so that these nitride layers can be removed and replaced with tungsten (or any other conductive material) to form a conductive path for each memory cell. These conductive paths may then form the word line or gate electrode of the memory cell. For example, a wet etch using hot phosphoric acid may be used to remove the nitride layer from the stack 224, and then the slit 218 may provide access to a precursor so that an atomic layer deposition process may be used to grow tungsten in the gap left after the nitride layer is removed.

[0034] FIG. 2J illustrates the selective removal of the nitride layer 204 according to some embodiments. In order to grow the epitaxial silicon 212 in the channel hole, the nitride layer 204 may be removed to expose the portion of the tunnel layer 214 that needs to be removed so that the epitaxial silicon 212 can be exposed to the channel hole again. In this example, a wet etch, such as a hot phosphoric acid chemical etch, may be used. The wet etch may access the nitride layer 204 through the slit 218 and selectively remove the nitride layer 204. The carbon liner 212 may protect the inner nitride layer from the etching process. Other embodiments may use a dry etch or other process configured to selectively remove the nitride layer 204.

[0035] 2K illustrates the selective removal of the tunneling layer 214 from the bottom of the channel hole according to some embodiments. The removal of the nitride layer of the tunneling layer 214 may use the wet / dry etching process described above. Similar processes may be used to selectively remove the dielectric layer or oxide layer of the tunneling layer 214. Note that the gap 230 left after the removal of the nitride layer 204 is lined with oxide layers on both the top and bottom. These oxide layers (such as oxide layer 202) may be formed so that they are slightly thicker than the other oxide layers in the stack 224. However, because the oxide and nitride layers in the tunneling layer 214 may be formed as atomic layer deposition layers, these layers will be relatively thin so that they can be removed without removing a large portion of the other oxide layers that may be exposed to the etching process.

[0036] 2L illustrates the removal of sacrificial gap fill material 216 from channel hole 219, in accordance with some embodiments. Note that removal of sacrificial gap fill material 216 leaves channel hole 219 lined with tunneling layer 214 and exposed to epitaxial silicon 212.

[0037] 2M illustrates the growth of epitaxial silicon 212 according to some embodiments. The epitaxial process may be performed as described above. However, because the slits 218 and the channel holes 219 are exposed to the epitaxial silicon 212, an epitaxial silicon layer 236 may be grown to fill the gaps 230 and begin to fill the channel holes 219. When the bottom of the channel holes 219 is reached, the growth of the epitaxial silicon layer 236 may be stopped to prevent the slits 218 from also being filled with epitaxial silicon.

[0038] 2N illustrates the selective removal of a portion of the epitaxial silicon layer 236 at the bottom of the slot 218. This portion of the epitaxial silicon layer 236 may be removed using an etching process to perform a bottom "punch" as described above. The etching may remove this portion of the epitaxial silicon layer 236 until the bottom oxide layer 202 is reached as shown in FIG. 2N, or the etching may proceed below the bottom oxide layer 202 into the substrate 200.

[0039] 20 illustrates the deposition of a sacrificial gap fill material 240 in the slots 218 according to some embodiments. The sacrificial gap fill material 214 may be deposited in the slots 218 so that the epitaxial silicon layer 236 may grow in the channel hole 219 without filling the slots 218.

[0040] FIG. 2P depicts epitaxial growth of an epitaxial silicon layer 236 upward through a channel hole 219 according to some embodiments. Thus far, the previous steps in this process have been performed to provide a channel hole in which epitaxial silicon can be grown as a channel core for a 3D NAND flash memory cell. For example, the above steps provide a reference layer of epitaxial silicon at the bottom of the channel hole 219 grown from the substrate 200 itself. The epitaxial process can be performed as described above to grow the epitaxial silicon layer 236 upward through the channel hole 219. The resulting structure can include a stack 224 with a channel hole filled with an epitaxial silicon core 242, rather than an oxide core or polysilicon core found in a conventional "macaroni" structure of a 3D NAND flash memory cell. Thus, the embodiments described herein can be distinguished from conventional 3D NAND flash memory cells at least in part by the epitaxial silicon core 242 for the channel and the physical connection between the epitaxial silicon core 242 and the substrate 200 and the angled walls of the channel and the channel hole.

[0041] Referring to FIG. 2P , a 3D NAND memory structure may include a silicon substrate 200, which may be formed of single crystal silicon. The memory structure may also include a plurality of alternating material layers 275 arranged vertically stacked on the silicon substrate 200. The alternating material layers 275 may include alternating layers of oxide materials and nitride materials (such as silicon oxide and silicon nitride). At a later stage of the manufacturing process, the alternating material layers 275 may alternatively include alternating layers of oxide materials and metals (such as tungsten). For example, the nitride material may be selectively removed and replaced with a metal to form a gate electrode for an individual memory cell in the memory structure.

[0042] The alternating material layers 275 may define a channel hole 277 extending through the plurality of alternating material layers 275 to the silicon substrate 200. This channel hole 277 may be formed using any of the processes described throughout this disclosure. As shown, the channel hole 277 may be approximately perpendicular to the plurality of alternating material layers 275. The memory structure may also include a channel within the channel hole 277. The channel may include a tunneling layer 214 surrounding the interior of the channel hole (and therefore surrounding the exterior of the channel) using the above layers. The channel may also include an epitaxial silicon core 242 within the tunneling layer, the epitaxial silicon core 242 contacting the silicon substrate 200. In some cases, the epitaxial silicon core 242 may extend into the silicon substrate 200 so that the epitaxial silicon core 242 begins its epitaxial growth below the top horizontal surface of the silicon substrate 200.

[0043] The memory structure may also include an epitaxial silicon layer 236 extending beyond the channel hole, wherein the epitaxial silicon layer 236 may be parallel to the plurality of alternating material layers 275. Recall that FIG. 2P represents only one of many channels in the memory structure. Thus, the epitaxial silicon layer 236 may connect the epitaxial silicon core 242 of the depicted channel to a plurality of other channels in the memory structure. For example, the epitaxial silicon cores of each channel connected by the epitaxial silicon layer 236 may be grown simultaneously from the epitaxial silicon layer 236 during the same epitaxial process.

[0044] The above process can be used to selectively grow epitaxial silicon core 242 using single crystal silicon of substrate 200. 3D NAND flash memory cells using epitaxial silicon core 242 exhibit better performance than similar memory cells using oxide cores. For example, the mobility of polycrystalline silicon is 10 to 20 times less than the mobility of epitaxial silicon.

[0045] Further processing may be performed later on the stack 224 to complete the memory array. Although these operations are beyond the scope of the present disclosure, they may include operations such as removing the sacrificial gap fill material 240 from the slits, removing the nitride layer in the stack 224, depositing a conductive metal (such as tungsten) in place of the nitride layer to form a gate electrode, performing a staircase etch on the stack, etc.

[0046] 3A illustrates a portion of a memory array 300 according to some embodiments. This portion of the memory array 300 may represent a single memory block with offset rows of channels 256. Slits 250, 252 may be used to separate this memory block from other memory blocks. This example uses 24 channels into the offset columns between the slits 250, 252. This portion of the memory array 300 may use conventional oxide or polysilicon cores for the channels. Thus, no support structure may be required, and each channel hole may be used to implement a memory cell.

[0047] In contrast, FIG. 3B illustrates a portion of the memory array 301 when a portion of the channel has been used for support structures to facilitate the epitaxial silicon channel cores according to some embodiments. As described above, the process for growing the epitaxial silicon channels of the memory cells in the memory array 301 may use a process in which a portion of the channel holes are used for support structures 254 to prevent the memory array 301 from collapsing when the sacrificial nitride layer is removed to make room for the epitaxial silicon layer. These support structures 254 may be spaced throughout the memory array to provide adequate support for the stacking of layers in the array during the manufacturing process. Note that the spacing shown in FIG. 3B is provided as an example only and is not intended to be limiting. In this example, the support structures 254 are spaced approximately every four channel holes and every other column. By using a portion of the channel holes that would otherwise be used for the memory cells for the support structures 254, this configuration does slightly reduce the bit density per area in the memory array 301.

[0048] As described above, some embodiments may use channel holes to provide support structures during the manufacturing process. Advantages of using channel holes for support structures include the ability to increase or decrease the spacing of the support structures as needed. However, some embodiments may provide support structures by using slits instead of channel holes to form the same epitaxial silicon channel. These embodiments trade the amount of support provided across the memory block for an increase in channel density.

[0049] 4A-4L illustrate progressive steps in a manufacturing process of a memory structure according to some embodiments that utilize slits separating memory blocks for support structures when growing epitaxial silicon channels for individual memory cells. FIG. 4A illustrates a channel hole 401 in a stack 400 having epitaxial silicon 406 grown from a substrate 400 according to some embodiments. The channel hole 401 and the epitaxial silicon 406 may be formed using the processes described above with respect to FIGS. 2A-2F . In this example, instead of using one of the channel holes 401 for a support structure, each of the channel holes 401 may be used to form a channel for a memory cell. FIG. 4B illustrates the channel hole 401 after being lined with a tunneling layer 408. The tunneling layer may be formed as described in detail above with respect to FIG. 2G . FIG. 4C illustrates the channel hole 401 filled with a sacrificial gap fill material 410, which may be formed as described in detail above with respect to FIG. 2H .

[0050] FIG. 4D illustrates slits 412, 413 that may be formed on either side of a memory block in accordance with some embodiments. It should be understood that, although only two channel holes are illustrated in FIG. 4D, there may be many additional channels between the slits 412, 413. For example, the slits 412, 413 may surround a memory block having a block width of 24 channels. These channels may be arranged in a honeycomb pattern consisting of two offset columns of channels, each column having 12 channels. There may be multiple pairs of such offset columns of 24 channels in the block. Typically, the slits 412, 413 are only etched to a certain depth above the substrate 400 but below the first oxide layer 417 in the alternating material layers forming the memory cells. For example, the slit 213 is etched to a certain depth below the first oxide layer 417 and within the sacrificial nitride layer 415. However, in order to provide a support structure when the epitaxial silicon layer and the channel core are later fabricated, the slits may undergo additional or extended etching processes to increase the depth of the slits. For example, a bottom punch etch may be used to etch the slit 412 to a depth below the top of the substrate 400. This allows the slit 412 to act as a support structure anchored to the substrate 400, rather than allowing it to float on top of the substrate.

[0051] 4E illustrates slots 412 designated as support structures filled with gap fill material 414, according to some embodiments. In this example, alternating slots may be used as support structures in a memory array. Thus, slots 413 may be kept at a shallow depth, while slots 412 may be etched to a depth below substrate 400 and filled with gap fill material 414, which may serve as a support structure during the growth of the epitaxial silicon layer.

[0052] FIG. 4F illustrates the removal of sacrificial nitride layer 415 according to some embodiments. As described above with respect to FIG. 2J , sacrificial nitride layer 415 may be exposed to an etching process through slot 413 to selectively remove sacrificial nitride layer 415. Although not explicitly shown in FIG. 4F , slot 413 may have a protective liner material (e.g., carbon) applied to the sidewalls of slot 413 to prevent the etching process from removing the nitride layer from the alternating material layers later used to form the memory cell. An additional bottom punch etch may be applied to remove the protective liner from the bottom of slot 213, exposing sacrificial nitride layer 415 to the etching process.

[0053] 4G illustrates the removal of the tunneling layer 408 from the bottom of the channel according to some embodiments. For example, the layers used in the tunneling layer 408 can be selectively removed by a wet and / or dry etching process as described above. After removing the exposed portion of the tunneling layer 408 at the bottom of the channel hole, the gap fill material 414 can provide a support structure for the stack 400 to prevent the stack 400 from collapsing after exposing the gap 416 between the substrate 400 and the first oxide layer 417.

[0054] FIG. 4H illustrates the removal of sacrificial gap fill material 410 from channel hole 401 using selective etching. FIG. 4I illustrates the epitaxial growth of epitaxial silicon layer 420 in gap 416. As described above, epitaxial silicon layer 420 may grow until it begins to fill channel hole 401. FIG. 4J illustrates the formation of hole 422 in epitaxial silicon layer 420 using a bottom punch etching process to expand slot 413. FIG. 4K illustrates slot 413 filled with gap fill material 424. FIG. 4L illustrates the growth of epitaxial silicon core 426 in each channel in the memory block. Each of these steps may be performed as described in detail above in conjunction with FIGS. 2A-2P.

[0055] The channels in the final stack 400 shown in FIG. 4L can be substantially the same as the channels in the final stack 224 in FIG. 2P , with alternating material layers 475 and channel holes 477 lined with tunneling layers 408 and filled with epitaxial silicon cores 426. However, in a memory structure including this stack 400, it is not necessary to set aside any channels as support structures. Instead, maximum channel density can be achieved by using slits as support structures during the manufacturing process. As described above, additional processing steps beyond the scope of the present disclosure can then be performed on the stack 400 to complete the fabrication of the memory structure, such as removing alternating nitride layers, forming conductive layers (such as tungsten layers) to form gate electrodes, performing step etching, etc.

[0056] FIG. 5 illustrates a top view of a portion of a memory array 500 according to some embodiments. In this example, all of the channel holes 456 may be used to form channels for the memory cells. Alternating slits 550 may be used to provide support structures during the manufacturing process, while the remaining slits 552 may be used to provide access to the sacrificial nitride layer during the manufacturing process as described above. Note that the use of alternating slits 550 is used only as an example and is not meant to be limiting. Depending on the block width of each memory block, other embodiments may use one of every three slits, every four slits, etc., based on the number of channels in each block and the amount of support needed to prevent collapse.

[0057] As an alternative to using only channel holes as support structures or only slits as support structures, some embodiments may use a combination of slits and channel holes to provide support structures. This allows for extremely flexible spacing of support structures. Using slits can still minimize the number of channel holes sacrificed as support structures, while still allowing multiple channel holes to provide additional support structures as needed.

[0058] 6A-6H illustrate progressive steps for forming a stack 600 including support structures in both channel holes and slits according to some embodiments. FIG. 6A illustrates a stack 600 having a channel hole filled with a support structure 604. Additional channel holes with support structures may also be present in the stack 600, which are not explicitly shown in FIG. 6A. The stack 600 may also include a channel hole filled with a gap fill material 602, wherein a tunneling layer 603 separates the gap fill material 602 from epitaxial silicon 611 grown from the substrate 601. Note that there may also be many additional channel holes in the stack 600 that are not visible in FIG. 6A. The stack 600 may also include a slit 606 with a liner that is etched to a level above the substrate 601 and contacts the sacrificial nitride layer 610. Another slit may be filled with a gap fill material 608 and may extend down into the substrate 601 to serve as a support structure.

[0059] The remaining steps of growing epitaxial silicon into the channels of stack 600 can be performed as described in detail above. For example, FIG. 6B illustrates the removal of sacrificial nitride layer 610 to expose gap 612 when stack 600 is supported by a support structure. FIG. 6C illustrates the removal of the portion of tunneling layer 603 exposed in gap 612. FIG. 6D illustrates the removal of gap filler material 602 in channel hole 614. FIG. 6E illustrates the growth of epitaxial silicon layer 616 in gap 612. FIG. 6F illustrates the result of bottom punch etching to extend a hole 618 through epitaxial silicon layer 616 for slit 606. FIG. 6G illustrates gap filler material 620 in slit 606. FIG. 6H illustrates the growth of epitaxial silicon core 622 in channel hole 614.

[0060] FIG. 7 illustrates a top view of a portion of a memory array 700 according to some embodiments. In this example, a majority of the channel holes may be used to form channels for the memory cells. Alternating slits 750 may be used to provide support structures during the manufacturing process, while the remaining slits 752 may be used to provide access to the sacrificial nitride layer during the manufacturing process as described above. As an alternative to using only slits as support structures, this hybrid example uses a combination of slits and channel holes 756 to provide the support structure described. This makes the spacing of the support structures very configurable. Using slits minimizes the number of channel holes that are sacrificed as support structures, while still allowing multiple channel holes to provide additional support structures as needed.

[0061] As shown in this implementation, the processing described herein can be used to form a 3D NAND memory array 700, which includes a silicon substrate and a plurality of alternating material layers arranged in a vertical stack on the silicon substrate. A plurality of channel holes can extend through the alternating material layers. A plurality of support structures extending through the plurality of alternating material layers into the silicon substrate can provide support during the manufacture of the memory array 700. The support structure can include a metal that fills one or more of the channel holes 756. The support structure can also include a gap filling material that fills the slits 750 in the memory array 700. Some embodiments can use a combination of metal filled channel holes and / or gap filling materials in one or more slits in any combination and without limitation.

[0062] FIG8 depicts a flow chart 800 of a method for manufacturing a 3D NAND memory structure according to some embodiments. The method may be performed in various processing chambers in a semiconductor processing system as shown in FIG1 . The method may include the following steps: forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate (802). The alternating layers may include nitride layers and oxide layers formed in a stack as described above in FIGS. 2A-2D . The method may also include the following steps: etching a channel hole extending through the plurality of alternating material layers to the silicon substrate (804). The channel hole may be etched using a bottom punch etch to penetrate the silicon substrate, as described above in FIG. 2D .

[0063] The method may additionally include the step of forming a tunneling layer surrounding the channel hole and contacting the plurality of alternating material layers (806). The tunneling layer in the channel hole may be formed as described in FIGS. 2G-2K by depositing a tunneling oxide (including layers as described above) and selectively removing portions of the tunneling layer exposed to an etching process at the bottom of the channel hole.

[0064] The method may further include the steps of epitaxially growing an epitaxial silicon core from the silicon substrate through the channel hole (808) within the tunneling layer. The epitaxial silicon core may be grown using the steps described throughout the present disclosure. For example, the steps of growing the epitaxial silicon core may include the steps of etching a slit in the memory structure extending through multiple alternating material layers to a sacrificial nitride layer above the silicon substrate, as shown in FIG2I. The sacrificial nitride layer may be exposed to an etching process configured to selectively etch the sacrificial nitride layer, as shown in FIGS. 2J-2L. An epitaxial silicon layer may be epitaxially grown from the silicon substrate to replace the sacrificial nitride layer, as shown in FIG2M. In some embodiments, a support structure may be formed by etching a second channel hole extending through multiple alternating material layers into the silicon substrate and filling the second channel hole with a gap fill material as a support structure.

[0065] It should be understood that the specific steps in FIG. 8 provide specific methods for manufacturing 3D NAND memory structures according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. In addition, the individual steps shown in FIG. 8 may include multiple sub-steps that may be performed in various orders suitable for the individual steps. In addition, additional steps may be added or deleted depending on the specific application. Many variations, modifications, and substitutions also fall within the scope of the present disclosure.

[0066] As used herein, the term "about" or "approximately" or "substantially" may be interpreted as being within the range expected by one of ordinary skill in the art based on the specification.

[0067] In the foregoing description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, it is apparent that some embodiments may be practiced without some of these specific details. In other cases, known structures and devices are represented in block diagram form.

[0068] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the foregoing description of various embodiments will provide a feasible disclosure for implementing at least one embodiment. It should be understood that various changes may be made to the function and arrangement of elements without departing from the spirit and scope of some embodiments set forth in the accompanying claims.

[0069] Specific details are given in the foregoing description to provide a comprehensive understanding of the embodiments. However, it should be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been represented as components in block diagram form so as not to obscure the embodiments with unnecessary detail. In other cases, well-known circuits, processes, algorithms, structures, and techniques may have been depicted without unnecessary detail so as not to obscure the embodiments.

[0070] In addition, please note that individual embodiments may be described as processes depicted in a flow chart, a schematic diagram of a process, a schematic diagram of a data flow, a structure diagram, or a block diagram. Although a flow chart may describe the operations as sequential processes, many of these operations may be performed in parallel or simultaneously. In addition, the order of the operations may be rearranged. When the operations of the process are completed, the process may be terminated, but the process may have additional steps not included in the figure. The process may correspond to a method, a function, a procedure, a routine, a subroutine, etc. When the process corresponds to a function, the termination of the process corresponds to the function returning to the calling function or the main function.

[0071] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine executable instruction may represent any combination of a process, function, subroutine, program, routine, subroutine, module, software package, class, or instruction, data structure, or program statement. A code segment may be coupled to another code segment or hardware circuit by transmitting and / or receiving information, data, actual parameters, formal parameters, or memory contents. Information, actual parameters, formal parameters, data, etc. may be transmitted, forwarded, or transmitted via any suitable means, including memory sharing, information transmission, token transmission, network transmission, etc.

[0072] In addition, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented by software, firmware, middleware, or microcode, program code or code segments that perform the necessary tasks may be stored in a machine-readable medium. A processor may perform the necessary tasks.

[0073] In the foregoing description, features are described with reference to specific embodiments thereof, but it should be appreciated that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or in combination. In addition, the embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the present description. Therefore, the description and drawings should be considered illustrative rather than restrictive.

[0074] In addition, for the purpose of illustration, the method is described in a specific order. It should be understood that in alternative embodiments, these methods can be performed in an order different from the described order. It should also be understood that the above methods can be performed by hardware elements, or can be implemented with a sequence of machine executable instructions, which can be used to make a machine (such as a general or special processor or a logic circuit programmed with instructions) perform these methods. These machine executable instructions can be stored on one or more machine-readable media, such as CD-ROM or other types of optical disks, floppy disks, ROM, RAM, EPROM, EEPROM, magnetic cards or optical cards, flash memory or other types of machine-readable media suitable for storing electronic instructions. Alternatively, these methods can be performed by a combination of hardware and software.

Claims

1. A three-dimensional (3D) NAND memory structure, comprising: Silicon substrate; A plurality of alternating material layers, the plurality of alternating material layers are arranged on the silicon substrate as a vertical stack, wherein a channel hole passes through the plurality of alternating material layers and extends to the silicon substrate, wherein the channel hole is perpendicular to the plurality of alternating material layers; and a channel within the channel aperture, wherein the channel comprises: a tunneling layer surrounding an interior of the channel hole and contacting the plurality of alternating material layers; and An epitaxial silicon core contacts the silicon substrate in the tunneling layer. 2 . The 3D NAND memory structure of claim 1 , wherein the silicon substrate comprises single crystal silicon, the epitaxial silicon core growing from the single crystal silicon through the channel hole. 3 . The 3D NAND memory structure of claim 1 , wherein the alternating material layers comprise alternating layers of oxide material and nitride material.

4. The 3D NAND memory structure of claim 1, wherein the alternating material layers include alternating layers of an oxide material and a metal, wherein the metal forms a gate electrode for each memory cell in the memory structure.

5. The 3D NAND memory structure of claim 1, wherein the epitaxial silicon core extends into the silicon substrate.

6. The 3D NAND memory structure according to claim 1, further comprising: An epitaxial silicon layer extends beyond the channel hole, wherein the epitaxial silicon layer is between the silicon substrate and the plurality of alternating material layers, and the epitaxial silicon layer connects the epitaxial silicon core to a plurality of other channels in the memory structure.

7. The 3D NAND memory structure according to claim 6, further comprising: A support structure extends through the plurality of alternating material layers and the epitaxial silicon layer and into the silicon substrate.

8. A method of manufacturing a three-dimensional (3D) NAND memory structure, the method comprising the steps of: forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate; etching a via hole extending through the plurality of alternating material layers to the silicon substrate; forming a tunneling layer surrounding the channel hole and contacting the plurality of alternating material layers; and An epitaxial silicon core is epitaxially grown from the silicon substrate in the tunneling layer through the channel hole.

9. The method according to claim 8, further comprising the steps of: Slits are etched in the memory structure, the slots extending through the plurality of alternating material layers to a sacrificial nitride layer above the silicon substrate.

10. The method according to claim 9, further comprising the steps of: The sacrificial nitride layer is exposed to an etching process configured to selectively etch the sacrificial nitride layer.

11. The method according to claim 10, further comprising the steps of: A portion of the tunnel layer that is exposed after removing the sacrificial nitride layer is removed.

12. The method according to claim 10, further comprising the steps of: An epitaxial silicon layer is epitaxially grown from the silicon substrate to replace the sacrificial nitride layer.

13. The method according to claim 8, further comprising the steps of: etching a second via hole extending through the plurality of alternating material layers into the silicon substrate; and The second via hole is filled with a gap filling material as a support structure.

14. A three-dimensional (3D) NAND memory array comprising: Silicon substrate; a plurality of alternating material layers arranged in a vertically stacked arrangement on the silicon substrate, wherein a plurality of via holes extend through the plurality of alternating material layers; and A plurality of support structures extend through the plurality of alternating material layers into the silicon substrate.

15. The 3D NAND memory array of claim 14, wherein the plurality of support structures comprises a metal filling one or more of the plurality of channel holes.

16. The 3D NAND memory array of claim 14 wherein the plurality of support structures comprises gap fill material in slots in the memory array.

17. The 3D NAND memory array of claim 16 wherein alternating slits in the memory array form the support structure.

18. The 3D NAND memory array of claim 14, wherein the plurality of support structures comprises a combination of: a gap-fill material in one or more slots in the memory array; and A metal fills one or more via holes of the plurality of via holes.

19. The 3D NAND memory array of claim 14, further comprising: a plurality of channels, the plurality of channels being within the plurality of channel holes, the plurality of channels comprising: a tunneling layer surrounding an interior of the channel hole and contacting the plurality of alternating material layers; and An epitaxial silicon core contacts the silicon substrate in the tunneling layer.

20. The 3D NAND memory array of claim 19, further comprising: An epitaxial silicon layer is disposed between the silicon substrates in the plurality of alternating material layers, wherein the epitaxial silicon layer connects the epitaxial silicon cores of the plurality of channels.

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