Method for forming silicon surface lead structure

Abstract

The invention relates to a method for forming a silicon surface lead structure, which can form an insulative lead structure on the surface of a common silicon wafer, and comprises the following steps of: providing a substrate which is made of low-resistance silicon and is sequentially provided with a first isolation region, a lead region and a second isolation region along a first direction parallel to the surface of the substrate; forming a first oxide layer covering the top surface of the substrate; removing a part of the first oxide layer and a part of thickness of the substrate material below the first oxide layer to form an isolation channel; forming a second oxide layer covering the side wall of the isolation channel; isotropically corroding the bottom surface of the isolation channel in a gaseous state to form an expansion channel; and oxidizing the extended channels by using a wet oxygen process to form a fourth oxide layer covering the surfaces of the extended channels, and enabling the fourth oxide layer to be communicated with the side walls of the two adjacent extended channels and to form a lead isolation structure together with the second oxide layer. According to the invention, the device performance can be improved while the device cost is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for forming a silicon surface lead structure. Background Art

[0002] Micro-Electro-Mechanical Systems (MEMS) is a technology that integrates micro-mechanical and electronic components and is widely used in various sensors and actuators. In the design and manufacturing process of MEMS devices, it is crucial to ensure the effective input and output of electrical signals. At present, common solutions include using metal or low-resistance silicon as wires and insulating and isolating them through insulating materials such as silicon oxide. Although the above solutions have been widely used in the field of MEMS device manufacturing, there are shortcomings such as introducing thermal stress problems and increasing production costs. In view of this, it is necessary to develop a new lead structure to reduce device costs and improve device performance. Summary of the invention

[0003] The technical problem solved by the embodiments of the present application is to provide a method for forming a silicon surface lead structure, which can reduce device costs while improving device performance.

[0004] To solve the above problems, on the one hand, an embodiment of the present application provides a method for forming a silicon surface lead structure, comprising the following steps: providing a substrate, the material of the substrate is low-resistance silicon, and the substrate is sequentially composed of a first isolation region, a lead region and a second isolation region along a first direction parallel to the surface of the substrate; forming a first oxide layer covering the top surface of the substrate; removing part of the first oxide layer and part of the thickness of the substrate material thereunder, and forming isolation channels in the first isolation region and the second isolation region respectively; forming a second oxide layer, and the second oxide layer covers the side walls of the isolation channel; isotropically corroding the bottom surface of the isolation channel in a gaseous state to form an extended channel below the isolation channel, and one side wall of the extended channel extends to the lead region; oxidizing the extended channel by a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel, and the fourth oxide layer connects two adjacent side walls of the extended channel and forms a lead isolation structure together with the second oxide layer.

[0005] Optionally, in the step of providing a substrate, the resistivity of the low-resistance silicon is less than 0.02Ω·cm.

[0006] Optionally, the step of removing part of the first oxide layer and part of the thickness of the substrate material thereunder to form an isolation channel in the first isolation region and the second isolation region, respectively, further includes: removing part of the first oxide layer located in the first isolation region and the second isolation region to expose the top surface of the substrate on both sides of the lead region to form a patterned first oxide layer; using the patterned first oxide layer as a mask, removing part of the thickness of the substrate material to form an isolation channel surrounded by the remaining substrate.

[0007] Optionally, in the step of removing a portion of the first oxide layer located in the first isolation region and the second isolation region to expose the top surface of the substrate on both sides of the lead region to form a patterned first oxide layer, an inductively coupled plasma process is used to remove a portion of the first oxide layer located in the first isolation region and the second isolation region; in the step of using the patterned first oxide layer as a mask to remove a portion of the thickness of the substrate material to form an isolation channel surrounded by the remaining substrate, a deep reactive ion etching process is used to remove a portion of the thickness of the substrate material.

[0008] Optionally, the step of forming a second oxide layer, wherein the second oxide layer covers the side walls of the isolation trench, further includes: using a thermal oxidation process to form a second oxide layer covering the side walls of the isolation trench and a third oxide layer covering the bottom surface of the isolation trench; and using an inductively coupled plasma process to remove the third oxide layer to expose the bottom surface of the isolation trench.

[0009] Optionally, in the step of forming a second oxide layer covering the sidewalls of the isolation trench and a third oxide layer covering the bottom surface of the isolation trench by using a thermal oxidation process, the thickness of the second oxide layer and the third oxide layer is 0.1 micrometer to 1 micrometer.

[0010] Optionally, in the step of isotropically etching the bottom surface of the isolation trench in the gaseous state to form an extended trench below the isolation trench, the distance between two adjacent side walls of the extended trench is 2 microns to 6 microns.

[0011] Optionally, the gaseous isotropic etching of the bottom surface of the isolation trench, in the step of forming an extended trench below the isolation trench, uses XeF2 gas to etch the bottom surface of the isolation trench.

[0012] Optionally, in the step of oxidizing the extended channel using a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel, the fourth oxide layer and the second oxide layer are interconnected to form a lead isolation structure, which insulates and isolates a portion of the thickness of the base material on the upper part of the lead area, thereby forming a lead structure on the silicon surface and a lead isolation structure surrounding the lead structure.

[0013] Optionally, after the step of oxidizing the extended channel using a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel, the step further includes: removing the first oxide layer on the surface of the lead area to expose the underlying substrate material.

[0014] Compared with the prior art, the technical solution of the embodiment of the present application has the following advantages:

[0015] The method for forming a silicon surface lead structure provided in an embodiment of the present application utilizes an etching process and a thermal oxidation process to form mutually interconnected oxide layers in the lead area, thereby providing good electrical isolation and mechanical support for the lead structure. In addition, the thermal stress of the oxide layer and the lead structure matches each other, thereby reducing thermal stress problems caused by temperature fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0017] Figure 1-Figure 9 This is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a silicon surface lead junction provided by the present invention. DETAILED DESCRIPTION

[0018] As can be seen from the background technology, the existing use of metal or low-resistance silicon as a conductor has problems such as introducing thermal stress and increasing production costs.

[0019] Specifically, if metal is used as a conductor, the mismatch in thermal expansion coefficients between metal and silicon-based materials may cause thermal stress in the device when the temperature changes, which may affect the structural stability and long-term reliability of the device. In addition, the deposition process of metal conductors not only increases production costs, but also increases the complexity of the process.

[0020] On the other hand, if low-resistance silicon is used as the conductor, for example, SOI (Silicon on Insulator) silicon wafers are used, low-resistance silicon is used in the device layer and processed into conductors. Although the thermal expansion coefficient mismatch problem of metal conductors can be solved to a certain extent, this method will significantly increase the cost of silicon wafers.

[0021] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a silicon surface lead structure, comprising the following steps:

[0022] Providing a substrate, wherein the material of the substrate is low-resistance silicon, and the substrate is sequentially divided into a first isolation region, a lead region, and a second isolation region along a first direction parallel to a surface of the substrate;

[0023] forming a first oxide layer covering the top surface of the substrate;

[0024] Removing part of the first oxide layer and part of the thickness of the substrate material thereunder, and forming isolation trenches in the first isolation region and the second isolation region respectively;

[0025] forming a second oxide layer, wherein the second oxide layer covers the sidewalls of the isolation trench;

[0026] Gaseously corroding the bottom surface of the isolation trench to form an extended trench below the isolation trench, wherein a side wall of the extended trench extends to the lead region;

[0027] The extended channel is oxidized by a wet oxygen process to form a fourth oxide layer connecting two adjacent side walls of the extended channel.

[0028] The method for forming a silicon surface lead structure provided in this embodiment utilizes an etching process and a thermal oxidation process to form interconnected oxide layers in the lead area, thereby providing good electrical isolation and mechanical support for the lead structure. The thermal stress of the oxide layer and the lead structure matches each other, thereby reducing thermal stress problems caused by temperature fluctuations.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figures 1 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a silicon surface lead structure provided by the present invention.

[0031] refer to Figure 1 , providing a substrate 110, wherein the material of the substrate 110 is low-resistance silicon, and the substrate 110 is sequentially divided into a first isolation region 102a, a lead region 101 and a second isolation region 102b along a first direction parallel to the substrate surface.

[0032] The material of the substrate 110 is low-resistance silicon. Low-resistance silicon is a silicon material with a relatively low resistivity. The resistivity of low-resistance silicon is generally less than 0.02Ω·cm, and in some embodiments may be further less than 0.01Ω·cm. Specifically, the resistivity of low-resistance silicon may range from 0.001Ω·cm to 0.005Ω·cm. Low-resistance silicon can be obtained by doping, that is, introducing impurity atoms into the silicon lattice to change its conductivity. In some embodiments, the substrate 110 is a low-resistance silicon wafer, which is a silicon wafer made of a low-resistance silicon material and has a relatively low resistivity.

[0033] Since low-resistance silicon has a lower resistivity, it can be used to form a lead structure to ensure that electrical signals can be effectively transmitted; and since the thermal expansion coefficient of low-resistance silicon matches that of other silicon-based materials, the semiconductor devices subsequently manufactured will not produce thermal stress problems when the temperature fluctuates.

[0034] The substrate 110 can be further divided into a lead area 101 and a first isolation area 102a and a second isolation area 102b respectively located on both sides of the lead area 101. The lead structure formed subsequently is located in the lead area 101, and the isolation structures formed on both sides of the lead structure are respectively located in the first isolation area 102a and the second isolation area 102b, and the isolation structure can be a silicon oxide layer of a certain thickness to provide electrical isolation for the lead.

[0035] refer to Figure 2 , forming a first oxide layer 120 covering the top surface of the substrate 110 .

[0036] In some embodiments, the first oxide layer 120 is a silicon oxide layer, and the silicon oxide layer can completely cover the top surface of the substrate 110 .

[0037] As a specific example, a plasma enhanced chemical vapor deposition (PECVD) process may be used to grow silicon dioxide on the top surface of the substrate 110 to form the first oxide layer 120 having a thickness of about 1 micron to 3 microns.

[0038] refer to Figure 3 and Figure 4 , remove part of the first oxide layer 120 and part of the thickness of the substrate material thereunder, and form isolation trenches 130a and 130b in the first isolation region 102a and the second isolation region 102b respectively.

[0039] In some embodiments, this step may further include:

[0040] refer to Figure 3 , removing a portion of the first oxide layer 120 located in the first isolation region 102a and the second isolation region 102b, exposing the top surface of the substrate 110 on both sides of the lead region 101 to form a patterned first oxide layer 121.

[0041] The patterned first oxide layer 121 is formed with openings, and the openings expose the top surface of the substrate 110. The openings are respectively located in the first isolation region 102a and the second isolation region 102b and are adjacent to the lead region 101, so as to expose the substrate material on both sides of the lead region 101.

[0042] As an example, a photolithography and etching process may be used to form the patterned first oxide layer 121, and the specific steps are as follows:

[0043] forming a pattern layer (not shown) on the first oxide layer 120, wherein the pattern layer exposes a portion of the first oxide layer 120;

[0044] The pattern layer is used as a mask to etch the first oxide layer 120 exposed by the pattern layer, and the remaining first oxide layer material after etching serves as the patterned first oxide layer 121 .

[0045] In this embodiment, the graphic layer can be a patterned photoresist layer. After the photoresist layer is formed, a dry etching process is used to etch the first oxide layer 120 located below the graphic layer opening along the graphic layer opening. During the etching process, the part of the first oxide layer material not covered by the photoresist will be removed, while the part of the first oxide layer material covered by the photoresist will be retained.

[0046] As a specific example, the first oxide layer material can be removed by an inductively coupled plasma (ICP) process. ICP etching is a high-density plasma source etching technology with a high etching rate and a high degree of anisotropy. Under the action of high-density plasma, the exposed first oxide layer material is quickly and accurately removed until the underlying substrate material is exposed. Due to the high anisotropy, an almost perfect vertical sidewall can be formed after the ICP etching is completed.

[0047] After the etching is completed, the remaining photoresist is removed using an appropriate solvent or oxygen plasma treatment, leaving the patterned first oxide layer 121.

[0048] refer to Figure 4 Using the patterned first oxide layer 121 as a mask, a portion of the substrate material is removed to form isolation trenches 130 a and 130 b surrounded by the remaining substrate 111 .

[0049] In this step, a dry etching process can be used to remove a portion of the substrate material. After etching, the remaining substrate 111 forms a groove on both sides of the lead area 101, namely, isolation trenches 130a and 130b. The isolation trenches 130a and 130b are prepared for the subsequent formation of isolation structures.

[0050] In some embodiments, the width of the isolation trenches 130a and 130b may be equal to or slightly smaller than the width of the lead region 101, for example, 5 microns to 20 microns; the depth of the isolation trenches 130a and 130b may be equal to or slightly smaller than their own width.

[0051] As a specific example, a deep reactive ion etching (DRIE) process can be used to etch the substrate material to form the isolation trenches 130a and 130b. DRIE is a plasma-based dry etching technology that uses a high-density plasma source to generate active ions and free radicals. The active molecules can selectively remove materials on the silicon wafer. The DRIE process can form almost vertical sidewalls on the substrate 110, which is convenient for the subsequent formation of fine device structures.

[0052] refer to Figure 5 and Figure 6 , forming a second oxide layer 131, which covers the sidewalls of the isolation trenches 130a and 130b.

[0053] In some embodiments, this step may further include:

[0054] refer to Figure 5 A second oxide layer 131 covering the sidewalls of the isolation trenches 130a and 130b and a third oxide layer 132 covering the bottom surfaces of the isolation trenches 130a and 130b are formed by a thermal oxidation process.

[0055] In this step, a thermal oxidation process is used to grow silicon oxide, thereby forming a silicon dioxide layer on the sidewalls and bottom surface of the isolation trenches 130a and 130b. The thickness of the generated silicon dioxide can be controlled to be between 0.1 microns and 1 microns by controlling the parameters of the thermal oxidation process. The thermal oxidation process uses oxygen or water vapor to react with silicon at high temperature to generate silicon dioxide. While using the thermal oxidation process to generate silicon dioxide, a portion of the silicon material will also be consumed.

[0056] The second oxide layer 131 formed in this step can provide electrical isolation for the subsequently formed leads, improve mechanical stability, and protect the silicon structure shielded by the second oxide layer 131 from gaseous corrosion in subsequent steps.

[0057] refer to Figure 6 , the third oxide layer 132 is removed until the bottom surfaces of the isolation trenches 130a and 130b are exposed.

[0058] In this step, a dry etching process may be used to remove the third oxide layer 132 located at the bottom of the isolation trenches 130a and 130b, while retaining the second oxide layer 131 located at the sidewalls of the isolation trenches 130a and 130b. It is understood that the second oxide layer 131 at the sidewalls of the isolation trenches 130a and 130b may also be etched a small amount during the etching process, but most of the thickness of the second oxide layer material will be retained.

[0059] As a specific example, an inductively coupled plasma (ICP) process can be used to remove silicon oxide as an isolation layer material. ICP etching is a high-density plasma source etching technology with a high etching rate and a high degree of anisotropy. Under the action of high-density plasma, the exposed third oxide layer 132 is quickly and accurately removed until the substrate material under the third oxide layer 132 is exposed. Due to the high anisotropy, an almost perfect vertical sidewall can be formed after etching, and the oxide layer material outside the target portion can be retained to the maximum extent to serve as a protective layer in the subsequent gaseous etching step.

[0060] refer to Figure 7 The bottom surfaces of the isolation trenches 130 a and 130 b are isotropically etched in a gaseous state to form extended trenches 140 a and 140 b below the isolation trenches 130 a and 130 b , and a side wall of the extended trenches 140 a and 140 b extends to the lead region 101 .

[0061] In this step, a gaseous etching process is used to etch the bottom surfaces of the exposed isolation trenches 130a and 130b. The gaseous etching process uses specific gas chemicals to react with the substrate material at the bottom surfaces of the isolation trenches 130a and 130b to remove a certain thickness of the substrate material in each direction, thereby forming corresponding extended trenches 140a and 140b below the isolation trenches 130a and 130b, respectively.

[0062] Specifically in this embodiment, the substrate 111 is subjected to gaseous etching using xenon difluoride (XeF2) gas to form a gaseously etched substrate 112. The XeF2 gaseous etching process is highly selective to different materials, and has a high selectivity to silicon materials, with a good selectivity ratio between silicon and silicon dioxide. In addition, the gaseous etching process has an isotropic characteristic, and the XeF2 gaseous etching effect is uniform in all directions of the silicon material, not only in the direction perpendicular to the first direction ( Figure 7 A certain thickness of silicon material can be removed in the vertical direction) or in the direction parallel to the first direction ( Figure 7 A certain thickness of silicon material is removed (in the horizontal direction) so that the sidewalls of the extended trenches 140a and 140b extend horizontally to the lead region 101. The base material in a certain space below the lead region 101 can be removed by gaseous etching, and a support structure with a certain width is retained at the bottom of the lead region 101. The support structure can be used to support the lead structure above, and the support structure can be completely oxidized in the subsequent steps to provide electrical isolation for the lead structure above.

[0063] The width of the support structure, that is, the distance between two adjacent side walls of the extended channel, is d. In some embodiments, the distance d may range from 2 microns to 6 microns.

[0064] In some embodiments, the substrate material may be silicon with a special crystal orientation, and a wet etching process may be used to etch the substrate material. The wet etching process is anisotropic etching, and selective etching may be performed in the lateral direction (the first direction in the figure), thereby reducing the thickness of the support structure in the first direction. Specifically, a certain thickness may be etched downward by DRIE, and after the sidewall is exposed, a wet process may be performed.

[0065] refer to Figure 8 The extended channels 140a and 140b are oxidized by a wet oxygen process to form a fourth oxide layer 141 covering the surfaces of the extended channels 140a and 140b. The fourth oxide layer 141 connects two adjacent extended channel sidewalls and the second oxide layer 131 to form a lead isolation structure.

[0066] In this step, a wet oxygen process is used to grow silicon oxide on the surface of the extended channels 140a and 140b, thereby forming a silicon dioxide layer on the sidewalls and bottom surfaces of the extended channels 140a and 140b. In the wet oxygen process, oxygen and water vapor react with silicon atoms on the surface of the extended channels 140a and 140b under high temperature conditions to form a uniform silicon dioxide layer. The wet oxygen process can accelerate the oxidation rate and improve the quality of the oxide film by introducing water vapor during the oxidation process. While using the wet oxygen process to generate silicon dioxide, a portion of silicon material will also be consumed. The thickness of the generated silicon dioxide layer can be controlled by controlling the parameters of the wet oxygen process. In some embodiments, the thickness of the oxide layer formed by the wet oxygen process can be between 3 microns and 8 microns, thereby forming a fourth oxide layer 141 that covers the surface of the extended channel and connects the two adjacent extended channel sidewalls. The fourth oxide layer 141 can provide mechanical support and electrical isolation for the lead structure above. Specifically, the fourth oxide layer 141 and the second oxide layer 131 formed above are interconnected to form a lead isolation structure. The lead isolation structure insulates and isolates the base material on the upper part of the lead area 101, thereby forming a lead structure 150 and a lead isolation structure surrounding the lead structure 150 on the silicon surface.

[0067] In some embodiments, the support structure may be pretreated before the extended channels 140a, 140b are oxidized using a wet oxygen process. Specifically, the silicon material forming the support structure may be processed into porous silicon before the wet oxygen oxidation. In the subsequent oxidation step, the porous silicon is more easily oxidized into silicon oxide.

[0068] refer to Fig. 9 , remove the first oxide layer on the surface of the lead area 101 until the underlying substrate material is exposed.

[0069] In this step, the oxide layer covering the surface of the lead area 101 is further removed to expose the low-resistance silicon as the base material underneath, thereby exposing the top surface of the lead structure 150. The side and bottom surfaces of the lead structure 150 are respectively covered by the second oxide layer 131 and the fourth oxide layer 141, thereby achieving complete electrical isolation.

[0070] It can be seen that the method for forming a silicon surface lead structure provided in the embodiment of the present application utilizes an etching process and a thermal oxidation process to form mutually interconnected oxide layers in the lead area, thereby providing good electrical isolation and mechanical support for the lead structure, and the thermal stress of the oxide layer and the lead structure matches each other, thereby reducing thermal stress problems caused by temperature fluctuations.

[0071] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0072] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for forming a silicon surface lead structure, characterized in that: The following steps are involved: Providing a substrate, wherein the material of the substrate is low-resistance silicon, and the substrate is sequentially divided into a first isolation region, a lead region, and a second isolation region along a first direction parallel to a surface of the substrate; forming a first oxide layer covering the top surface of the substrate; Removing part of the first oxide layer and part of the thickness of the substrate material thereunder, and forming isolation trenches in the first isolation region and the second isolation region respectively; forming a second oxide layer, wherein the second oxide layer covers the sidewalls of the isolation trench; isotropically etching the bottom surface of the isolation trench in a gaseous state to form an extended trench below the isolation trench, wherein a side wall of the extended trench extends to the lead region; The extended channel is oxidized by a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel. The fourth oxide layer connects two adjacent side walls of the extended channel and forms a lead isolation structure together with the second oxide layer.

2. The method for forming a silicon surface lead structure according to claim 1, characterized in that: In the step of providing a substrate, the resistivity of the low-resistance silicon is less than 0.02Ω·cm.

3. The method for forming a silicon surface lead structure according to claim 1, characterized in that: The step of removing part of the first oxide layer and part of the thickness of the substrate material thereunder to form isolation channels in the first isolation region and the second isolation region respectively further comprises: Removing a portion of the first oxide layer located in the first isolation region and the second isolation region to expose the top surface of the substrate at both sides of the lead region to form a patterned first oxide layer; Using the patterned first oxide layer as a mask, a portion of the thickness of the substrate material is removed to form an isolation channel surrounded by the remaining substrate.

4. The method for forming a silicon surface lead structure according to claim 3, characterized in that: In the step of removing the portion of the first oxide layer located in the first isolation region and the second isolation region to expose the top surface of the substrate on both sides of the lead region to form a patterned first oxide layer, the portion of the first oxide layer located in the first isolation region and the second isolation region is removed by using an inductively coupled plasma process; In the step of using the patterned first oxide layer as a mask to remove a portion of the thickness of the substrate material to form an isolation channel surrounded by the remaining substrate, a deep reactive ion etching process is used to remove a portion of the thickness of the substrate material.

5. The method for forming a silicon surface lead structure according to claim 1, characterized in that: The step of forming a second oxide layer, wherein the second oxide layer covers the sidewalls of the isolation trench further comprises: Forming a second oxide layer covering the sidewalls of the isolation trench and a third oxide layer covering the bottom surface of the isolation trench by a thermal oxidation process; The third oxide layer is removed by an inductively coupled plasma process until a bottom surface of the isolation trench is exposed.

6. The method for forming a silicon surface lead structure according to claim 5, characterized in that: In the step of forming the second oxide layer covering the sidewalls of the isolation trench and the third oxide layer covering the bottom surface of the isolation trench by using a thermal oxidation process, the thickness of the second oxide layer and the third oxide layer is 0.1 micrometer to 1 micrometer.

7. The method for forming a silicon surface lead structure according to claim 1, characterized in that: In the step of isotropically etching the bottom surface of the isolation trench in the gaseous state to form an extended trench below the isolation trench, the distance between two adjacent side walls of the extended trench is 2 microns to 6 microns.

8. The method for forming a silicon surface lead structure according to claim 1, wherein: The gaseous isotropic etching is performed on the bottom surface of the isolation trench. In the step of forming an extended trench below the isolation trench, XeF2 gas is used to etch the bottom surface of the isolation trench.

9. The method for forming a silicon surface lead structure according to claim 1, characterized in that: In the step of oxidizing the extended channel using a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel, the fourth oxide layer and the second oxide layer are interconnected to form a lead isolation structure together, and the lead isolation structure insulates and isolates a portion of the thickness of the substrate material on the upper part of the lead area, thereby forming a lead structure on the silicon surface and a lead isolation structure surrounding the lead structure.

10. The method for forming a silicon surface lead structure according to claim 1, characterized in that: After the step of oxidizing the extended channel by a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel, the method further includes: The first oxide layer on the surface of the lead area is removed until the underlying substrate material is exposed.

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