Chip testing system and method

Abstract

The invention discloses a chip testing system and method, and relates to the technical field of radio frequency. The chip test system comprises a to-be-tested circuit board, a first switch assembly and a second switch assembly. The to-be-tested circuit board is used for bearing at least one to-be-tested chip; a plurality of first ports of the first switch assembly are respectively used for receiving different first test signals, and the first switch assembly is used for switching and conducting the first port of the first switch assembly corresponding to the first test signals and the first port of the circuit board to be tested based on the different first test signals; the second switch assembly is used for switching and conducting a second port of the to-be-tested circuit board corresponding to the first port of the to-be-tested circuit board and a second port of the second switch assembly based on the first port of the to-be-tested circuit board. Therefore, for different first test signals, switching conduction can be directly performed through the first switch assembly and the second switch assembly, so that support for various first test signals is realized, and the test efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of radio frequency technology, and in particular to a chip testing system and method. Background Art

[0002] With the rapid development of wireless communication technology, the industry has higher and higher requirements on the performance of wireless communication systems. In wireless communication systems, chips are important components of wireless communication systems, and various performance parameters of chips need to be tested. However, the efficiency of testing various performance parameters of chips is currently low. Summary of the invention

[0003] The present application proposes a chip testing system and method to improve the efficiency of testing various performance parameters of a chip.

[0004] In a first aspect, an embodiment of the present application provides a chip testing system, the chip testing system comprising a circuit board to be tested, a first switch component and a second switch component; the circuit board to be tested is used to carry at least one chip to be tested; the multiple first ports of the first switch component are respectively used to receive different first test signals, the multiple second ports of the first switch component are respectively connected to the multiple different first ports of the circuit board to be tested, and the first switch component is used to switch and connect the first port of the first switch component corresponding to the first test signal and the first port of the circuit board to be tested based on different first test signals; the multiple first ports of the second switch component are respectively connected to the multiple different second ports of the circuit board to be tested, and the multiple second ports of the second switch component are respectively used to output different first signals to be detected, and the second switch component is used to switch and connect the second port of the circuit board to be tested corresponding to the first port of the circuit board to be tested and the second port of the second switch component based on the first port of the circuit board to be tested, wherein the first signal to be detected is a signal generated by the circuit board to be tested based on the first test signal.

[0005] Optionally, the first switch component includes: a first RF switch and a second RF switch; multiple first ports of the first RF switch are respectively used to receive different first test signals, and the second port of the first RF switch is connected to the first port of the second RF switch; multiple second ports of the second RF switch are respectively connected to multiple different first ports of the circuit board to be tested.

[0006] Optionally, the first switch component also includes: a third RF switch, a fourth RF switch and a fifth RF switch; the first port of the third RF switch, the first port of the fourth RF switch and the first port of the fifth RF switch are respectively connected to different second ports of the second RF switch, and multiple second ports of the third RF switch, multiple second ports of the fourth RF switch and multiple second ports of the fifth RF switch are respectively connected to multiple different first ports of the circuit board to be tested.

[0007] Optionally, the first RF switch, the second RF switch, the third RF switch, the fourth RF switch and the fifth RF switch are all single-pole multi-throw switches.

[0008] Optionally, the second switch component includes: a sixth RF switch and a seventh RF switch; multiple first ports of the sixth RF switch are respectively connected to multiple different second ports of the circuit board to be tested, and the second port of the sixth RF switch is connected to the first port of the seventh RF switch; and the multiple second ports of the seventh RF switch are respectively used to output different first signals to be detected.

[0009] Optionally, the sixth RF switch and the seventh RF switch are both single-pole multi-throw switches.

[0010] Optionally, the single-pole multi-throw radio frequency switch is a single-pole six-throw radio frequency switch.

[0011] Optionally, the chip testing system also includes: a first signal generating module and a first receiving test module; multiple output ports of the first signal generating module are respectively connected to multiple different first ports of the first switch component, and the first signal generating module is used to generate different first test signals; the input port of the first receiving test module is connected to the second port of the second switch component, and the first receiving test module is used to receive the first signal to be detected.

[0012] Optionally, the first signal generating module includes: a first noise source, a first signal source, a filtering component, a second noise source, a coupler, an eighth RF switch and a ninth RF switch; the output port of the first noise source, the second port of the ninth RF switch and the first port of the coupler are respectively connected to multiple different first ports of the first switch component; the first noise source is used to generate a first noise signal; the output port of the first signal source is connected to the first port of the eighth RF switch, and the first signal source is used to generate a first RF signal; multiple second ports of the eighth RF switch are respectively connected to multiple different first ports of the filtering component, the first port of the ninth RF switch and the third port of the coupler; multiple different second ports of the filtering component are respectively connected to multiple different first ports of the ninth RF switch, and the filtering component is used to generate multiple different filtered signals based on the first RF signal; the output port of the second noise source is connected to the second port of the coupler, and the second noise source is used to generate a second noise signal; the coupler is used to couple the second noise signal and the first RF signal to generate a second RF signal.

[0013] Optionally, the filtering component includes: a low-frequency bandpass filter, an intermediate frequency bandpass filter and a high-frequency bandpass filter; the first port of the low-frequency bandpass filter, the first port of the intermediate frequency bandpass filter and the first port of the high-frequency bandpass filter are respectively connected to multiple different second ports of the eighth RF switch, and the second port of the low-frequency bandpass filter, the second port of the intermediate frequency bandpass filter and the second port of the high-frequency bandpass filter are respectively connected to multiple different first ports of the ninth RF switch; the low-frequency bandpass filter is used to filter the first RF signal to obtain a first filtered signal; the intermediate frequency bandpass filter is used to filter the first RF signal to obtain a second filtered signal; the high-frequency bandpass filter is used to filter the first RF signal to obtain a third filtered signal.

[0014] Optionally, the first receiving test module includes: a first spectrum analyzer, a first attenuator and a first DC block; the first port of the first attenuator is connected to the second port of the second switch component, and the second port of the first attenuator is connected to the first port of the first DC block; the second port of the first DC block is connected to the input port of the first spectrum analyzer.

[0015] Optionally, the chip testing system also includes: a specified parameter testing module; a first port of the specified parameter testing module is connected to the first port of the first switch component, and a second port of the specified parameter testing module is connected to the second port of the second switch component; the specified parameter testing module is used to generate a specified parameter test signal, and is also used to receive and test a specified parameter signal to be detected, wherein the specified parameter signal to be detected is a signal generated by the circuit board to be tested based on the specified parameter test signal, and the specified parameter test signal is used to test the specified parameter performance of the circuit board to be tested.

[0016] Optionally, the specified parameter performance includes at least one of S parameter performance, stability performance and out-of-band suppression performance.

[0017] Optionally, the second port of the second switch component is also used to receive a second test signal, wherein the second port of the second switch component for receiving the second test signal is different from multiple second ports for outputting different first signals to be detected; the first port of the first switch component is also used to output a second signal to be detected, wherein the first port of the first switch component for outputting the second signal to be detected is different from multiple first ports for receiving different first test signals, and the second signal to be detected is a signal generated by the circuit board to be tested based on the second test signal; the second switch component is also used to switch on the second port of the second switch component corresponding to the second test signal and the second port of the circuit board to be tested based on the second test signal; the first switch component is also used to switch on the first port of the circuit board to be tested corresponding to the second port of the circuit board to be tested and the first port of the first switch component based on the second port of the circuit board to be tested.

[0018] Optionally, the chip testing system also includes: a second signal generating module and a second receiving test module; the output port of the second signal generating module is connected to the second port of the second switch component, and the second signal generating module is used to generate a second test signal; the input port of the second receiving test module is connected to the first port of the first switch component, and the second receiving test module is used to receive the second signal to be detected.

[0019] Optionally, the second signal generating module includes a second signal source, and the second receiving test module includes a second spectrum analyzer, a second attenuator and a second DC block; the output port of the second signal source is connected to the second port of the second switch component; the first port of the second DC block is connected to the second port of the second attenuator, and the second port of the second DC block is connected to the first port of the first switch component; the first port of the second attenuator is connected to the input end of the second spectrum analyzer.

[0020] In a second aspect, an embodiment of the present application provides a chip testing method, which is applied to a chip testing system, wherein the chip testing system includes a circuit board to be tested, a first switch component and a second switch component, and the method includes: switching on a first port of the first switch component corresponding to a first test signal and a first port of the circuit board to be tested based on the first switch component; switching on a second port of the circuit board to be tested corresponding to the first port of the circuit board to be tested and a second port of the second switch component based on the second switch component.

[0021] Optionally, the method also includes: switching on a second port of the second switch component corresponding to a second test signal and a second port of the circuit board to be tested based on the second switch component; and switching on a first port of the circuit board to be tested corresponding to the second port of the circuit board to be tested and a first port of the first switch component based on the first switch component.

[0022] The chip testing system provided in the embodiment of the present application can directly switch on the first port of the first switch component corresponding to the first test signal and the first port of the circuit board to be tested through the first switch, and then switch on the second port of the circuit board to be tested and the second port of the second switch component corresponding to the first port of the circuit board to be tested through the second switch component, for multiple different first test signals, so as to transmit the first test signal to the second port of the second switch component through the circuit board to be tested, thereby avoiding manual disconnection of the circuit, which not only improves the efficiency of testing various chip parameters, but also reduces the interference introduced by disconnecting the circuit, and improves the accuracy and reliability of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic diagram of the structure of a chip testing system provided in an embodiment of the present application is shown;

[0025] Figure 2 A schematic diagram of the structure of a chip testing system provided by another embodiment of the present application is shown;

[0026] Figure 3 A schematic diagram of the structure of a chip testing system provided by another embodiment of the present application is shown;

[0027] Figure 4A schematic diagram showing the structure of a chip testing system provided by another embodiment of the present application is shown;

[0028] Figure 5 A schematic diagram of the structure of a chip testing system provided by another embodiment of the present application is shown;

[0029] Figure 6 A schematic diagram of the structure of a chip testing system provided by another embodiment of the present application is shown;

[0030] Figure 7 A schematic diagram of the structure of a chip testing system provided by another embodiment of the present application is shown;

[0031] Figure 8 A schematic diagram of the structure of a chip testing system provided by another embodiment of the present application is shown;

[0032] Fig. 9 A method flow chart of a chip testing method provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0034] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0035] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0036] With the rapid development of wireless communication technology, the industry has higher and higher requirements on the performance of wireless communication systems. In wireless communication systems, chips are important components of wireless communication systems, and various performance parameters of chips need to be tested. However, the efficiency of testing various performance parameters of chips is currently low.

[0037] At present, various performance parameters of the chip can be tested, wherein the performance parameters may include S parameters, stability parameters, 1dB compression output power parameters, spurious radiation parameters, noise coefficient parameters, harmonic component parameters, setup time parameters, isolation parameters, RF sensitivity deterioration parameters, etc. Generally, the RF signal corresponding to the performance parameter to be tested can be generated by a signal source, and then the RF signal is input to the chip to be tested, and then the signal output by the chip to be tested is tested by the test equipment, so as to determine the required performance parameters. Then, when the next performance parameter needs to be tested, the signal source, the test equipment, and the connection between the signal source and the test equipment and the chip to be tested are manually disconnected, the test instrument is replaced, and the test path is recalibrated before testing.

[0038] However, the inventors found in their research that each time the performance parameters to be tested are changed, the test path needs to be manually adjusted, which not only results in low test efficiency, but also may introduce interference when manually adjusting the test path, thereby reducing the accuracy and reliability of the performance parameters subsequently obtained.

[0039] Therefore, in order to solve or partially solve the above problems, the present application provides a chip testing system and method.

[0040] See also Figure 1 , Figure 1 The schematic diagram of the structure of a chip testing system provided by an embodiment of the present application is shown. The chip testing system 100 includes a circuit board to be tested 130 , a first switch component 110 and a second switch component 120 .

[0041] In order to test the performance parameters of the chip, a test signal can be input to the chip, and then a signal to be detected output by the chip based on the test signal is obtained, and the signal to be detected is analyzed to determine the performance parameters of the chip. It is easy to understand that in order to facilitate testing, in some embodiments, the chip can be placed on the circuit board to be tested 130, and the chip is the chip to be tested.

[0042] The circuit board to be tested 130 can be used to carry at least one chip to be tested. Specifically, different first test signals can be obtained through multiple first ports 131 of the circuit board to be tested 130, and then the circuit board to be tested 130 can transmit the obtained first test signal to the chip to be tested, thereby inputting the first test signal to the chip to be tested. Further, the chip to be tested can output a first signal to be detected based on the first test signal, and the first signal to be detected can be transmitted to the second port 132 of the circuit board to be tested 130 for output.

[0043] In some embodiments, the first test signal may be a signal for testing generated by the first signal generating module, for example, a radio frequency signal. The first signal to be detected is a signal generated by the circuit board to be tested 130 based on the first test signal. The first signal to be detected is essentially a signal generated after the first test signal passes through the chip to be tested carried by the circuit board to be tested 130.

[0044] It should be noted that the circuit board to be tested 130 can carry one chip to be tested or multiple chips to be tested. For the performance test of multiple chips to be tested, the embodiment of the present application does not require manual disconnection of the circuit, nor does it require manual construction of a new test path before testing. Multiple chips to be tested can be directly carried by the circuit board to be tested 130, thereby improving the test efficiency and the accuracy and reliability of the performance parameters obtained by the test.

[0045] The first switch component 110 can be used to receive different first test signals and switch to conduct different first test signals to the circuit board to be tested 130. The first switch component 110 can include a plurality of first ports 111 and a plurality of second ports 112, and the plurality of first ports 111 of the first switch component 110 can be used to receive different first test signals respectively.

[0046] Exemplarily, the first test signal may include a first RF signal, a second RF signal and a first noise signal, and the first first port 1111 of the first switch component 110 may be used to receive the first RF signal, the second first port 1112 of the first switch component 110 may be used to receive the second RF signal, and the third first port 1113 of the first switch component 110 may be used to receive the first noise signal.

[0047] Further, the plurality of second ports 112 of the first switch component 110 are respectively connected to the plurality of different first ports 131 of the circuit board to be tested 130, so that the received first test signal can be conducted to the circuit board to be tested. The first switch component 110 can be used to switch and conduct the first port 111 of the first switch component 110 corresponding to the first test signal and the first port 131 of the circuit board to be tested 130 based on different first test signals. Therefore, even for different first test signals, different first test signals can be conducted to the circuit board to be tested 130 by switching the first switch component 110.

[0048] In some embodiments, the chip to be tested may be a related chip for wireless communication technology, such as a radio frequency chip. When the chip to be tested is a radio frequency chip, the first test signal may be a radio frequency signal. Therefore, in order to switch the transmission radio frequency signal, the first switch component 110 may include at least one radio frequency switch. For example, the first switch component 110 may be a multi-pole multi-throw radio frequency switch; for another example, the first switch component 110 may also be a switch circuit composed of a plurality of single-pole multi-throw radio frequency switches cascaded. For the specific structure of the first switch component 110, please refer to the introduction of the subsequent embodiments.

[0049] The second switch component 120 can be used to receive the first signal to be detected output by the circuit board to be tested 130, and switch to conduct different first signals to be detected to different second ports 122 of the second switch component 120. In some embodiments, the first signal to be detected can be output for detection through the second port 122 of the second switch component 120. For example, the second port 122 of the second switch component 120 outputs the first signal to be detected to the first receiving test module, so that the first signal to be detected is tested through the first receiving test module, and then the performance parameters of the chip to be tested are determined.

[0050] The second switch component 120 may include a plurality of first ports 121 and a plurality of second ports 122. The plurality of first ports 121 of the second switch component 120 are respectively connected to a plurality of different second ports 132 of the circuit board to be tested 130, and the plurality of second ports 122 of the second switch component 120 are respectively used to output different first signals to be detected.

[0051] Exemplarily, the second switch component 120 is used to switch and conduct the second port 132 of the circuit board to be tested 130 and the second port 122 of the second switch component 120 based on the first port 131 of the circuit board to be tested 130, wherein the second port 132 of the circuit board to be tested that is switched on is the second port 132 corresponding to the first port 131 of the circuit board to be tested 130. Thus, for different first test signals, different first signals to be detected can be generated after passing through the circuit board to be detected 130, and then by switching the second switch component 120, different first signals to be detected can be output through different second ports 122 of different second switch components 120.

[0052] In some embodiments, since the chip to be tested may be a related chip for wireless communication technology, such as a radio frequency chip, when the chip to be tested is a radio frequency chip, the first test signal may be a radio frequency signal, and the first signal to be detected may also be a radio frequency signal. Therefore, in order to switch the transmission radio frequency signal, the second switch component 120 may also include at least one radio frequency switch. For example, the second switch component 120 may be a multi-pole multi-throw radio frequency switch; for another example, the second switch component 120 may also be a switch circuit composed of a plurality of single-pole multi-throw radio frequency switches cascaded. For the specific structure of the second switch component 120, please refer to the introduction of the subsequent embodiments.

[0053] The chip testing system provided in the embodiment of the present application can directly switch on the first port of the first switch component corresponding to the first test signal and the first port of the circuit board to be tested through the first switch, and then switch on the second port of the circuit board to be tested corresponding to the first port of the circuit board to be tested and the second port of the second switch component through the second switch component, so as to transmit the first test signal to the second port of the second switch component through the circuit board to be tested. When testing various types of performance parameters of the chip to be tested, the first switch component and the second switch component can be directly switched on, thereby avoiding manual disconnection of the circuit, which not only improves the efficiency of testing various chip parameters, but also reduces the interference introduced by disconnecting the circuit, and improves the accuracy and reliability of the test.

[0054] Optional, see Figure 2 , Figure 2 The schematic diagram of the structure of a chip testing system provided by an embodiment of the present application is shown. The chip testing system 100 includes a circuit board to be tested 130 , a first RF switch 210 , a second RF switch 220 and a second switch assembly 120 .

[0055] The multiple first ports 121 of the second switch assembly 120 are respectively connected to multiple different second ports 132 of the circuit board to be tested 130 , which has been introduced in the above embodiments and will not be described again here.

[0056] In some embodiments, the first switch component may include a first RF switch 210 and a second RF switch 220. The first RF switch 210 may include a plurality of first ports 211 and a second port 212, and the second RF switch 220 may also include a first port 221 and a plurality of second ports 222. The plurality of first ports 211 of the first RF switch 210 may be respectively used to receive different first test signals, and the second port 212 of the first RF switch 210 is connected to the first port 221 of the second RF switch 220.

[0057] Furthermore, the plurality of second ports 222 of the second RF switch 220 may also be respectively connected to a plurality of different first ports 131 of the circuit board to be tested 130 .

[0058] For some embodiments, the first RF switch 210 and the second RF switch 220 may both be single-pole multi-throw switches, so that the first port 211 of the first RF switch 210 may be a multi-throw side, and the second port 212 of the first RF switch 210 may be a single-pole side; and the first port 221 of the second RF switch 220 may be a single-pole side, and the second port 222 of the second RF switch 220 may be a multi-throw side. Exemplarily, the single-pole multi-throw switch may be a single-pole six-throw switch; in another exemplary embodiment, the single-pole multi-throw switch may also be a single-pole ten-throw switch.

[0059] It should be noted that, depending on the power of the first test signal, if the power of the first test signal is relatively large, the first RF switch 210 and the second RF switch 220 may also use high-power RF switches, which is not specifically limited in the embodiment of the present application.

[0060] Optional, see Figure 3 , Figure 3 The schematic diagram of the structure of the chip test system provided by an embodiment of the present application is shown. The chip test system 100 includes a circuit board to be tested 130, a first RF switch 210, a second RF switch 220, a third RF switch 230, a fourth RF switch 240, a fifth RF switch 250 and a second switch component 120.

[0061] The multiple first ports 121 of the second switch assembly 120 are respectively connected to multiple different second ports 132 of the circuit board to be tested 130 , which has been introduced in the above embodiments and will not be described again here.

[0062] In some embodiments, the first switch assembly may further include a third RF switch 230, a fourth RF switch 240, and a fifth RF switch 250. The third RF switch 230 may include a first port 231 and a plurality of second ports 232; the fourth RF switch 240 may include a first port 241 and a plurality of second ports 242; and the fifth RF switch 250 may include a first port 251 and a plurality of second ports 252.

[0063] The first port 231 of the third RF switch 230, the first port 241 of the fourth RF switch 240, and the first port 251 of the fifth RF switch 250 are respectively connected to different second ports 222 of the second RF switch 220. The multiple second ports 232 of the third RF switch 230, the multiple second ports 242 of the fourth RF switch 240, and the multiple second ports 252 of the fifth RF switch 250 are respectively connected to different first ports 131 of the circuit board 130 to be tested.

[0064] Similar to the above-mentioned embodiment, the third RF switch 230, the fourth RF switch 240 and the fifth RF switch 250 can all be single-pole multi-throw switches, so that the first port 231 of the third RF switch 230 can be a single-pole side, and the multiple second ports 232 of the third RF switch 230 can be a multi-throw side; the first port 241 of the fourth RF switch 240 can be a single-pole side, and the multiple second ports 242 of the fourth RF switch 240 can be a multi-throw side; the first port 251 of the fifth RF switch 250 can be a single-pole side, and the multiple second ports 252 of the fifth RF switch 250 can be a multi-throw side. Exemplarily, the single-pole multi-throw switch can be a single-pole six-throw switch; in another exemplary manner, the single-pole multi-throw switch can also be a single-pole ten-throw switch.

[0065] Optional, see Figure 4 , Figure 4 The schematic diagram of the structure of a chip testing system provided by an embodiment of the present application is shown. The chip testing system 100 includes a circuit board to be tested 130 , a first switch component 110 , a sixth RF switch 310 and a seventh RF switch 320 .

[0066] Among them, the multiple first ports 111 of the first switch component 110 are respectively used to receive different first test signals, and the multiple second ports 112 of the first switch component 110 are respectively connected to multiple different first ports 131 of the circuit board 130 to be tested, which has been described in detail in the previous embodiment and will not be repeated here.

[0067] In some embodiments, the second switch assembly may include a sixth RF switch 310 and a seventh RF switch 320. The sixth RF switch 310 may include a plurality of first ports 311 and a second port 322; and the seventh RF switch 320 may also include a first port 321 and a plurality of second ports 322. The plurality of first ports 311 of the sixth RF switch 310 are respectively connected to a plurality of different second ports 132 of the circuit board to be tested 130, and the second port 312 of the sixth RF switch 310 is connected to the first port 321 of the seventh RF switch 320.

[0068] Furthermore, the plurality of second ports 322 of the seventh RF switch 320 are respectively used to output different first signals to be detected.

[0069] Similar to the above-mentioned embodiments, the sixth RF switch 310 and the sixth RF switch 320 can both be single-pole multi-throw switches, so that the first port 311 of the sixth RF switch 310 can be a multi-throw side, and the second port 312 of the sixth RF switch 310 can be a single-pole side; the first port 321 of the seventh RF switch 320 can be a single-pole side, and the second port 322 of the seventh RF switch 320 can be a multi-throw side. Exemplarily, the single-pole multi-throw switch can be a single-pole six-throw switch; in another exemplary embodiment, the single-pole multi-throw switch can also be a single-pole ten-throw switch.

[0070] See also Figure 5 , Figure 5 The schematic diagram of the structure of the chip test system provided by an embodiment of the present application is shown. The chip test system 100 includes a circuit board to be tested 130, a first RF switch 210, a second RF switch 220, a third RF switch 230, a fourth RF switch 240, a fifth RF switch 250, a sixth RF switch 310 and a seventh RF switch 320.

[0071] Among them, the multiple first ports 211 of the first RF switch 210 can be used to receive different first test signals respectively, and the second port 212 of the first RF switch 210 is connected to the first port 221 of the second RF switch 220. The first port 231 of the third RF switch 230, the first port 241 of the fourth RF switch 240, and the first port 251 of the fifth RF switch 250 are respectively connected to different second ports 222 of the second RF switch 220. The multiple second ports 232 of the third RF switch 230, the multiple second ports 242 of the fourth RF switch 240, and the multiple second ports 252 of the fifth RF switch 250 are respectively connected to different first ports 131 of the circuit board 130 to be tested.

[0072] The sixth RF switch 310 may include a plurality of first ports 311 and a second port 322; and the seventh RF switch 320 may also include a first port 321 and a plurality of second ports 322. The plurality of first ports 311 of the sixth RF switch 310 are respectively connected to a plurality of different second ports 132 of the circuit board to be tested 130, and the second port 312 of the sixth RF switch 310 is connected to the first port 321 of the seventh RF switch 320. The plurality of second ports 322 of the seventh RF switch 320 are respectively used to output different first signals to be detected.

[0073] That is to say, the first test signal received by the first port 211 of the first RF switch 210 can be transmitted to the first port 131 of the circuit board 130 to be tested through the combination of the first RF switch 210, the second RF switch 220, the third RF switch 230, the fourth RF switch 240 and the fifth RF switch 250.

[0074] It should be noted that which specific first port among the multiple first ports 131 of the test circuit board 130 needs to be transmitted can be determined according to the first test signal. Exemplarily, the correspondence between each first test signal and the second port 122 of the second switch component 120, the second port 132 of the circuit board 130 to be tested, the first port 131 of the circuit board 130 to be tested, and the first port 111 of the first switch component 110 can be predetermined. Therefore, after determining the first test signal that needs to be transmitted, the first port 211 of the first RF switch 210 and the first port 131 of the circuit board 130 to be tested corresponding to the first test signal that needs to be turned on can be determined. Then, the conduction of the first RF switch 210, the second RF switch 220, the third RF switch 230, the fourth RF switch 240, and the fifth RF switch 250 can be controlled, so as to realize the conduction of the first port 211 of the first RF switch 210 corresponding to the first test signal and the first port 131 of the circuit board 130 to be tested.

[0075] Similarly, after acquiring the first test signal, the circuit board to be tested 130 generates a first signal to be detected based on the chip to be tested carried thereon, and outputs the signal through the second port 132 of the circuit board to be tested 130. Specifically, which second port among the multiple second ports 132 of the circuit board to be tested 130 is used for output can be determined by which first port 131 the first test signal input to the circuit board to be tested 130 passes through. In some embodiments, the correspondence between each first port 131 and the second port 132 in the circuit board to be tested 130 can be predetermined, so that the second port 132 of the circuit board to be tested 130 can be determined based on the first port 131 of the circuit board to be tested 130.

[0076] Further, the sixth RF switch 310 and the seventh RF switch 320 can be switched so that the first signal to be detected outputted from the second port 132 of the circuit board 130 to be tested is outputted through the second port 322 of the seventh RF switch 320. The correspondence between different first test signals and the second port 322 of the seventh RF switch 320 can be predetermined, so that after the first test signal is determined, a specific second port can be determined from the multiple second ports 322 of the seventh RF switch 320.

[0077] It can be seen that the chip testing system provided in the embodiment of the present application does not require manual disconnection of the circuit for a variety of different first test signals, which not only improves the efficiency of testing various chip parameters, but also reduces the interference introduced by disconnecting the circuit, thereby improving the accuracy and reliability of the test.

[0078] Optional, see Figure 6 , Figure 6 The schematic diagram of the structure of a chip testing system provided by an embodiment of the present application is shown. The chip testing system 100 includes a circuit board to be tested 130 , a first switch component 110 and a second switch component 120 .

[0079] Among them, the multiple first ports 111 of the first switch component 110 are respectively used to receive different first test signals, the multiple second ports 112 of the first switch component 110 are respectively connected to the multiple different first ports 131 of the circuit board 130 to be tested, and the multiple first ports 121 of the second switch component 120 are respectively connected to the multiple different second ports 132 of the circuit board 130 to be tested, which have been introduced in the previous embodiments and will not be repeated here.

[0080] From the above introduction, it can be known that different first test signals are required to test the chip to be tested carried by the circuit board to be tested 130. Therefore, the chip testing system 100 may include a first signal generating module 140, which is used to generate different first test signals.

[0081] Furthermore, in order to detect the first signal to be detected, the chip testing system 100 may further include a first receiving test module 150, wherein the first receiving test module 150 is used to receive the first signal to be detected and detect the first signal to be detected.

[0082] Specifically, the first signal generating module 140 may include a plurality of output ports 141, and the plurality of output ports 141 of the first signal generating module 140 are respectively connected to a plurality of different first ports 111 of the first switch component 110. The first receiving test module 150 may include an input port 151, and the input port 151 of the first receiving test module 150 is connected to the second port 122 of the second switch component 120.

[0083] Exemplarily, the first signal generating module 140 may include a noise source, a signal source, etc., so that different radio frequency signals may be generated based on the noise source and the signal source, etc., as the first test signal. The first receiving test module 150 may include a spectrum analyzer or an oscilloscope, etc., so that the first signal to be detected may be detected by the spectrum analyzer or the oscilloscope. For details, please refer to the introduction of the subsequent embodiments.

[0084] Optionally, for some chips to be tested carried on the circuit board to be tested 130, it may be necessary to input a test signal from the second port 132 of the circuit board to be tested 130, and the test signal passes through the circuit board to be tested 130 and then outputs through the first port 131 of the circuit board to be tested 130. In other words, the chip to be tested may require a test signal with a transmission direction opposite to that of the first test signal. Therefore, in some embodiments, the second port 122 of the second switch component 120 can also be used to receive a second test signal, wherein the second port of the second switch component for receiving the second test signal is different from the plurality of second ports 122 for outputting different first signals to be detected.

[0085] The first port 111 of the first switch component 110 can also be used to output a second signal to be detected, wherein the first port 111 of the first switch component 110 used to output the second signal to be detected is different from the multiple first ports 111 used to receive different first test signals, and the second signal to be detected is a signal generated by the circuit board to be tested based on the second test signal.

[0086] That is to say, the second switch component 120 in the chip testing system 100 can also be used to switch on the second port 122 of the second switch component 120 corresponding to the second test signal and the second port 132 of the circuit board 130 to be tested based on the second test signal; the first switch component 110 can also be used to switch on the first port 131 of the circuit board to be tested and the first port 111 of the first switch component 110 based on the second port 131 of the circuit board 130 to be tested, wherein the first port 131 of the circuit board 130 to be tested that is switched on is the first port 131 corresponding to the second port 132 of the circuit board 130 to be tested.

[0087] Similar to the above-mentioned embodiments, the correspondence between the second test signal and the second port 122 of the second switch component 120, the second port 132 of the circuit board 130 to be tested, the first port 131 of the circuit board 130 to be tested and the first port 111 of the first switch component 110 can be predetermined, so that after the second test signal is determined, the first switch component 110 and the second switch component 120 can be controlled to switch on without manually disconnecting the circuit, thereby reducing interference caused by human intervention, improving the accuracy and reliability of detecting the performance parameters of the chip to be detected, and improving the detection performance.

[0088] Optionally, in order to generate the second test signal, the chip testing system 100 may include a second signal generating module 160, and the second signal generating module 160 is used to generate the second test signal.

[0089] Furthermore, in order to detect the second signal to be detected, the chip detection system 100 may further include a second receiving test module 170. The second receiving test module 170 is used to receive the second signal to be detected and detect the second signal to be detected.

[0090] Specifically, the second signal generating module 160 may include an output port 161, and the output port 161 of the second signal generating module 160 is connected to the second port 122 of the second switch component 120. The second receiving test module 170 may include an input port 171, and the input port 171 of the second receiving test module 170 is connected to the first port 111 of the first switch component 110.

[0091] Exemplarily, the first signal generating module 140 may include a noise source, a signal source, etc., so that different radio frequency signals may be generated based on the noise source and the signal source, etc., as the first test signal. The first receiving test module 150 may include a spectrum analyzer or an oscilloscope, etc., so that the first signal to be detected may be detected by the spectrum analyzer or the oscilloscope. For details, please refer to the introduction of the subsequent embodiments.

[0092] The embodiment of the present application connects the first signal generating module, the second signal generating module, the first receiving test module and the second receiving test module respectively through the first switch component and the second switch component. By switching the first switch component and the second switch component, it is possible to solve the problem that the chip to be tested may require a test signal with a transmission direction opposite to that of the first test signal for testing.

[0093] Optional, see Figure 7 , Figure 7The schematic diagram of the structure of a chip testing system provided by an embodiment of the present application is shown. The chip testing system 100 includes a circuit board to be tested 130 , a first switch component 110 and a second switch component 120 .

[0094] Among them, the multiple first ports 111 of the first switch component 110 are respectively used to receive different first test signals, the multiple second ports 112 of the first switch component 110 are respectively connected to the multiple different first ports 131 of the circuit board 130 to be tested, and the multiple first ports 121 of the second switch component 120 are respectively connected to the multiple different second ports 132 of the circuit board 130 to be tested, which have been introduced in the previous embodiments and will not be repeated here.

[0095] Optionally, the first signal generating module in the chip testing system 100 may include a first noise source 710 , a first signal source 720 , a filter component 730 , a second noise source 740 , a coupler 750 , an eighth RF switch 760 , and a ninth RF switch 770 .

[0096] Among them, the first noise source 710 may include an output port 711; the first signal source 720 may include an output port 721; the filtering component 730 may include multiple different first ports 731 and multiple different second ports 732; the second noise source 740 may include an output port 741; the coupler 750 may include a first port 753, a second port 751 and a third port 752; the eighth RF switch 760 may include a first port 761 and multiple second ports 762; the ninth RF switch 770 may include a first port 771 and multiple second ports 772.

[0097] exist Figure 7 In the chip test system shown, the output port 711 of the first noise source 710, the second port 772 of the ninth RF switch 770, and the first port 753 of the coupler 750 are respectively connected to a plurality of different first ports 111 of the first switch component 110. The first noise source 710 is used to generate a first noise signal, that is, the first noise signal can be used as a first test signal.

[0098] Furthermore, the output port 721 of the first signal source 720 is connected to the first port 761 of the eighth RF switch 760. The first signal source 720 is used to generate a first RF signal, that is, the first RF signal can be used as a first test signal.

[0099] The second ports 762 of the eighth RF switch 760 are respectively connected to the different first ports 731 of the filter component 730 , the first port 771 of the ninth RF switch 770 , and the third port 752 of the coupler 750 .

[0100] The multiple different second ports 732 of the filter component 730 are respectively connected to the multiple different first ports 771 of the ninth RF switch 770. The filter component 730 is used to generate multiple different filter signals based on the first RF signal, that is, the multiple different filter signals can also be used as multiple different first test signals.

[0101] The output port 741 of the second noise source 740 is connected to the second port 751 of the coupler 750. The second noise source 740 is used to generate a second noise signal, that is, the second noise signal can also be used as a first test signal.

[0102] The coupler 750 is used to couple the second noise signal and the first radio frequency signal to generate a second radio frequency signal. That is, the second radio frequency signal can also be used as the first test signal.

[0103] In the embodiment of the present application, the first port 753 of the coupler 750 can be used as the input port of the coupler, the second port 751 of the coupler can be used as the output port of the coupler 750, and the third port 752 of the coupler 750 can be used as the coupling port of the coupler.

[0104] Furthermore, the first receiving test module in the chip testing system 100 may include a first spectrum analyzer 780 , a first attenuator 790 , and a first DC block 7100 .

[0105] The first spectrum analyzer 780 may include an input port 781 ; the first attenuator 790 may include a first port 791 and a second port 792 ; and the first DC block 7100 may include a first port 7101 and a second port 7102 .

[0106] exist Figure 7 In the chip testing system 100 shown, the first port 791 of the first attenuator 790 is connected to the second port 122 of the second switch component 120, and the second port 792 of the first attenuator 790 is connected to the first port 7101 of the first DC block 7100. The second port 7102 of the first DC block 7100 is connected to the input port 781 of the first spectrum analyzer 780.

[0107] Optionally, the chip testing system 100 may further include a specified parameter testing module 7110. The specified parameter testing module 7110 includes a first port 7111 and a second port 7112. Figure 7 , the first port 7111 of the designated parameter test module 7110 is connected to the first port 111 of the first switch component 110 , and the second port 7112 of the designated parameter test module 7110 is connected to the second port 122 of the second switch component 120 .

[0108] The designated parameter test module 7110 is used to generate a designated parameter test signal, and is also used to receive and test a designated parameter to-be-detected signal, wherein the designated parameter to-be-detected signal is a signal generated by the circuit board to be tested based on the designated parameter test signal, and the designated parameter test signal is used to test the designated parameter performance of the circuit board to be tested. In other words, the designated parameter test signal can be regarded as a first test signal, and the designated parameter to-be-detected signal can be regarded as a first to-be-detected signal, so that the designated parameter test module 7110 can be regarded as a first signal generating module, and can also be regarded as a first receiving test module.

[0109] Optionally, the first port 7111 of the designated parameter test module 7110 can be used as both an input and an output, and similarly, the second port 7112 of the designated parameter test module 7110 can be used as both an input and an output. Thus, in some embodiments, the designated parameter test module 7110 can output a designated parameter test signal through the first port input 7111 of the parameter test module 7110, and receive a designated parameter to-be-detected signal through the second port 7112 of the parameter test module 7110. In other embodiments, the designated parameter test module 7110 can also output a designated parameter test signal through the second port input 7112 of the parameter test module 7110, and receive a designated parameter to-be-detected signal through the first port 7111 of the parameter test module 7110.

[0110] In some implementations, the specified parameter performance includes at least one of S parameter performance, stability performance, and out-of-band suppression performance. Thus, the specified parameter test module 7110 may be a vector network analyzer (VNA).

[0111] Optionally, the second signal generating module in the chip testing system 100 may include a second signal source 7120 . The second signal source 7120 may include an output port 7121 , and the output port 7121 of the second signal source 7120 is connected to the second port 122 of the second switch component 120 .

[0112] Furthermore, the second receiving test module in the chip testing system 100 may include a second spectrum analyzer 7130 , a second attenuator 7140 , and a second DC block 7150 .

[0113] The second spectrum analyzer 7130 may include an input port 7131 ; the second attenuator 7140 may include a first port 7141 and a second port 7142 ; and the second DC block 7150 may include a first port 7151 and a second port 7152 .

[0114] exist Figure 7In the chip testing system 100 shown, the first port 7151 of the second DC block 7150 is connected to the second port 7142 of the second attenuator 7140 , and the second port 7152 of the second DC block 7150 is connected to the first port 111 of the first switch component 110 ; the first port 7141 of the second attenuator 7140 is connected to the input terminal 7131 of the second spectrum analyzer 7130 .

[0115] Optional, see Figure 8 , Figure 8 The schematic diagram of the structure of the chip test system provided by an embodiment of the present application is shown. Among them, the chip test system 100 includes a circuit board to be tested 130, a circuit board to be tested 130, a first radio frequency switch 210, a second radio frequency switch 220, a third radio frequency switch 230, a fourth radio frequency switch 240, a fifth radio frequency switch 250, a sixth radio frequency switch 310, a seventh radio frequency switch 320, a first noise source 710, a first signal source 720, a filter component 730, a second noise source 740, a coupler 750, an eighth radio frequency switch 760, a ninth radio frequency switch 770, a first spectrum analyzer 780, a first attenuator 790, a first direct current block 7100, a specified parameter test module 7110, a second signal source 7120, a second spectrum analyzer 7130, a second attenuator 7140, and a second direct current block 7150. Among them, the ports included in the above-mentioned components and the connection relationship have been described in detail in the aforementioned embodiments, and will not be repeated here.

[0116] Optional, in Figure 8 In the chip test system 100 shown, the filter component 730 may specifically include a low-frequency bandpass filter 810, an intermediate frequency bandpass filter 820, and a high-frequency bandpass filter 830. The low-frequency bandpass filter 810 may include a first port 811 and a second port 812; the intermediate frequency bandpass filter 820 may include a first port 821 and a second port 822; and the high-frequency bandpass filter 830 may include a first port 831 and a second port 832.

[0117] Specifically, the first port 811 of the low-frequency bandpass filter 810, the first port 821 of the intermediate frequency bandpass filter 820, and the first port 831 of the high-frequency bandpass filter 830 are respectively connected to multiple different second ports 762 of the eighth RF switch 760, and the second port 812 of the low-frequency bandpass filter 810, the second port 822 of the intermediate frequency bandpass filter 820, and the second port 832 of the high-frequency bandpass filter 830 are respectively connected to multiple different first ports 771 of the ninth RF switch 770.

[0118] Among them, the low-frequency bandpass filter 810 can be used to filter the first RF signal to obtain a first filtered signal; the intermediate-frequency bandpass filter 820 can be used to filter the first RF signal to obtain a second filtered signal; and the high-frequency bandpass filter 830 is used to filter the first RF signal to obtain a third filtered signal. In other words, the first RF signal generated by the first signal source 720 can be directly used as a first test signal, or the first filtered signal can be generated by the low-frequency bandpass filter 810, thereby using the first filtered signal as a first test signal. The second filtered signal can also be generated by the intermediate-frequency bandpass filter 820, thereby using the second filtered signal as a first test signal. The third filtered signal can also be generated by the high-frequency bandpass filter 830, thereby using the third filtered signal as a first test signal.

[0119] Further, in Figure 8 In the chip testing system 100 shown, the output port 711 of the first noise source 710, the second port 772 of the ninth RF switch 770, the first port 753 of the coupler 750, the second port 7152 of the second DC block 7150, and the first port 7111 of the specified parameter testing module 7110 are respectively connected to the multiple first ports 211 of the first RF switch. The output port 7121 of the second signal source 7120, the first port 791 of the first attenuator 790, and the second port 7112 of the specified parameter testing module 7110 are respectively connected to the multiple second ports 322 of the seventh RF switch 320.

[0120] Exemplarily, the output port 711 of the first noise source 710 can be connected to the second first port 2112 of the first RF switch 210; the second port 7152 of the second DC block 7150 can be connected to the third first port 2113 of the first RF switch 210; the second port 772 of the ninth RF switch 770 can be connected to the fourth first port 2114 of the first RF switch 210; the first port 753 of the coupler 750 can be connected to the fifth first port 2115 of the first RF switch 210; the first port 7111 of the specified parameter test module 7110 can be connected to the sixth first port 2116 of the first RF switch 210. It should be noted that different components can also be connected to the first port 211 of other first RF switches 210, which can be flexibly adjusted as needed, and the embodiments of the present application are not limited thereto.

[0121] Exemplarily, the output port 7121 of the second signal source 7120 may be connected to the fourth second port 3224 of the seventh RF switch 320; the first port 791 of the first attenuator 790 may be connected to the fifth second port 3225 of the seventh RF switch 320; the second port 7112 of the designated parameter test module 7110 may be connected to the sixth second port 3226 of the seventh RF switch 320. It should be noted that different components may also be connected to the second port 322 of other seventh RF switches 320, which may be flexibly adjusted as needed, and the embodiments of the present application are not limited thereto.

[0122] The chip testing system provided in the embodiment of the present application can directly switch on the first port of the first switch component corresponding to the first test signal and the first port of the circuit board to be tested through the first switch, and then switch on the second port of the circuit board to be tested corresponding to the first port of the circuit board to be tested and the second port of the second switch component through the second switch component, so as to transmit the first test signal to the second port of the second switch component through the circuit board to be tested. When testing various types of performance parameters of the chip to be tested, the first switch component and the second switch component can be directly switched on, thereby avoiding manual disconnection of the circuit, which not only improves the efficiency of testing various parameters of the chip, but also reduces the interference introduced by disconnecting the circuit, thereby improving the accuracy and reliability of the test. At the same time, the embodiment of the present application can solve the problem that the chip to be tested may need a test signal opposite to the transmission direction of the first test signal by respectively setting the first signal generation module, the second signal generation module, the first receiving test module and the second receiving test module.

[0123] See also Fig. 9 , Fig. 9 A method flow chart of a chip testing method provided by an embodiment of the present application is shown, and the chip testing method can be applied to the chip testing system 100 shown in the aforementioned embodiments. Among them, the chip testing system 100 may include a circuit board to be tested 130, a first switch component 110, and a second switch component 120. The specific ports of the circuit board to be tested 130, the first switch component 110, and the second switch component 120 and the connection relationship between the ports have been introduced in detail in the aforementioned embodiments, and will not be repeated here. The chip testing method may specifically include steps S110 to S140.

[0124] Step S110: switching on a first port of the first switch component corresponding to a first test signal and a first port of the circuit board to be tested based on the first switch component.

[0125] Step S120: switching on the second port of the circuit board to be tested corresponding to the first port of the circuit board to be tested and the second port of the second switch component based on the second switch component.

[0126] In some embodiments, the first port of the first switch component can be used to receive different first test signals, and the different first test signals can pre-establish a correspondence between the first port and the second port of the first switch component, the first port and the second port of the circuit board to be tested, and the first port and the second port of the second switch component. In this case, the first test signal can be received by the first switch component and transmitted to the circuit board to be tested. After the chip to be tested on the circuit board to be tested obtains the first test signal, it generates a first signal to be tested, and transmits the first detection signal to the second switch component, and outputs it through the second port of the second switch component.

[0127] Thus, the first port of the first switch component corresponding to the first test signal can be switched on based on the first switch component and the first port of the circuit board to be tested, and the second port of the circuit board to be tested can be switched on based on the second switch component, wherein the second port of the circuit board to be tested that is switched on is the second port corresponding to the first port of the circuit board to be tested. Thus, when testing various types of performance parameters of the chip to be tested, the first switch component and the second switch component can be directly switched on, thereby avoiding manual disconnection of the circuit, which not only improves the efficiency of testing various chip parameters, but also reduces the interference introduced by disconnecting the circuit, thereby improving the accuracy and reliability of the test.

[0128] Step S130: switching on the second port of the second switch component corresponding to the second test signal and the second port of the circuit board to be tested based on the second switch component.

[0129] Step S140: switching on the first port of the circuit board to be tested corresponding to the second port of the circuit board to be tested and the first port of the first switch component based on the first switch component.

[0130] Optionally, for some chips to be tested carried on the circuit board to be tested, a test signal may need to be input from the second port of the circuit board to be tested, and the test signal passes through the circuit board to be tested and then output through the first port of the circuit board to be tested. In other words, the chip to be tested may need a test signal in the opposite direction of the transmission direction of the first test signal.

[0131] At this time, the second test signal can be received by the second switch component and transmitted to the circuit board to be detected. After the chip to be detected on the circuit board to be detected obtains the second test signal, a second signal to be detected is generated, and the second detection signal is transmitted to the first switch component and output through the first port of the first switch component.

[0132] Thus, the second port of the second switch component corresponding to the second test signal can be switched on with the second port of the circuit board to be tested based on the second switch component. The first port of the circuit board to be tested and the first port of the first switch component can be switched on based on the first switch component, wherein the first port of the circuit board to be tested that is switched on is the first port corresponding to the second port of the circuit board to be tested. At this time, the problem that the chip to be tested may require a test signal in the opposite direction of the transmission direction of the first test signal can be solved.

[0133] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip testing system, characterized in that: The chip testing system comprises a circuit board to be tested, a first switch component and a second switch component; The circuit board to be tested is used to carry at least one chip to be tested; The multiple first ports of the first switch component are respectively used to receive different first test signals, the multiple second ports of the first switch component are respectively connected to multiple different first ports of the circuit board to be tested, and the first switch component is used to switch and conduct the first port of the first switch component corresponding to the first test signal and the first port of the circuit board to be tested based on different first test signals; The multiple first ports of the second switch component are respectively connected to multiple different second ports of the circuit board to be tested, and the multiple second ports of the second switch component are respectively used to output different first signals to be detected. The second switch component is used to switch and connect the second port of the circuit board to be tested corresponding to the first port of the circuit board to be tested and the second port of the second switch component based on the first port of the circuit board to be tested, wherein the first signal to be detected is a signal generated by the circuit board to be tested based on the first test signal.

2. The chip testing system according to claim 1, characterized in that: The first switch assembly includes: a first radio frequency switch and a second radio frequency switch; The multiple first ports of the first RF switch are respectively used to receive different first test signals, and the second port of the first RF switch is connected to the first port of the second RF switch; The plurality of second ports of the second radio frequency switch are respectively connected to a plurality of different first ports of the circuit board to be tested.

3. The chip testing system according to claim 2, characterized in that: The first switch component further includes: a third RF switch, a fourth RF switch and a fifth RF switch; The first port of the third RF switch, the first port of the fourth RF switch, and the first port of the fifth RF switch are respectively connected to different second ports of the second RF switch, and multiple second ports of the third RF switch, multiple second ports of the fourth RF switch, and multiple second ports of the fifth RF switch are respectively connected to multiple different first ports of the circuit board to be tested.

4. The chip testing system according to claim 3, characterized in that: The first RF switch, the second RF switch, the third RF switch, the fourth RF switch, and the fifth RF switch are all single-pole multi-throw switches.

5. The chip testing system according to claim 1, characterized in that: The second switch component includes: a sixth radio frequency switch and a seventh radio frequency switch; The multiple first ports of the sixth RF switch are respectively connected to the multiple different second ports of the circuit board to be tested, and the second port of the sixth RF switch is connected to the first port of the seventh RF switch; The multiple second ports of the seventh radio frequency switch are respectively used to output different first signals to be detected.

6. The chip testing system according to claim 5, characterized in that: The sixth radio frequency switch and the seventh radio frequency switch are both single-pole multi-throw switches.

7. The chip testing system according to claim 4 or 6, characterized in that: The single-pole multi-throw radio frequency switch is a single-pole six-throw radio frequency switch.

8. The chip testing system according to claim 1, characterized in that: The chip testing system further includes: a first signal generating module and a first receiving testing module; The multiple output ports of the first signal generating module are respectively connected to the multiple different first ports of the first switch component, and the first signal generating module is used to generate different first test signals; The input port of the first receiving test module is connected to the second port of the second switch component, and the first receiving test module is used to receive the first signal to be detected.

9. The chip testing system according to claim 8, characterized in that: The first signal generating module includes: a first noise source, a first signal source, a filtering component, a second noise source, a coupler, an eighth RF switch and a ninth RF switch; The output port of the first noise source, the second port of the ninth RF switch, and the first port of the coupler are respectively connected to a plurality of different first ports of the first switch component; The first noise source is used to generate a first noise signal; The output port of the first signal source is connected to the first port of the eighth RF switch, and the first signal source is used to generate a first RF signal; The multiple second ports of the eighth RF switch are respectively connected to the multiple different first ports of the filter component, the first port of the ninth RF switch and the third port of the coupler; The multiple different second ports of the filter component are respectively connected to the multiple different first ports of the ninth RF switch, and the filter component is used to generate multiple different filter signals based on the first RF signal; The output port of the second noise source is connected to the second port of the coupler, and the second noise source is used to generate a second noise signal; The coupler is used to couple the second noise signal and the first radio frequency signal to generate a second radio frequency signal.

10. The chip testing system according to claim 9, characterized in that: The filtering component includes: a low-frequency band-pass filter, an intermediate-frequency band-pass filter and a high-frequency band-pass filter; The first port of the low-frequency band-pass filter, the first port of the intermediate-frequency band-pass filter, and the first port of the high-frequency band-pass filter are respectively connected to a plurality of different second ports of the eighth RF switch, and the second port of the low-frequency band-pass filter, the second port of the intermediate-frequency band-pass filter, and the second port of the high-frequency band-pass filter are respectively connected to a plurality of different first ports of the ninth RF switch; The low-frequency bandpass filter is used to filter the first radio frequency signal to obtain a first filtered signal; The intermediate frequency bandpass filter is used to filter the first radio frequency signal to obtain a second filtered signal; The high frequency bandpass filter is used to filter the first radio frequency signal to obtain a third filtered signal.

11. The chip testing system according to claim 8, characterized in that: The first receiving test module includes: a first spectrum analyzer, a first attenuator and a first DC block; The first port of the first attenuator is connected to the second port of the second switch component, and the second port of the first attenuator is connected to the first port of the first DC block; The second port of the first DC block is connected to the input port of the first spectrum analyzer.

12. The chip testing system according to claim 1, characterized in that: The chip testing system further includes: a specified parameter testing module; The first port of the specified parameter test module is connected to the first port of the first switch component, and the second port of the specified parameter test module is connected to the second port of the second switch component; The specified parameter test module is used to generate a specified parameter test signal, and is also used to receive and test a specified parameter to-be-detected signal, wherein the specified parameter to-be-detected signal is a signal generated by the circuit board to be tested based on the specified parameter test signal, and the specified parameter test signal is used to test the specified parameter performance of the circuit board to be tested.

13. The chip testing system according to claim 12, characterized in that: The specified parameter performance includes at least one of S parameter performance, stability performance and out-of-band suppression performance.

14. The chip testing system according to claim 1, characterized in that: The second port of the second switch component is also used to receive a second test signal, wherein the second port of the second switch component used to receive the second test signal is different from the plurality of second ports used to output different first signals to be detected; The first port of the first switch component is also used to output a second signal to be detected, wherein the first port of the first switch component used to output the second signal to be detected is different from a plurality of first ports used to receive different first test signals, and the second signal to be detected is a signal generated by the circuit board to be tested based on the second test signal; The second switch component is further used to switch on the second port of the second switch component corresponding to the second test signal and the second port of the circuit board to be tested based on the second test signal; The first switch component is further used for switching on the first port of the circuit board to be tested and connecting the first port of the circuit board to be tested corresponding to the second port of the circuit board to be tested and the first port of the first switch component based on the second port of the circuit board to be tested.

15. The chip testing system according to claim 14, characterized in that: The chip testing system further includes: a second signal generating module and a second receiving testing module; The output port of the second signal generating module is connected to the second port of the second switch component, and the second signal generating module is used to generate a second test signal; The input port of the second receiving test module is connected to the first port of the first switch component, and the second receiving test module is used to receive the second signal to be detected.

16. The chip testing system according to claim 15, characterized in that: The second signal generating module comprises a second signal source, and the second receiving test module comprises a second spectrum analyzer, a second attenuator and a second DC block; The output port of the second signal source is connected to the second port of the second switch component; The first port of the second DC block is connected to the second port of the second attenuator, and the second port of the second DC block is connected to the first port of the first switch component; The first port of the second attenuator is connected to the input end of the second spectrum analyzer.

17. A chip testing method, characterized in that: Applied to a chip testing system, the chip testing system includes a circuit board to be tested, a first switch component and a second switch component, and the method includes: Switching on the first port of the first switch component and the first port of the circuit board to be tested corresponding to the first test signal based on the first switch component; Based on the switching of the second switch component, the second port of the circuit board to be tested corresponding to the first port of the circuit board to be tested and the second port of the second switch component are connected.

18. The method according to claim 17, characterized in that The method further comprises: Switching on the second port of the second switch component and the second port of the circuit board to be tested corresponding to the second test signal based on the second switch component; Based on the switching of the first switch component, the first port of the circuit board to be tested corresponding to the second port of the circuit board to be tested and the first port of the first switch component are connected.

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