A mask plate for etching a rectangular array dot matrix and a method for preparing an array dot matrix pattern using the same

Abstract

This invention discloses a mask for etching a rectangular array of dots and a method for fabricating array dot matrix patterns using the mask. This invention is the first to propose a mask and method for dry etching of rectangular array dot matrix patterns; it avoids the use of photoresist or polar solvents, improving the compatibility of MEMS processes and enabling the application of more high-performance novel thin films in microelectronic devices; the array patterns fabricated using this layout etching method are compatible with any MEMS manufacturing plant, and the alignment marks between the substrate and the mask are compatible with the first layer circuit wiring process, saving manufacturing costs.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, specifically relating to a mask for etching a rectangular array of dots and a method for preparing an array of dots using the mask. Background Technology

[0002] Calcium etching is a crucial process in semiconductor device and integrated circuit manufacturing, serving as a vital method for patterning integrated circuit devices. Typically, etching follows photolithography, transferring the device structure pattern created by photolithography onto a lower substrate. Simply put, photolithography first reacts the photoresist under light or laser exposure, then immerses it in a developing solution to reveal the pattern to be removed. Next, etching removes the areas of the pattern not masked by photoresist, and finally, the photoresist is removed. Etching includes wet etching and dry etching. Wet etching uses various etching solutions to remove the pattern protected by the photoresist through immersion; while dry etching utilizes specialized etching techniques, including reactive ion etching (RIE), inductively coupled plasma (ICP), and ion beam etching (IBE).

[0003] The etching methods described above are commonly used strategies in semiconductor device and integrated circuit manufacturing. However, with the continuous emergence of high-performance new materials, new challenges are constantly being posed to MEMS manufacturing processes. For example, the physicochemical properties of new materials often cannot be manufactured using existing MEMS technologies (e.g., some materials are easily corroded by photoresists or polar solvents), leading to process incompatibility and thus limiting the use of new materials in microelectronic chips. For example, halide perovskite materials, which have attracted global attention in recent years due to their suitable band gap, high carrier mobility, high absorption coefficient, low exciton binding energy, and long carrier lifetime, have become next-generation optoelectronic functional materials with structures such as quantum dots and nanowires. They have shown excellent performance in light-emitting diodes, optical sensors, and memristors, but they are easily corroded by polar solutions (water, ethanol, acetone, photoresist, etc.). Another example is MnBi₂Te₄, an antiferromagnetic topological insulator, which possesses exotic states such as quantum anomalous Hall insulator, axion insulator, and Weyl half-metal. It is attractive not only in basic research but also has great potential in practical applications. However, this functional material is also easily corroded by polar solvents. With the development of technology, the number and types of these new materials are becoming increasingly diverse. To avoid contact with polar solvents, photolithography and wet etching methods must be ruled out, so only dry etching methods are possible. However, a mask is needed to pattern the material by masking it.

[0004] Typically, a perforated photomask is used where the portion to be patterned is hidden / protected, while the exposed portion is the part to be removed. A key characteristic is that the non-perforated portion of the photomask must have a continuous pattern; that is, the pattern of the hidden / protected portion must be continuous. Conversely, if the pattern of the perforated portion is continuous, but the pattern of the hidden / protected portion is discontinuous, the photomask itself does not exist for this pattern design. Figure 1 As shown. Therefore, in dry etching, when encountering array-type pattern etching, it is impossible to directly etch the pattern using a mask. Summary of the Invention

[0005] The purpose of this invention is to provide a mask for etching a rectangular array of point matrices, and the second objective of this invention is to provide a method for etching a rectangular array of point matrices using the mask.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0007] A mask for etching a rectangular array of dots, wherein the rectangular array of dots has N*M dots, the dot matrix is ​​a square of size a*b, the column resolution is c, and the row resolution is d; the mask includes a first layer, a second layer, and a third layer.

[0008] The first layer layout is used to fabricate the lower-layer circuitry for various applications of alignment markers and functional thin films, including:

[0009] 1) The thin film and circuit area located at the center of the layout and the blank area located at the periphery of the layout, wherein the blank area is the layout drawing area for other leads and pads of the circuit; the thin film and circuit area is a rectangle centered at the center of the layout (0,0), with a side length of N*c and a width of M*d;

[0010] 2) First etching alignment marks are provided at the four outer corners of the thin film and circuit area;

[0011] 3) First alignment marks are set at the four corners of the blank area of ​​the first layer layout for alignment between the mask and the substrate;

[0012] The second layer pattern is used to fabricate an etching mask, including:

[0013] 4) The second cutout area corresponding to the thin film and circuit area of ​​the first layer layout, and the second mask area corresponding to the blank area of ​​the first layer layout. The second cutout area is an etching mask area with a grid stripe structure. Each stripe is a rectangle with a length of N*c and a width of b. There are a total of M stripes. The center of the rectangle formed by the M stripes is the layout center (0, 0).

[0014] 5) Second etching alignment marks are set at the four corners of the second cutout area for positional alignment between the mask etching area and the substrate, and are consistent with the first etching alignment mark of the first layer layout;

[0015] 6) The second cutout area is provided with a second alignment mark corresponding to the first alignment mark, which is used to align the contact position between the mask and the substrate;

[0016] The third layer pattern, used to fabricate an etching mask, includes:

[0017] 7) A third cutout area corresponding to the thin film and circuit area of ​​the first layer layout, and a third mask area corresponding to the blank area of ​​the first layer layout; the third cutout area is an etching mask area, which has a grid stripe structure and is set perpendicular to the grid stripe structure of the etching mask area of ​​the second layer layout. Each stripe is a rectangle with a length of M*d and a width of a, and there are N stripes in total. The center of the rectangle formed by the N stripes is the layout center (0, 0).

[0018] 8) The four corners of the third cutout area are provided with third etching alignment marks. The third etching alignment marks are used for positional alignment between the mask etching area and the substrate, and are consistent with the first etching alignment marks of the first layer layout.

[0019] 9) The mask area of ​​the third layer layout is provided with a third alignment mark: used for aligning the contact position between the mask and the substrate, corresponding to the first alignment mark of the first layer layout.

[0020] As a further preferred embodiment of the present invention, the center positions of the first, second, and third etched alignment marks are distanced from the center position (0, 0) of the layout by c, where c > (N). 2 c 2 +M 2 d 2 ) 1 / 2 / 2, and the first, second, and third etch alignment marker layer structures range from a hundred-micrometer-level cross shape to a micrometer-level cross shape; the first, second, and third alignment markers are cross-shaped structures and are designed with multi-level precision, with the cross shape size ranging from a thousand-micrometer-level to a micrometer-level; the first, second, and third etch alignment markers and the next level of the first, second, and third alignment markers are all set in the blank positions at the four corners of the previous level; the layer of the first, second, and third alignment markers is determined according to the precision of the etch pattern. If the pattern precision is at the hundred-micrometer level, then the alignment marker cross shape between the mask and the substrate is drawn from a thousand-micrometer-level to a ten-micrometer-level. The first level cross shape of this pattern is at the thousand-micrometer level (millimeter level), and the position between the mask and the substrate can be determined by the naked eye for the first time; the second level is at the hundred-micrometer level, and can be determined by an optical microscope; the third level is at the ten-micrometer level; the fourth level is at the several-micrometer level; and so on, according to the increasing precision level, the cross shape of each level is located in the blank positions at the four corners of the previous level cross shape.

[0021] The present invention also discloses a method for etching a rectangular array of point matrix patterns using the aforementioned mask, comprising the following steps:

[0022] S1: First, utilize the first layer of the map:

[0023] S11: Fabricate the circuitry and various patterned alignment marks of the lower layer of the functional thin-film array region on the substrate;

[0024] S12: After the lower layer circuit and alignment mark patterning of the array points are completed, a functional thin film is deposited on the upper layer of the circuit. The functional thin film is deposited by thermal evaporation or spin coating.

[0025] S2: Use the second layer pattern to create a mask for etching:

[0026] S21: The mask material can be a thin metal plate such as stainless steel, or a silicon-based wafer or a ceramic thin film material such as silicon nitride and silicon dioxide; the red area in the layout is the removal area of ​​the mask, that is, the cutout area, and the white area is the retention area, that is, the mask area.

[0027] S22: Mask and substrate alignment: For the initial contact alignment, the mask and substrate can be visually judged based on the thousand-micron-level cross-shaped alignment marks at the four corners of the mask and substrate. By adjusting the relative positions of the mask and substrate, the mask and substrate make their first contact. Next, the position of the mask and substrate is further adjusted using a substrate transfer platform. The alignment between the mask and substrate is coarsely adjusted based on the hundred-micron-level cross-shaped alignment marks at the four corners of the mask and substrate. The alignment between the mask and substrate is then finely adjusted again using the substrate transfer platform based on the ten-micron-level and micron-level cross-shaped alignment marks at the four corners of the mask and substrate.

[0028] S23: Etching position alignment confirmation: After the mask and substrate are aligned, use the substrate transfer platform to observe whether the alignment marks at the four corners of the functional thin film and the circuit area are aligned at each level. If they are inconsistent, the positions of the mask and substrate can be further fine-tuned as needed.

[0029] S24: After alignment is completed, the mask plate and the substrate are fixed by pressure spring and / or resin glue;

[0030] S25: Place the fixed mask and substrate together into the etching machine for the first etching;

[0031] S3: After the first etching is completed, remove the mask of the second layer pattern; use the mask of the third layer pattern to perform alignment etching between the mask and the substrate again;

[0032] S4: Repeat S2 to S3 until the array point matrix pattern is etched.

[0033] As a further preferred embodiment of the present invention, in S11, the circuit is a metal layer, and the first layer pattern is used as a photolithography pattern to complete the patterning process: photolithography—development—deposition of conductive metal layer—lifting or deposition of conductive metal layer—photolithography—development—etching; or, the first layer pattern can be made into a mask, attached to the surface of the substrate, and the thin film of the circuit and the alignment mark can be made using physical vapor deposition process.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. This invention is the first to propose a mask and method for dry etching of rectangular array matrix array points.

[0036] 2. This invention avoids the use of photoresist or polar solvents, improves the inclusiveness of MEMS processes, and enables more high-performance new thin films to be applied in microelectronic devices.

[0037] 3. The array pattern made using the pattern etching method of this invention can be compatible with any MEMS manufacturing plant. The alignment marks of the substrate and the mask can be compatible with the first layer circuit wiring process, saving manufacturing costs. Attached Figure Description

[0038] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram illustrating a situation where existing photomasks cannot etch array-type patterns;

[0040] Figure 2 This is a rectangular dot matrix pattern completed using the present invention;

[0041] Figure 3 It is the first layer of layout design scheme and description;

[0042] Figure 4 It is the design scheme and explanation for the second layer of the layout;

[0043] Figure 5 It is the design scheme and explanation of the third layer layout;

[0044] Figure 6 This is a schematic diagram of the etching process of the rectangular array of point matrices according to the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described in detail below. However, the following embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0046] Example 1

[0047] This embodiment provides a mask for etching a rectangular array of point matrices, wherein the rectangular array of point matrices is as follows: Figure 2 The array shown has N*M points, the size of the array is an a*b square, the column resolution (the distance between the centers of adjacent vertical arrays) is c, and the row resolution (the distance between the centers of adjacent horizontal arrays) is d.

[0048] The photomask includes a first layer layout, a second layer layout, and a third layer layout:

[0049] The first layer of the layout is used to fabricate the lower-layer circuitry for various applications of alignment markers and functional thin films, such as... Figure 3 Shown, including:

[0050] 1) Thin film and circuit regions located at the center of the layout ( Figure 3 The central purple area Figure 3 The top left area shows the layout of the thin film and the blank area surrounding the layout. The blank area is the layout drawing area for other circuit leads and pads. The thin film and circuit area (purple area) is a rectangle centered at the layout center (0, 0), with a side length of N*c (N is the number of rectangular dot arrays, c is the resolution of the rectangular dot array) and a width of M*d (M is the number of rectangular dot array rows, d is the resolution of the rectangular dot array rows). The circuit layout design of the thin film layer and the circuit leads outside the thin film layer (purple area) are determined based on the dot array and device structure of the thin film. This layout does not provide a specific design scheme. This layout only needs to draw the functional thin film and the circuit area (purple area) of the thin film layer.

[0051] 2) First etching alignment markers 1 are set at the four outer corners of the thin film and circuit area (purple area). The distance between the center position of the first etching alignment marker 1 and the center position of the layout (center of the purple area) (0, 0) is c, where c > (N). 2 c 2 +M 2 d 2 ) 1 / 2 / 2. The first etching alignment marker layer structure ranges from a hundred-micrometer-level cross shape to a micrometer-level cross shape;

[0052] 3) Set the first alignment mark 2 at the four corners of the blank area of ​​the first layer map. Figure 3(Right figure) is used for alignment between the mask and the substrate. The alignment mark has a cross-shaped structure and a multi-level precision design. The size of the cross ranges from the thousand-micrometer level to the micrometer level.

[0053] The second layer pattern (mask) is used to fabricate the etching mask, such as... Figure 4 Shown, including:

[0054] 4) The second cutout region 3 corresponding to the thin film and circuit areas of the first layer layout, and the second mask region 4 corresponding to the blank areas of the first layer layout, such as... Figure 4 The red area shown is the cutout area, and the white area is the mask area; the second cutout area 3 is the etching mask area, which has a grid-like stripe structure as shown. Figure 4 As shown on the left, each stripe is a rectangle with a length of N*c (N is the number of matrix columns, c is the matrix column resolution) and a width of b (array point width). There are a total of M stripes, and the center of the rectangle formed by the M stripes is the center of the layout (0, 0).

[0055] 5) The second etching alignment markers 5 of the etching array are set at the four corners of the etching mask area. Figure 4 As shown in the lower middle section, it is used for positional alignment between the etched area of ​​the mask and the substrate, and is consistent with the first etch alignment mark 1 of the first layer layout;

[0056] 6) The second hollow area 3 is provided with a second alignment mark 6 corresponding to the first alignment mark 2. Figure 4 (As shown on the right), used for aligning the contact position between the mask and the substrate;

[0057] The third layer pattern (mask) is used to fabricate the etching mask, such as... Figure 5 Shown, including:

[0058] 7) The third cutout region 7 corresponding to the thin film and circuit areas of the first layer layout, and the third mask region 8 corresponding to the blank areas of the first layer layout, such as... Figure 5 As shown in the upper middle section, the red area is the cutout area, and the white area is the mask area; the third cutout area 7 is the etching mask area, which has a grid-like stripe structure (e.g., Figure 5 As shown on the left), and is set perpendicular to the grid stripe structure of the second layer etch mask area. Each stripe has a length of M*d (M is the number of matrix rows and is the matrix row resolution), and a width of a rectangle (the length of the array point). There are N stripes in total, and the center of the rectangle formed by the N stripes is the center of the layout (0, 0).

[0059] 8) The third etching alignment marks 9 of the etching array are set at the four corners of the third hollow area 7, as shown in the figure. Figure 5 As shown in the lower middle section, the third etching alignment mark 9 is used for positional alignment between the etched area of ​​the mask and the substrate, and is consistent with the first etching alignment mark 1 of the first layer layout.

[0060] 9) A third alignment marker 10 is set at each of the four corners of the mask area of ​​the third layer layout. Figure 5 (Right): The third alignment mark 10 is used for the alignment of the contact position between the mask and the substrate, and corresponds to the first alignment mark 2 of the first layer layout.

[0061] In this embodiment, the center positions of the first, second, and third etch alignment marks are c' away from the center position (0, 0) of the layout, where c > (N). 2 c 2 +M 2 d 2 ) 1 / 2 / 2, and the first, second, and third etched alignment marker layer structures range from a hundred-micron-level cross shape to a micron-level cross shape; the first, second, and third alignment markers have a cross-shaped structure and are designed with multi-level precision, with the cross shape size ranging from a thousand-micron-level to a micron-level; the first, second, and third etched alignment markers and the next level of the first, second, and third alignment markers are all set in the blank positions at the four corners of the previous level.

[0062] The first, second, and third alignment layers are determined based on the precision of the etching pattern. If the pattern precision is at the hundred-micrometer level, the alignment crosshairs between the mask and the substrate are drawn at the thousand-micrometer level to the ten-micrometer level. The first-level crosshair is at the thousand-micrometer level (millimeter level) and can be visually determined for the first time between the mask and the substrate; the second level is at the hundred-micrometer level and can be determined using an optical microscope; the third level is at the ten-micrometer level; the fourth level is at the several-micrometer level; and so on, according to the increasing precision of the layers. Each level's crosshair is located in the previous layer and in the blank positions at the four corners of the crosshair.

[0063] When using the first, second, third, and fourth corner alignment markers: First, place the mask on the substrate surface and determine the position visually based on the first-level thousand-micrometer cross shape; second, use a substrate transfer stage to coarsely adjust the position between the mask and the substrate based on the second-level hundred-micrometer cross shape; then, use a substrate transfer stage to finely adjust the position between the mask and the substrate based on the third-level ten-micrometer and fourth-level several-micrometer cross shape structures.

[0064] Example 2

[0065] This embodiment provides a method for etching a square array of dots using a mask according to the present invention, including the following steps:

[0066] S1: First, utilize the first layer of the map:

[0067] S11: Fabricate the circuitry beneath the functional thin-film array region on the substrate, and also fabricate the patterned alignment markers in this step. Generally, the circuitry is a metal layer, and its fabrication process, along with that of the patterned alignment markers, is not constrained by photoresist or polar solvent etching. Therefore, general MEMS processes can be used, using the first layer pattern as the photolithography pattern to complete the patterning process: photolithography – development – ​​deposition of conductive metal layer – lift-off or deposition of conductive metal layer – photolithography – development – ​​etching (wet / dry etching); alternatively, the first layer pattern can be fabricated as a mask, bonded to the substrate surface, and physical vapor deposition processes (electron beam evaporation, thermal evaporation, magnetron sputtering) can be used to complete the thin-film fabrication of the circuitry and alignment markers.

[0068] S11: After the lower layer circuit and alignment mark patterning of the array points are completed, a functional thin film is deposited on the upper layer of the circuit. The functional thin film can be deposited by thermal evaporation, spin coating, or other processes. The specific method is set according to the specific functional thin film fabrication situation, and will not be described in detail here.

[0069] S2: Use the second layer pattern to create a mask for etching:

[0070] S21: The mask material can be a thin metal sheet such as stainless steel, or a silicon-based wafer or a ceramic thin film material such as silicon nitride and silicon dioxide. In the layout, the red area is the area to be removed (cut out), and the white area is the area to be retained (mask area).

[0071] S22: Mask and substrate alignment: For the initial contact alignment, the mask and substrate can be visually judged based on the thousand-micron-level cross-shaped alignment marks at the four corners of the mask and substrate. By adjusting the relative positions of the mask and substrate, the mask and substrate make their first contact. Next, the position of the mask and substrate is further adjusted using a substrate transfer platform. The alignment between the mask and substrate is coarsely adjusted based on the hundred-micron-level cross-shaped alignment marks at the four corners of the mask and substrate. The alignment between the mask and substrate is then finely adjusted again using the substrate transfer platform based on the ten-micron-level and micron-level cross-shaped alignment marks at the four corners of the mask and substrate.

[0072] S23: Etching position alignment confirmation: After the mask and substrate are aligned, use the substrate transfer platform to observe whether the alignment marks at the four corners of the functional thin film and the circuit area are aligned at each level. If they are inconsistent, the positions of the mask and substrate can be further fine-tuned as needed.

[0073] S24: After alignment is completed, the mask and substrate are fixed with pressure springs and / or resin glue; the resin glue acts as a buffer to prevent vibration and misalignment between the mask and the substrate; the pressure spring acts as a fixation to prevent large-scale misalignment during the transfer of the mask and substrate to the etching machine.

[0074] S25: Place the fixed mask and substrate together into the etching machine for the first etching; the specific equipment, etching parameters and other details used in the etching process are related to the physicochemical properties of the etched film, and each step of the process needs to be adjusted according to the specific situation. This instruction does not provide specific details.

[0075] S3: After the first etching is completed, remove the mask of the second layer pattern; use the mask of the third layer pattern to perform alignment etching between the mask and the substrate again;

[0076] S4: Repeat S2 to S3 until the square array of dots is etched.

[0077] The above process can be found in, for example... Figure 6 As shown.

[0078] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be considered as equivalent replacement methods and are included in the scope of protection of the present invention.

Claims

1. A mask for etching a rectangular array of point matrices, characterized in that, The rectangular array point matrix has N*M array points, the array size is a*b square, the column resolution is c, and the row resolution is d. The mask includes a first layer layout, a second layer layout, and a third layer layout; The first layer layout is used to fabricate the lower-layer circuitry for various applications of alignment markers and functional thin films, including: 1) The thin film and circuit area located at the center of the layout and the blank area located at the periphery of the layout, wherein the blank area is the layout drawing area for other leads and pads of the circuit; the thin film and circuit area is a rectangle centered at the center of the layout (0,0), with a side length of N*c and a width of M*d; 2) First etching alignment marks are provided at the four outer corners of the thin film and circuit area; 3) First alignment marks are set at the four corners of the blank area of ​​the first layer layout for alignment between the mask and the substrate; the second layer layout is used to fabricate the etching mask, including: 4) A second cutout area corresponding to the thin film and circuit area of ​​the first layer layout, and a second mask area corresponding to the blank area of ​​the first layer layout. The second cutout area is an etching mask area with a grid stripe structure. Each stripe is a rectangle with a length of N*c and a width of b. There are a total of M stripes. The center of the rectangle formed by the M stripes is the layout center (0, 0). 5) Second etching alignment marks are set at the four corners of the second cutout area for positional alignment between the mask etching area and the substrate, and are consistent with the first etching alignment mark of the first layer layout; 6) The second cutout area is provided with a second alignment mark corresponding to the first alignment mark, which is used to align the contact position between the mask and the substrate; The third layer pattern, used to fabricate an etching mask, includes: 7) A third cutout area corresponding to the thin film and circuit area of ​​the first layer layout, and a third mask area corresponding to the blank area of ​​the first layer layout; the third cutout area is an etching mask area, which has a grid-like stripe structure and is set perpendicular to the grid-like stripe structure of the etching mask area of ​​the second layer layout. Each stripe is a rectangle with a length of M*d and a width of a, and there are N stripes in total. The center of the rectangle formed by the N stripes is the layout center (0, 0). 8) The four corners of the third cutout area are provided with third etching alignment marks. The third etching alignment marks are used for positional alignment between the mask etching area and the substrate, and are consistent with the first etching alignment marks of the first layer layout. 9) The mask area of ​​the third layer layout is provided with a third alignment mark: used for aligning the contact position between the mask and the substrate, corresponding to the first alignment mark of the first layer layout.

2. The mask for etching a rectangular array of dots according to claim 1, characterized in that, The center positions of the first, second, and third etch markers are c' apart from the center position (0, 0) of the layout, where c > (N). 2 c 2 +M 2 d 2 ) 1 / 2 / 2, and the first, second, and third etched alignment marker layer structures range from a hundred-micron-level cross shape to a micron-level cross shape; the first, second, and third alignment markers have a cross-shaped structure and are designed with multi-level precision, with the cross shape size ranging from a thousand-micron-level to a micron-level; the first, second, and third etched alignment markers and the next level of the first, second, and third alignment markers are all set in the blank positions at the four corners of the previous level.

3. The method for etching a rectangular array of point matrix patterns using a mask as described in claim 1 or 2, characterized in that, Includes the following steps: S1: First, utilize the first layer of the map: S11: Fabricate the circuitry and various patterned alignment marks of the lower layer of the functional thin-film array region on the substrate; S12: After the lower layer circuit and alignment mark patterning of the array points are completed, a functional thin film is deposited on the upper layer of the circuit. The functional thin film is deposited by thermal evaporation or spin coating. S2: Use the second layer pattern to create a mask for etching: S21: The mask material is one of the following: metal sheet, silicon wafer, and ceramic thin film material; the red area in the layout is the removal area of ​​the mask, that is, the cutout area, and the white area is the retention area, that is, the mask area. S22: Mask and substrate alignment: For the initial contact alignment, the mask and substrate can be visually judged based on the thousand-micron-level cross-shaped alignment marks at the four corners of the mask and substrate. By adjusting the relative positions of the mask and substrate, the mask and substrate make their first contact. Next, the position of the mask and substrate is further adjusted using a substrate transfer platform. The alignment between the mask and substrate is coarsely adjusted based on the hundred-micron-level cross-shaped alignment marks at the four corners of the mask and substrate. The alignment between the mask and substrate is then finely adjusted again using the substrate transfer platform based on the ten-micron-level and micron-level cross-shaped alignment marks at the four corners of the mask and substrate. S23: Etching position alignment confirmation: After the mask and substrate are aligned, use the substrate transfer platform to observe whether the alignment marks at the four corners of the functional thin film and the circuit area are aligned at each level. If they are not aligned, further fine-tune the position of the mask and substrate as needed. S24: After alignment is completed, the mask plate and the substrate are fixed by pressure spring and / or resin glue; S25: Place the fixed mask and substrate together into the etching machine for the first etching; S3: After the first etching is completed, remove the mask of the second layer pattern; use the mask of the third layer pattern to perform alignment etching between the mask and the substrate again; S4: Repeat S2 to S3 until the array point matrix pattern is etched.

4. The method for etching a rectangular array of point matrices according to claim 3, characterized in that, In step S21, the metal sheet is stainless steel; the ceramic thin film material is one of silicon nitride thin film material and silicon dioxide thin film material.

5. The method for etching a rectangular array of point matrices according to claim 3, characterized in that, In S11, the circuit is a metal layer. The first layer pattern is used as a photolithography pattern to complete the patterning process: photolithography - development - deposition of conductive metal layer - stripping or deposition of conductive metal layer - photolithography - development - etching; or, the first layer pattern can be made into a mask, attached to the substrate surface, and the circuit and alignment thin film can be made using physical vapor deposition process.

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