Programmable channel multiplexing signal detection structure

Abstract

The invention is suitable for the technical field of chips, and provides a programmable channel multiplexing signal detection structure which comprises an input signal selector, a programmable gain amplifier, an output signal selector, a signal detection module and a control logic module. The input signal selector gates one group of external input signals and transmits the input signals to the programmable gain amplifier, and the amplifier processes the input signals and then sends the processed signals into the signal detection module for signal processing and use. A user can control the on-off selection of an input channel and the gain coefficient of the programmable gain amplifier in real time by himself / herself, the practicability is high, and the signal detection module can be an analog-to-digital converter, a signal comparator and other signal processing devices. And the control logic module is used for obtaining the working state of the signal detection module to automatically control the input signal selector, so that the complexity of software control can be effectively reduced in some applications with shortage of software resources, and the operation efficiency of channel multiplexing is improved.

Description

Technical Field

[0001] The invention belongs to the field of chip technology, and in particular relates to a signal detection structure for programmable channel multiplexing. Background Art

[0002] As more and more dedicated microcontroller chips emerge, the integration of special functional circuits in MCU is increasing. At present, motor control dedicated microcontrollers usually integrate various analog signal detection modules to perform analog signal to digital signal processing required in motor control. When integrating operational amplifiers inside the chip, it is necessary to consider the number of integration, input channels, output channels and other connection methods. Too many operational amplifiers and inappropriate internal analog circuit connection methods will directly increase the production cost of the microcontroller and the overall chip size, and reduce the processing efficiency of analog signals. Summary of the invention

[0003] The purpose of the present invention is to overcome the problems in the above-mentioned existing solutions, such as the need for too many operational amplifiers, inappropriate analog circuit connection methods leading to increased production costs of the entire microcontroller, and low processing efficiency of analog signals. On this basis, a signal detection structure with programmable channel multiplexing is proposed.

[0004] Specific implementation method: A signal detection structure for programmable channel multiplexing includes an input signal selector, a programmable gain amplifier, a signal detection module, and a control logic module. The input end of the input signal selector is connected to a plurality of external microcontroller chip pins and the output end of the control logic module. The output end of the input signal selector is connected to the programmable gain amplifier. The control signal in the control logic module controls the input signal selector and selects one group of input channels in the input signal selector. The selected input channel transmits the voltage signal of the corresponding chip pin to the programmable gain amplifier. The programmable gain amplifier is connected to a gain control register, and the gain control register is used to provide a user programming channel to configure and select the amplification factor of the programmable gain amplifier for the voltage signal; The output signal of the programmable gain amplifier enters the next-level signal detection module, which uses one or more signal processing devices such as an analog-to-digital converter or a voltage comparator; The output end of the signal detection module is connected to the input end of the control logic module. The signal detection module synchronizes the output result to the control logic module, and the control logic module uses this as a reference to control the input signal selector to perform the next step.

[0005] Furthermore, the location of the gain control register in the memory space is determined when the microcontroller chip is designed. When the user writes a program on the programming channel provided by the gain control register, the user uses the memory assignment instruction to write data to the spatial address of the gain register through the bus matrix to configure programmable gain amplifiers with different amplification factors and select different gain resistors to connect to the operational amplifier path.

[0006] Furthermore, after the analog-to-digital converter completes the task of sampling the current motor phase current, if no new task arrives for a long time, the analog-to-digital converter can automatically turn off the power supply and input clock to reduce power consumption.

[0007] Furthermore, the analog-to-digital converter is connected to a first status register. When the analog-to-digital converter reaches a fixed clock cycle when entering the analog-to-digital conversion, the completion of the conversion is indicated by setting a flag bit of the first status register, so that the control logic module obtains a completion signal of the analog-to-digital converter; The voltage comparator is connected to a second status register. When the time for the voltage comparator to start voltage comparison reaches a fixed clock cycle, the comparison result and the comparison completion flag are updated through the set flag of the second status register, so that the control logic module obtains the completion signal and comparison result of the voltage comparator.

[0008] Both the analog-to-digital converter and the voltage comparator are external op amp tasks originally required in motor control applications. Both are placed in a programmable channel multiplexing signal detection structure built inside the microcontroller chip, achieving more efficient analog signal detection tasks using a minimum number of op amps, and more directly reflecting the practicality of the programmable channel multiplexing signal detection structure in motor control applications. In addition, the programmable gain amplifier is connected to a gain control register, and the control logic module is connected to a selection control register. Users can write software programs and use machine instructions to allow the microcontroller chip to program any register to modify data during operation. Users can control the programmable channel multiplexing signal detection structure by themselves, greatly improving the usability of the entire multiplexing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] The following drawings are only intended to illustrate and explain the present invention, and are not intended to limit the scope of the present invention.

[0011] Figure 1 This is a schematic diagram of a signal detection structure for programmable channel multiplexing provided by the present invention. Figure 2 It is a circuit connection diagram of the signal detection module provided by the present invention.

[0012] Figure 3 It is a circuit diagram of the selection control register provided by the present invention.

[0013] Description of the reference numerals: 1. Input signal selector; 2. Programmable gain amplifier; 3. Signal detection module; 4. Control logic module; DETAILED DESCRIPTION In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0014] See also Figure 1-Figure 3 , is a signal detection structure for programmable channel multiplexing disclosed in the invention, comprising an input signal selector 1, a programmable gain amplifier 2, an output signal selector 3, a signal detection module 4, and a control logic module. The input end of the input signal selector 1 is connected to a number of external microcontroller chip pins and the output end of the control logic module 4, and the output end of the input signal selector 1 is connected to the programmable gain amplifier 2. Among them, the number of external MCU chip pins can be defined as the first group IN1, the second group IN2, ..., the xth group INx, and the number of input ports depends on the chip design. The x groups of pins are all connected to the input end of the programmable gain amplifier 2 through the input channel selector. In this process, the control signal in the control logic module 4 controls the input signal selector 1 and selects one of the input channels in the input signal selector 1. The selected input channel transmits the voltage signal of the corresponding chip pin to the programmable gain amplifier 2, that is, in one operation cycle of the programmable gain amplifier 2, only one group of pin INx analog signals can be transmitted to the input end of the programmable gain amplifier 2 through the input channel selector, so as to avoid multiple groups of input signals entering the input end of the programmable gain amplifier 2 at the same time, which will cause signal interference and affect the signal amplification effect.

[0015] Furthermore, the programmable gain amplifier 2 is connected to a gain control register, which is used to provide a user programming channel to configure and select the amplification factor of the voltage signal of the programmable gain amplifier 2. The location of the gain control register in the memory space has been determined when the MCU chip is designed, that is, the number of gain channels on the programmable gain amplifier 2 is already determined. When the user writes a program on the programming channel provided by the gain control register, the user writes data to the space address where the gain register is located through the bus matrix through the memory assignment instruction to configure the programmable gain amplifier 2 with different amplification factors, and choose to connect different gain resistors to the op amp path. The user can freely adjust the amplification factor of the programmable gain amplifier 2 according to actual needs, so that the entire op amp system can dynamically adjust the gain to adapt to different signal strengths and types, and the gain resistor on the external input channel allows the user to achieve more precise gain adjustment through software configuration.

[0016] The signal detector uses one or more signal processing devices such as an analog-to-digital converter or a voltage comparator, and integrates and uses a variety of analog signal processing circuits internally to meet the needs of analog-to-digital conversion and voltage signal comparison.

[0017] Preferably, after the analog-to-digital converter completes the task of sampling the current motor phase current, if no new task arrives for a long time, the analog-to-digital converter can automatically turn off the power supply and input the clock to reduce power consumption. Specifically, after completing the current motor phase current sampling task, and the input end of the analog-to-digital converter does not receive a voltage signal, the analog-to-digital converter performs timing through an externally connected clock circuit. When the clock circuit reaches a set time point and a voltage signal is input at the input end of the analog-to-digital converter, the clock circuit returns to zero. When the clock circuit timing reaches a set time point and the input end of the analog-to-digital converter does not receive a voltage signal within this time period, the analog-to-digital converter turns off the power supply and the clock circuit, thereby reducing the power consumption of the overall system when not in operation.

[0018] Similarly, after the voltage comparator completes the voltage comparison task of the current motor, if no new task arrives for a long time, the voltage comparator can automatically turn off the power supply and input the clock to reduce power consumption. Specifically, after completing the voltage comparison task of the current motor, and the input end of the voltage comparator does not receive a voltage signal, the voltage comparator performs timing through an externally connected clock circuit. When the clock circuit reaches the set time point and a voltage signal is input at the input end of the voltage comparator, the clock circuit returns to zero. When the clock circuit timing reaches the set time point and the input end of the voltage comparator does not receive a voltage signal within this time period, the voltage comparator turns off the power supply and the clock circuit, thereby reducing the power consumption of the overall system when it is not working.

[0019] The analog-to-digital converter is connected to a first status register. The analog-to-digital converter requires a fixed clock cycle for analog-to-digital conversion. When the analog-to-digital converter reaches the fixed clock cycle when entering the analog-to-digital conversion, the completion of the conversion is indicated by setting a flag bit in the first status register, so that the control logic module obtains the completion signal of the analog-to-digital converter.

[0020] The voltage comparator is connected to the second state register. Similarly, the voltage comparator also needs a fixed clock cycle to perform voltage comparison. The positive and negative input voltages of the voltage comparator are always compared, but the comparison output result that is not within the fixed clock cycle is invalid. When the time for the voltage comparator to start voltage comparison reaches the fixed clock cycle, the comparison result and the comparison completion flag are updated through the set flag of the second state register, so that the control logic module obtains the completion signal and comparison result of the voltage comparator.

[0021] Specifically, the user selects the input line by controlling the value inside the ANA_INSEL_MOD register on the logic module. For example: when the internal value is 0, the value inside the ANA_INSEL register is used to control the selection of the next input line of the programmable gain amplifier 2 through software; when the internal value is 1: the input line is switched by hardware by polling the analog-to-digital converter and the voltage comparator conversion end flag, and the order of the switched input lines will be determined according to the value written in the ANA_INCHSEL register. For another example: ANA_INCHSEL register bit0~bit3 is 0, bit4~bit7 is 2, bit8~bit11 is 1. Then the order of input channel selection is: input channel 0, input channel 2, input channel 1.

[0022] The output signal selector 3 is controlled by the values ​​inside the registers ANA_ADCIN and ANA_CMPIN to control the output connection line. When the channel input channel 1 is selected inside ANA_ADCIN, after the programmable gain amplifier 2 calculates the input channel 0 signal, the output signal channel is disconnected, after the programmable gain amplifier 2 calculates the input channel 2 signal, the output signal channel is disconnected, and after the programmable gain amplifier 2 calculates the input channel 1 signal, the output signal channel is connected. The same applies to ANA_CMPIN.

[0023] The programmable gain amplifier 2, the analog-to-digital converter and the voltage comparator all have a conversion end flag to indicate the current state of the system. The specific implementation method is as follows: all three have a fixed conversion cycle, that is, a fixed time, from the beginning to the end is a fixed clock cycle. When the clock cycle is reached, the result state is updated to prepare for the next round of conversion.

[0024] The user writes a software program and converts it into memory assignment instructions that the microcontroller can recognize and execute through a compiler. Data is written to the space address of the corresponding register through the bus matrix to configure the internal value of each register, thereby achieving the effect of controlling the entire reusable op amp system.

[0025] Users can define the signal processing process through the software program. The signal processing process includes signal selection, amplification, conversion and comparison. Users can customize the signal processing process to flexibly apply it to different usage scenarios or adapt to different usage conditions, thereby enhancing the adaptability of the overall system. The program can also set specific conditions to trigger specific operations. For example, when the voltage comparator detects overcurrent, the system can shut down the motor to improve safety.

[0026] In summary, the programmable gain amplifier 2 is connected to the gain control register, and the control logic module is connected to the selection control register. The user writes a software program and uses machine instructions to enable the microcontroller chip to modify the data of the corresponding register during operation, so that the user can freely control the entire reusable operational amplifier system, greatly improving the flexibility and practicality of use.

[0027] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions or improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A signal detection structure for programmable channel multiplexing, characterized in that: The invention comprises an input signal selector (1), a programmable gain amplifier (2), a signal detection module (3), and a control logic module (4); the input end of the input signal selector (1) is connected to a plurality of external MCU chip pins and the output end of the control logic module (4); the output end of the input signal selector (1) is connected to the programmable gain amplifier (2); a control signal in the control logic module (4) controls the input signal selector (1) and selects one group of input channels in the input signal selector (1); the selected input channel transmits the voltage signal of the corresponding chip pin to the programmable gain amplifier (2); The programmable gain amplifier (2) has a programmable gain control register, and the gain control register is used to provide programming for a user to configure and select the amplification factor of the programmable gain amplifier (2) for a voltage signal; The control logic module (4) is configured so that the amplifier signal enters the next-stage signal detection module (3), and the signal detection module (3) adopts one or more signal processing devices such as an analog-to-digital converter or a voltage comparator; The output end of the signal detection module (3) is connected to the input end of the control logic module (4), and the signal detection module (3) synchronizes the output result to the control logic module (4), which uses this as a reference to perform the next step.

2. A signal detection structure for programmable channel multiplexing according to claim 1, characterized in that: The gain control register is located in the memory space when the MCU chip is designed. When the user writes a program on the programming channel provided by the gain control register, the user uses the memory assignment instruction to write data to the space address where the gain register is located through the bus matrix to configure different amplification factors and physically connect different gain resistors to the amplifier path.

3. The signal detection structure of programmable channel multiplexing according to claim 1, characterized in that: After the analog-to-digital converter completes the task of sampling the current motor phase current, if no new tasks arrive for a long time, the analog-to-digital converter can automatically turn off the power supply and input clock to reduce power consumption.

4. The signal detection structure of programmable channel multiplexing according to claim 1, characterized in that: When the signal detection module (3) is an analog-to-digital converter, it is connected to a first status register. When the analog-to-digital converter reaches a fixed clock cycle when entering analog-to-digital conversion, the completion of the conversion is indicated by setting a flag bit of the first status register, so that the control logic module (4) obtains a completion signal of the analog-to-digital converter; the control logic module (4) uses this as a reference and performs channel switching according to a conversion signal sequence configured in the control logic module (4).

5. The signal detection structure of programmable channel multiplexing according to claim 1, characterized in that: When the signal detection module (3) is a voltage comparator, it is connected to a second state register. When the time for the voltage comparator to start voltage comparison reaches a fixed clock cycle, the comparison result and the comparison completion flag are updated through the set flag of the second state register, so that the control logic module (4) obtains the completion signal of the voltage comparator. The control logic module (4) uses this as a reference and performs channel switching through the conversion signal sequence configured in the control logic module (4).

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