In-memory calculation method and device of floating-point number index and storage medium

Abstract

The invention relates to the field of in-memory calculation, and provides an in-memory calculation method and device of a floating-point number exponent and a storage medium, the method is applied to an in-memory calculation structure of the floating-point number exponent, the structure comprises a static random access memory (SRAM) row, a first delay chain and a maximum value searching and difference value generating module, the first delay chain is formed by connecting N in-memory computing units (CIMs) in series; according to the in-memory calculation method of the floating-point number index, an input floating-point number index and a weight floating-point number index are divided into a high part and a low part, maximum value searching and difference value generation are carried out on the high part and the low part respectively, and double-edge index summation calculation is carried out on a rising edge and a falling edge of an output pulse. The amount of data needing to be stored and the number of calculation units are reduced, the circuit area of calculation in the floating-point number index memory can be reduced, and the calculation time and the calculation power consumption can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of in-memory calculation, and in particular to an in-memory calculation method, device and storage medium for floating point exponents. Background Art

[0002] In the field of neural networks, the accuracy of the network model determines the final recognition accuracy of the model. Currently, most in-memory computing chips only support integer multiplication and accumulation calculations, so the accuracy of the weights and activation values ​​in the model needs to be converted from floating point numbers to integers, which reduces the accuracy of the overall neural network model. In order to improve the recognition accuracy of the neural network model, some in-memory computing architectures and methods that can calculate floating point multiplication and accumulation have been developed. Among them, floating point in-memory computing in the time domain is also one of the types with higher energy efficiency.

[0003] Compared with the in-memory calculation of integers, the structure and calculation process of the in-memory calculation of floating-point numbers in the time domain are more complicated. In the in-memory calculation of floating-point numbers in the time domain, there are mainly two different calculation processes: exponential addition and mantissa multiplication and accumulation. Among them, the mantissa multiplication and accumulation is the same as the in-memory calculation of integers, so the difference lies mainly in the calculation process of exponential addition. However, since doubling operations cannot be performed in the summation operation in the time domain, for the summation operation of multi-bit exponents, the multi-bit exponential values ​​must be converted into thermometer codes with the same weight for each bit, and then the summation operation is performed. For example, if the exponent is n bits, it requires 2 after conversion to thermometer code. n -1 storage unit to store data and 2 n -1 computing unit is used to calculate the exponential sum. At the same time, since the delay time of each computing unit is basically the same, more computing units mean longer computing time and more power consumption. Summary of the invention

[0004] The present invention provides an in-memory calculation method, device and storage medium for floating-point exponents, which are used to solve the defects of large power consumption and calculation time required for exponential summation operation in the in-memory calculation of time-domain floating-point exponents in the prior art.

[0005] The present invention provides an in-memory calculation method for a floating-point number exponent, which is applied to an in-memory calculation structure for a floating-point number exponent, wherein the in-memory calculation structure for a floating-point number exponent comprises a static random access memory SRAM row, a first delay chain, and a maximum value search and difference generation module, wherein the first delay chain is composed of N in-memory calculation units CIM connected in series; the in-memory calculation method for a floating-point number exponent comprises: The input floating-point exponent to be calculated and the weighted floating-point exponent are equally divided into high-order bits and low-order bits, and the high-order bits are converted into high-order thermometer codes and stored in the SRAM row, and the low-order bits are converted into low-order thermometer codes and stored in the SRAM row; One bit of the high-order thermometer code and the low-order thermometer code is respectively taken from the SRAM row and input into the first delay chain for calculation, and the corresponding output pulse is input into the high-order unit of the maximum value search and difference generation module; the high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and the target pulse of the output pulse is screened out and input into the low-order unit of the maximum value search and difference generation module; The low-order unit searches for a maximum value and generates a difference for the target pulse at a falling edge of the output pulse to obtain an exponent and a difference corresponding to the input floating-point number exponent.

[0006] According to the in-memory calculation method of floating-point exponents provided by the present invention, the in-memory calculation unit CIM comprises a primary inverter, a secondary inverter, a tertiary inverter and a quaternary inverter connected in series in sequence; The first-stage inverter includes a transistor PM2 and a transistor NM2 connected in parallel, the second-stage inverter includes a transistor PM3 and a transistor NM3 connected in parallel, the third-stage inverter includes a transistor PM6 and a transistor NM6 connected in parallel, and the fourth-stage inverter includes a transistor PM7 and a transistor NM7 connected in parallel; A transistor NM0 and a transistor NM1 are connected in parallel between the source end of the transistor NM2 and the ground end of the first-stage inverter, and a transistor PM0 and a transistor PM1 are connected in parallel between the source end of the transistor PM2 and the power supply; The gate terminal of the transistor NM0 is connected to a first bias voltage, the first bias voltage is used to perform exponential sum calculation on the high bits of the input floating-point number exponent, and the gate terminal of the transistor NM1 is connected to the value of the high bits of the input floating-point number exponent; the gate terminal of the transistor PM0 is connected to a second bias voltage, the second bias voltage is used to perform exponential sum calculation on the low bits of the input floating-point number exponent, and the transistor PM1 is connected to the value of the low bits of the input floating-point number exponent; A transistor NM4 and a transistor NM5 are connected in parallel between the source end of the transistor NM6 and the ground end of the three-stage inverter, and a transistor PM4 and a transistor PM5 are connected in parallel between the source end of the transistor PM6 and the power supply; The gate terminal of the transistor NM4 is connected to the first bias voltage, and the gate terminal of the NM5 is connected to the value of the high bit of the weighted floating point exponent; the gate terminal of the transistor PM4 is connected to the second bias voltage, and the transistor PM5 is connected to the value of the low bit of the weighted floating point exponent.

[0007] According to the in-memory calculation method of floating-point exponents provided by the present invention, the step of taking one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row and inputting them into the first delay chain for calculation comprises: Take one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row as the target thermometer code, and input the target thermometer code and the input pulse into the in-memory calculation unit in the delay chain; In the in-memory calculation unit, when the rising edge of the input pulse signal arrives, the transistor NM2 and the transistor NM6 are turned on and generate a pull-down current, and start calculating the first exponential sum of the high-order bits of the input floating-point exponent and the high-order bits of the weighted floating-point exponent; The on-state of the transistor NM1 is controlled by the value of the high-order bit of the input floating-point exponent, and the on-state of the transistor NM5 is controlled by the value of the high-order bit of the weighted floating-point exponent.

[0008] According to the in-memory calculation method of floating-point exponents provided by the present invention, the step of taking one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row and inputting them into the first delay chain for calculation comprises: Take one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row as the target thermometer code, and input the target thermometer code and the input pulse into the in-memory calculation unit in the delay chain; In the in-memory calculation unit, when the falling edge of the input pulse arrives, the transistor PM2 and the transistor PM6 are turned on and charged and pulled up, and the second exponential sum of the low-order bits of the input floating-point exponent and the low-order bits of the weighted floating-point exponent is calculated; The on-state of the transistor PM1 is controlled by the value of the low-order bit of the input floating-point exponent, and the on-state of the transistor PM5 is controlled by the value of the low-order bit of the weighted floating-point exponent.

[0009] According to the in-memory calculation method of floating-point exponents provided by the present invention, the high-order unit of the maximum value search and difference generation module includes an inverter INV1, a NAND gate NAND1, an inverter INV2, a second delay chain, an AND gate AND, and a counter CNT1 connected in series in sequence; wherein the second delay chain is composed of a plurality of inverters connected in series; A first trigger is connected in parallel between the NAND gate NAND1 and the inverter INV2; The low-order unit of the maximum value search and difference generation module includes an inverter INV3, a NAND gate NAND2 and an inverter INV4 which are connected in series in sequence, the inverter INV4 is connected to the first branch and the second branch respectively, the first branch is connected in parallel with the second branch; a second trigger is connected in parallel between the NAND gate NAND2 and the inverter INV4; The first branch includes an OR gate OR, a NAND gate NAND3 and a third trigger connected in series in sequence; the second branch includes a third delay chain, an XNOR gate XNOR and a counter CNT2 connected in series in sequence; wherein the third delay chain is composed of a plurality of inverters connected in series.

[0010] According to the in-memory calculation method of floating-point exponent provided by the present invention, the high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and selects the target pulse of the output pulse and inputs it into the low-order unit of the maximum value search and difference generation module, including: When the rising edge of the output pulse arrives, the high-order unit determines the first pulse and the second pulse, as well as the first inverse pulse of the first pulse and the second inverse pulse of the second pulse according to the output pulse and the input pulse of each of the in-memory computing units CIM; the pulse width of the first pulse is the delay time between the rising edge of the output pulse and the input pulse, and the pulse width of the second pulse is the delay time between the falling edge of the output pulse and the input pulse; Inputting the first pulses corresponding to the N in-memory computing units CIM into the AND gate AND, screening out the first target pulse with the smallest pulse width and the first target anti-pulse corresponding to the first target pulse; Based on the first trigger, using the first anti-pulse to perform trigger sampling on the first target pulse to obtain a second target pulse; Generate a first pulse width difference between the first pulse and the first target pulse by using the AND gate AND, and input the first pulse width difference into the counter CNT1 to obtain a target difference between the first pulse and the first target pulse; According to the target difference, a third target pulse is selected from the second target pulse and input into the low-order unit of the maximum value search and difference generation module; the third target pulse is a pulse whose target difference corresponding to the second target pulse is greater than a preset value.

[0011] According to the in-memory calculation method of the floating-point number exponent provided by the present invention, the low-order unit searches for the maximum value and generates the difference of the target pulse at the falling edge of the output pulse to obtain the exponent and the difference corresponding to the input floating-point number exponent, including: When the falling edge of the output pulse arrives, the low-order unit selects a fourth target pulse with the largest low-order bit from the third target pulse; Modulating a fifth target pulse to obtain a modulated pulse and a modulated inverse pulse of the modulated pulse; the fifth target pulse is a pulse in the third target pulse except the fourth target pulse; Selecting a target modulated pulse with the largest low-order bit from the modulated pulses, and based on the third trigger, using the modulated anti-pulse to perform trigger sampling on the target modulated pulse to obtain a sixth target pulse and a sixth target anti-pulse of the sixth target pulse; A second pulse width difference between the second pulse and the sixth target counter pulse is generated, and the second pulse width difference is input into the counter CNT2 to obtain an index and a difference value corresponding to the input index.

[0012] According to the in-memory calculation method of the floating point exponent provided by the present invention, after inputting the second pulse width difference into the counter CNT2 to obtain the exponent and the difference corresponding to the input exponent, the method further includes: Based on the second trigger, the target modulation pulse is triggered by the second anti-pulse to generate the numerical sign of the index and the difference.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the in-memory calculation method of a floating-point exponent as described in any one of the above are implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the in-memory calculation method of floating-point exponents as described in any one of the above.

[0015] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the steps of the in-memory calculation method of floating-point exponents as described in any one of the above are implemented.

[0016] The in-memory calculation method, device and storage medium of floating-point exponents provided by the present invention divide the input floating-point exponent and the weighted floating-point exponent into two high and low parts for respectively performing maximum value search and difference generation, and performing exponential sum calculation of both edges at the rising edge and the falling edge of the output pulse, thereby reducing the amount of data that needs to be stored and the number of calculation units, and can not only reduce the circuit area of ​​the in-memory calculation of the floating-point exponent, but also reduce the calculation time and calculation power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic flow chart of the in-memory calculation method of floating point exponent provided by the present invention; Figure 2 It is a schematic diagram of the memory calculation structure of the floating point exponent provided by the present invention; Figure 3 It is a schematic diagram of the circuit structure of the in-memory computing unit provided by the present invention; Figure 4 It is a schematic diagram of the circuit structure of the maximum value search and difference generation module provided by the present invention; Figure 5 It is a timing diagram of the in-memory calculation process of the floating-point exponent provided by the present invention; Figure 6 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] In the related art, the multiplication and accumulation of floating-point exponents requires first calculating the exponent and input of each weight, then comparing a maximum value and using it as a reference value, and then shifting and aligning the input mantissa according to the difference between each exponent and the maximum exponent, and then performing multiplication and accumulation operations on the mantissa to obtain the final result.

[0021] Specifically, in the conventional integer multiplication and accumulation process, for multi-bit input and weight values, the data on different weight bits will be separated for calculation and shifted and added in the digital domain. However, in the exponential summation of floating-point numbers, not many values ​​are added, but each input exponent is added with the exponent of the corresponding weight. In fact, the summation of two 8-bit values ​​is required. Therefore, the operation of calculating the weights separately and then performing the shift and addition operation is not applicable to the exponential summation of floating-point numbers. At the same time, since the delay doubling operation cannot be completed in the time domain, and the exponent bit of a floating-point number is usually 8 bits, for the exponential summation of multiple bits, the exponential value of the multiple bits must be converted into a thermometer code with the same weight for each bit, and then the summation operation is performed. Generally speaking, for the exponent of an 8-bit floating point number, an 8-bit input exponent Ein and an 8-bit weight exponent Ew are converted into thermometer code, which requires a total of 510 storage units SRAM (Static Random-Access Memory) for data storage, and 255 in-memory computing units CIM (Computing In Memory) for calculating the exponent sum. In other words, to calculate the sum of an 8-bit input exponent Ein and an 8-bit weight exponent Ew, it is necessary to pass through 255 in-memory computing units CIM, and the delay and power consumption required for the calculation are relatively large.

[0022] In order to improve the calculation speed and reduce the calculation power consumption, the in-memory calculation method of the floating point exponent provided by the embodiment of the present invention adopts the bit-separated exponent summation method, which divides the n-bit exponent into high-order bits and low-order bits, that is, high n / 2 bits and low n / 2 bits, and uses the rising edge and falling edge of the input pulse to sum the high n / 2 bits and low n / 2 bits respectively. In this way, the original 2 n -1 bit thermometer code becomes two 2 n / 2-1 bit thermometer code, the number of storage units can be saved by about 88%.

[0023] Furthermore, the computing unit can simultaneously calculate the sum of the rising edge and the falling edge, saving about 94% of the number of computing units, and the upper and lower edges can be used for simultaneous calculation, which requires less calculation time and power consumption.

[0024] Specifically, Figure 1: is a flow chart of the in-memory calculation method of floating-point exponents provided by the present invention. The in-memory calculation method of floating-point exponents provided by the embodiment of the present invention is applied to the in-memory calculation structure of floating-point exponents, which includes a static random access memory SRAM row, a first delay chain and a maximum value search and difference generation module, wherein the first delay chain is composed of N in-memory calculation units CIM connected in series. Figure 1 As shown, the in-memory calculation method of floating-point exponent provided by the embodiment of the present invention includes the following steps: Step 100, dividing the exponent bits of the input floating-point exponent to be calculated and the weighted floating-point exponent into high-order bits and low-order bits, converting the high-order bits into high-order thermometer codes and storing them in the SRAM row, and converting the low-order bits into low-order thermometer codes and storing them in the SRAM row; Step 200, taking one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row and inputting them into the first delay chain for calculation, and obtaining corresponding output pulses and inputting them into the high-order unit of the maximum value search and difference generation module; Step 300, the high-order unit compares and screens the exponential sum of the high-order bits at the rising edge of the output pulse, and inputs the screened target bits into the low-order unit of the maximum value search and difference generation module; Step 400: the low-order unit searches for a maximum value and generates a difference for the target bit at the falling edge of the output pulse to obtain an exponent and a difference corresponding to the input floating-point number exponent.

[0025] The in-memory calculation method of the floating-point number exponent provided by the embodiment of the present invention is used to calculate the exponent sum of the floating-point number time domain in-memory calculation, and is applied to the in-memory calculation structure of the floating-point number exponent. The in-memory calculation structure of the floating-point number exponent is as follows: Figure 2 shown.

[0026] First, the input floating-point exponent and the weighted floating-point exponent to be calculated are equally divided into high-order bits and low-order bits, where the input floating-point exponent is the input exponent Ein, and the weighted floating-point exponent is the weighted exponent Ew, as shown in Figure 2 As shown, the input index Ein is equally divided into high bits (i.e., high n / 2 bits) and low bits (i.e., low n / 2 bits), and the weight index Ew is also equally divided into high bits (i.e., high n / 2 bits) and low bits (i.e., low n / 2 bits). For ease of distinction, the high n / 2 bits and low n / 2 bits of the input index Ein are respectively recorded as the first high bit and the first low bit, that is, the first high n / 2 bit and the first low n / 2 bit; the high n / 2 bits and low n / 2 bits of the weight index Ew are respectively recorded as the second high bit and the second low bit, that is, the second high n / 2 bit and the second low n / 2 bit.

[0027] The divided high-order bits are converted into high-order thermometer codes and stored in an SRAM row, and the low-order bits are converted into low-order thermometer codes and stored in an SRAM row, the high-order thermometer codes include a first high-order thermometer code and a second high-order thermometer code, and the low-order thermometer codes include a first low-order thermometer code and a second low-order thermometer code. Converting the high-order bits into high-order thermometer codes specifically includes converting the first high n / 2 bits of the input index Ein into a first high-order thermometer code and storing it in an SRAM row, and converting the second high n / 2 bits of the weight index Ew into a second high-order thermometer code and storing it in an SRAM row; converting the low-order bits into low-order thermometer codes specifically includes converting the first low n / 2 bits of the input index Ein into a first low-order thermometer code and storing it in an SRAM row, and converting the second low n / 2 bits of the weight index Ew into a second low-order thermometer code and storing it in an SRAM row.

[0028] Optionally, the SRAM row includes a plurality of rows, and the first high-order thermometer code, the second high-order thermometer code, the first low-order thermometer code, and the second low-order thermometer code are stored in different SRAM rows, respectively. Figure 2 As shown, the first high-order thermometer code is stored in the first SRAM row, the second high-order thermometer code is stored in the second SRAM row, the first low-order thermometer code is stored in the third SRAM row, and the second low-order thermometer code is stored in the fourth SRAM row. The first SRAM row, the second SRAM row, the third SRAM row, and the fourth SRAM row each include at least 1×(2^(n / 2)-1 bit.

[0029] One bit of the high-order thermometer code and one bit of the low-order thermometer code are respectively taken from the SRAM row and input into the first delay chain for calculation, that is, one bit is taken from the first high-order thermometer code in the first SRAM row, one bit is taken from the second high-order thermometer code in the second SRAM row, one bit is taken from the first low-order thermometer code in the third SRAM row, and one bit is taken from the second low-order thermometer code in the fourth SRAM row, and then input into the same in-memory calculation unit CIM in the first delay chain for calculation, and the corresponding output pulse is input into the high-order unit of the maximum value search and difference generation module.

[0030] Furthermore, the high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and selects the target pulse of the output pulse and inputs it into the low-order unit of the maximum value search and difference generation module. The low-order unit performs maximum value search and difference generation on the target pulse on the falling edge of the output pulse to obtain the exponent and difference corresponding to the input floating-point number exponent.

[0031] In one embodiment, one bit is taken from the high n / 2 bits of Ein, the low n / 2 bits of Ein, the high n / 2 bits of Ew and the low n / 2 bits of Ew respectively and input into the same in-memory calculation unit CIM, and then after the calculation of the first delay chain, the output pulses of k different exponential additions to be calculated are connected to the high n / 2 bit maximum value search and difference generation module, and the high n / 2 bit exponent sum is compared. Assuming that the difference between the exponential sum of m high n / 2 bits and the maximum value of the exponential sum is not greater than the preset value, the exponential sum of m high n / 2 bits is input into the low-order unit of the maximum value search and difference generation module, and the low n / 2 bits of m high n / 2 bits are searched for the maximum value and difference generation to obtain the complete exponent sum difference. Because the difference between the exponential sum and the maximum value of the remaining km rows is greater than the preset value, a skip signal Skip is directly generated, thereby skipping all subsequent calculation operations.

[0032] In the related technology of exponential addition operation of floating-point numbers, the search for the maximum value and the generation of the difference are set as two independent modules, which requires a larger circuit area and requires additional data transmission consumption. In the present embodiment, the search for the maximum value and the generation of the difference are integrated into the same module, which improves the circuit integration, helps to reduce the circuit area of ​​the in-memory computing structure, and can also reduce the time and power consumption of data transmission.

[0033] Moreover, in the related art, because there is a large difference between the results of different exponential additions, the exponential sum calculation result is usually ignored when the exponential sum calculation result is much smaller than the maximum value, thereby reducing the subsequent shift and mantissa multiplication and accumulation power consumption. In this embodiment, a judgment can be made directly based on the calculation result of the high-order bit, so that the exponential sum calculation process of the low-order bit can be ignored, thereby further reducing the calculation power consumption.

[0034] In this embodiment, the input floating-point exponent and the weighted floating-point exponent are divided into two parts, a high part and a low part, for respectively performing maximum value search and difference generation, and performing bilateral exponential sum calculation on the rising and falling edges of the output pulse. This reduces the amount of data that needs to be stored and the number of computing units, which not only reduces the circuit area for in-memory calculation of the floating-point exponent, but also reduces the calculation time and power consumption.

[0035] In one embodiment, referring to Figure 2The structure of the in-memory computing unit CIM shown in the figure includes a first-stage inverter, a second-stage inverter, a third-stage inverter and a fourth-stage inverter connected in series in sequence. Among them, the first-stage inverter includes a transistor PM2 and a transistor NM2 connected in parallel, the second-stage inverter includes a transistor PM3 and a transistor NM3 connected in parallel, the third-stage inverter includes a transistor PM6 and a transistor NM6 connected in parallel, and the fourth-stage inverter includes a transistor PM7 and a transistor NM7 connected in parallel.

[0036] Optionally, transistors NM0 and NM1 are connected in parallel between the source terminal of transistor NM2 and the ground terminal of the first-stage inverter, and transistors PM0 and PM1 are connected in parallel between the source terminal of transistor PM2 and the power supply. The gate terminal of transistor NM0 is connected to a first bias voltage, the first bias voltage is used to perform exponential sum calculation on the high bits of the input floating-point number exponent, and the gate terminal of transistor NM1 is connected to the value of the high bits of the input floating-point number exponent; the gate terminal of transistor PM0 is connected to a second bias voltage, the second bias voltage is used to perform exponential sum calculation on the low bits of the input floating-point number exponent, and transistor PM1 is connected to the value of the low bits of the input floating-point number exponent; parallel transistors NM4 and NM5 are connected between the source terminal of transistor NM6 and the ground terminal of the three-stage inverter, and parallel transistors PM4 and PM5 are connected between the source terminal of transistor PM6 and the power supply; the gate terminal of transistor NM4 is connected to the first bias voltage, and the gate terminal of NM5 is connected to the value of the high bits of the weighted floating-point number exponent; the gate terminal of transistor PM4 is connected to the second bias voltage, and transistor PM5 is connected to the value of the low bits of the weighted floating-point number exponent.

[0037] Based on the structure of the in-memory computing unit CIM, in step 200, one bit of the high-order thermometer code and one bit of the low-order thermometer code are respectively taken from the SRAM row and input into the first delay chain for calculation, including: Step 210, taking one bit of the high-order thermometer code and the low-order thermometer code from the SRAM row as the target thermometer code, and inputting the target thermometer code and the input pulse into the in-memory calculation unit in the first delay chain; Step 220, in the in-memory calculation unit, when the rising edge of the input pulse signal arrives, the transistor NM2 and the transistor NM6 are turned on and generate a pull-down current, and start calculating the first exponential sum of the high-order bit of the input floating-point exponent and the high-order bit of the weighted floating-point exponent; The on-state of the transistor NM1 is controlled by the value of the high-order bit of the input floating-point exponent, and the on-state of the transistor NM5 is controlled by the value of the high-order bit of the weighted floating-point exponent.

[0038] Furthermore, in step 200, taking one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row and inputting them into the first delay chain for calculation may also include: Step 201, taking one bit of the high-order thermometer code and the low-order thermometer code from the SRAM row as the target thermometer code, and inputting the target thermometer code and the input pulse into the in-memory calculation unit in the first delay chain; Step 202, in the in-memory calculation unit, when the falling edge of the input pulse arrives, the transistor PM2 and the transistor PM6 are turned on and charged and pulled up, and start calculating the second exponential sum of the low-order bit of the input floating-point exponent and the low-order bit of the weighted floating-point exponent; The on-state of the transistor PM1 is controlled by the value of the low-order bit of the input floating-point exponent, and the on-state of the transistor PM5 is controlled by the value of the low-order bit of the weighted floating-point exponent.

[0039] exist Figure 3 In the structure of the in-memory computing unit CIM shown, four stages of inverters are connected in series to connect the input pulse PULSEIN and the output pulse PULSEOUT: the first-stage inverter includes transistor PM2 and transistor NM2 connected in parallel, the second-stage inverter includes transistor PM3 and transistor NM3 connected in parallel, the third-stage inverter includes transistor PM6 and transistor NM6 connected in parallel, and the fourth-stage inverter includes transistor PM7 and transistor NM7 connected in parallel.

[0040] Optionally, an additional calculation structure is added to the ground terminal of the first-stage inverter and the third-stage inverter to calculate the exponential sum of the high n / 2 bits of the input floating-point number exponent and the weighted floating-point number exponent. In the first-stage inverter, two transistors NM0 and NM1 are connected in parallel between the ground terminal and the source terminal of the transistor NM2, the gate terminal of NM0 is connected to the fixed bias voltage VBIAS_H for the high n / 2 bit exponential sum calculation, and the gate terminal of NM1 is connected to the value IN_H corresponding to the high n / 2 bit part of the exponent bit of the input floating-point value corresponding to the in-memory calculation unit CIM. In the third-stage inverter, two transistors NM4 and NM5 are connected in parallel between the ground terminal and the source terminal of the transistor NM6, the gate terminal of NM4 is connected to the fixed bias voltage VBIAS_H for the high n / 2 bit exponential sum calculation, and the gate terminal of NM5 is connected to the value W_H corresponding to the high n / 2 bit part of the exponent bit of the weighted floating-point value corresponding to the in-memory calculation unit CIM.

[0041] Optionally, additional calculation structures are added to the power supply terminals of the first-stage inverter and the third-stage inverter to calculate the low n / 2bit exponent sum of the floating-point input and the weight. In the first-stage inverter, two transistors PM0 and PM1 are connected in parallel between the power supply and the source terminal of the transistor PM2, the gate terminal of PM0 is connected to the fixed bias voltage VBIAS_L for low n / 2bit exponent sum calculation, and the gate terminal of PM1 is connected to the value IN_L corresponding to the low n / 2bit part of the exponent bit of the input floating-point number exponent value corresponding to the in-memory calculation unit CIM. In the third-stage inverter, two transistors PM4 and PM5 are connected in parallel between the power supply and the source terminal of the transistor PM6, the gate terminal of PM4 is connected to the fixed bias voltage VBIAS_L for low n / 2bit exponent sum calculation, and the gate terminal of PM5 is connected to the value W_L corresponding to the low n / 2bit part of the exponent bit of the weight floating-point number exponent value corresponding to the in-memory calculation unit CIM.

[0042] When one bit of the high thermometer code and one bit of the low thermometer code are respectively taken from the SRAM row and input into the first delay chain for calculation, specifically one bit of the high thermometer code and one bit of the low thermometer code are respectively taken from the SRAM row as the target thermometer code, and the target thermometer code includes one bit of the first high thermometer code, one bit of the second high thermometer code, one bit of the first low thermometer code and one bit of the second low thermometer code. The target thermometer code is input into the in-memory calculation unit of the first delay chain together with the input pulse for calculation.

[0043] Specifically, when the rising edge of the input pulse arrives, the transistor NM2 in the first-stage inverter and the transistor NM6 in the third-stage inverter are turned on and discharged downward, and the high n / 2bit exponent sum of the input floating-point number exponent and the weighted floating-point number exponent is calculated. In the first-stage inverter, there is an inherent current path turned on by NM0, and another parallel path NM1 controlled by the high n / 2bit exponent value IN_H of the input floating-point number exponent. In the third-stage inverter, there is an inherent current path turned on by NM4, and another parallel path NM5 controlled by the high n / 2bit exponent value W_H of the weighted floating-point number exponent. When the values ​​of IN_H and W_H are both 0, transistors NM1 and NM5 are both in the off state, so only the inherent current path is turned on to generate a pull-down current, and the actual input pulse rising edge delay is also greater. When one of IN_H and W_H is 1, one of the first-stage inverter and the third-stage inverter is pulled down by two transistors at the same time, while the other is still pulled down by an inherent current path, so the actual input pulse rising edge delay is smaller than when both values ​​are 0. When the values ​​of IN_H and W_H are both 1, the first-stage inverter and the third-stage inverter are pulled down by two parallel transistors at the same time, so the actual input pulse rising edge delay is smaller. Therefore, when using the rising edge to calculate the high n / 2bit exponential sum, as the value of IN_H+W_H increases, the delay of the input pulse rising edge will decrease accordingly.

[0044] When the falling edge of the input pulse arrives, the transistor PM2 in the first-stage inverter and the transistor PM6 in the third-stage inverter are turned on and charged and pulled up, and the exponential sum of the low n / 2 bits of the input floating-point exponent and the weighted floating-point exponent begins to be calculated. In the first-stage inverter, there is an inherent current path turned on by transistor PM0, and another parallel path PM1 controlled by the low n / 2-bit exponent value IN_L of the input floating-point exponent. In the third-stage inverter, there is an inherent current path turned on by transistor PM4, and another parallel path PM5 controlled by the low n / 2-bit exponent value W_L of the weighted floating-point exponent. When the values ​​of IN_L and W_L are both 0, transistors PM1 and PM5 are both in the off state, so only the inherent current path is turned on to generate pull-up current, and the actual falling edge delay of the input pulse is also greater. When one of IN_L and W_L has a value of 1, one of the first-stage inverter and the third-stage inverter is pulled up by two transistors at the same time, while the other is still pulled up by an inherent current path, so the actual falling edge delay of the input pulse is smaller than when both values ​​are 0. When the values ​​of IN_L and W_L are both 1, the first-stage inverter and the third-stage inverter are pulled up by two parallel transistors at the same time, so the actual falling edge delay of the input pulse is smaller. Therefore, when using the falling edge to calculate the low n / 2bit exponential sum, as the value of IN_L+W_L increases, the delay of the falling edge of the input pulse will decrease accordingly. Among them, the target thermometer code is used to control the delay.

[0045] In this summation method, the Figure 4 The structure of the maximum value search and difference generation module shown in FIG. Figure 4 As shown, the maximum value search and difference generation module includes a high-order unit and a low-order unit. In the high-order unit, an inverter INV1, a NAND gate NAND1, an inverter INV2, a second delay chain, an AND gate AND, and a counter CNT1 are sequentially connected in series; wherein the second delay chain is composed of a plurality of inverters connected in series. A first trigger DFF1 is connected in parallel between the NAND gate NAND1 and the inverter INV2.

[0046] Furthermore, the low-order unit sequentially connects an inverter INV3, a NAND gate NAND2 and an inverter INV4 in series, the inverter INV4 is connected to the first branch and the second branch respectively, and the first branch is connected in parallel with the second branch; a second trigger DFF2 is connected in parallel between the NAND gate NAND2 and the inverter INV4.

[0047] Furthermore, the first branch includes an OR gate OR, a NAND gate NAND3 and a third trigger DFF3 connected in series in sequence; the second branch includes a third delay chain, an XNOR gate XNOR and a counter CNT2 connected in series in sequence; wherein the third delay chain is also composed of a plurality of inverters connected in series.

[0048] based on Figure 4 The structure of the maximum value search and difference generation module shown in FIG. 1 , in step 300 , the high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and selects the target pulse of the output pulse and inputs it into the low-order unit, including: Step 310, when the rising edge of the output pulse arrives, the high-order unit determines the first pulse and the second pulse, as well as the first inverse pulse of the first pulse and the second inverse pulse of the second pulse according to the output pulse and the input pulse of each of the in-memory computing units CIM; the pulse width of the first pulse is the delay time between the rising edge of the output pulse and the input pulse, and the pulse width of the second pulse is the delay time between the falling edge of the output pulse and the input pulse; Step 320, inputting the first pulses corresponding to the N in-memory computing units CIM into the AND gate AND, screening out the first target pulse with the smallest pulse width and the first target anti-pulse corresponding to the first target pulse; Step 330, based on the first trigger, using the first anti-pulse to perform trigger sampling on the first target pulse to obtain a second target pulse; Step 340, using the AND gate AND, generating a first pulse width difference between the first pulse and the first target pulse, and inputting the first pulse width difference into the counter CNT1 to obtain a target difference between the first pulse and the first target pulse; Step 350, according to the target difference, select a third target pulse from the second target pulse and input it into the low-order unit of the maximum value search and difference generation module; the third target pulse is a pulse whose target difference corresponding to the second target pulse is greater than a preset value.

[0049] Further, in step 400, the low-order unit searches for the maximum value and generates the difference of the input target pulse at the falling edge of the output pulse to obtain the exponent and the difference corresponding to the input floating-point number exponent, including: Step 410, when the falling edge of the output pulse arrives, the low-order unit selects a fourth target pulse with the largest low-order bit from the third target pulse; Step 420, modulating the fifth target pulse to obtain a modulated pulse and a modulated inverse pulse of the modulated pulse; the fifth target pulse is a pulse in the third target pulse except the fourth target pulse; Step 430, selecting a target modulated pulse with the largest low-order bit from the modulated pulses, and based on the third trigger, using the modulated anti-pulse to perform trigger sampling on the target modulated pulse to obtain a sixth target pulse and a sixth target anti-pulse of the sixth target pulse; Step 440 , generating a second pulse width difference between the second pulse and the sixth target counter pulse, and inputting the second pulse width difference into the counter CNT2 to obtain an index and a difference value corresponding to the input index.

[0050] The exponent sum difference is the calculation result of the exponent sum of the input floating point exponent. In step 440, after inputting the second pulse width difference into the counter CNT2 to obtain the exponent sum difference corresponding to the input exponent, the following may also be included: Step 450: Based on the second trigger, the second anti-pulse is used to perform trigger adoption on the target modulation pulse to generate numerical symbols of the index and the difference.

[0051] According to the input pulse PULSEIN and the output pulse PULSEOUT of each row memory calculation unit CIM in the first delay chain, a first pulse and a first anti-pulse whose pulse width is equal to the delay time of the rising edge can be obtained, namely, the pulse PULSERISE and its anti-pulse PULSERISE_B, and a second pulse and a second anti-pulse whose pulse width is equal to the delay time of the falling edge, namely, the pulse PULSEFALL and its anti-pulse PULSEFALL_B. Among them, the output pulse PULSEOUT is obtained by adjusting the delay of the input pulse PULSEIN through the first delay chain based on the target thermometer code obtained by taking one bit from the high n / 2bit of Ein, the low n / 2bit of Ein, the high n / 2bit of Ew and the low n / 2bit of Ew, respectively. Figure 4 In the embodiment, the output pulse PULSEOUT and the preset reference pulse PULSEERF are used as the input of the maximum value search and difference generation module.

[0052] In the maximum value search and difference generation module, the high-order unit uses the pulse width of the rising edge to search for the maximum value of the upper n / 2 bits and generate the difference, and the low-order unit uses the pulse width of the falling edge combined with the difference generation result of the upper n / 2 bits to search for the maximum value of the lower n / 2 bits and generate the difference. Specifically, in the maximum value search of the upper n / 2 bits, the high-order unit inputs the pulse PULSERISE corresponding to the delay time of the rising edge of N rows into the same AND gate AND, and selects the first target pulse with the smallest pulse width, that is, pulse RISE_MAX, and its first target anti-pulse RISE_MAX_B.

[0053] The high-order unit uses the pulse PULSERISE_B of each row to perform D-type flip-flop DFF sampling on the pulse RISE_MAX to obtain the second target pulse. In the second target pulse, the TAG1 of the row with the largest value of the high n / 2bit will be reduced from 1 to 0 for preliminary screening, and the TAG1 of the remaining rows will remain 1. At the same time, the pulse width difference between the pulse PULSERISE and the pulse RISE_MAX is generated by the AND gate AND and input into the counter CNT1 to generate the target difference HIGH<3:0> between the data of each row in the high n / 2bit and the maximum value. Figure 4 As shown, with 1 as the preset value, if the target difference is greater than 1, it can be considered that the difference between the data of the row and the index and the maximum value is too large, and the subsequent calculation of the corresponding lower n / 2 bits can be stopped through a control signal.

[0054] For the third target pulse whose target difference is less than or equal to 1, the low-order unit will compare the rows with the largest values ​​of the upper n / 2 bits to select the fourth target pulse with the largest lower n / 2 bits. When generating the AND result of the falling edge pulse width, only the row with the largest value of the upper n / 2 bits is retained, and the remaining rows are modulated as the fifth target pulse through the TAG1B signal, and the pulse is controlled to 1 to obtain the modulated pulse PULSEFALL_MODULATED and its inverse pulse PULSEFALL_MODULATED_B of each row. The inverse pulse PULSEFALL_MODULATED_B is also a modulated inverse pulse, which will not affect the generation of the AND result of the falling edge pulse width. Finally, the modulated target modulated pulse PULSEFALL_MODULATED_MAX with the largest lower n / 2 bits can be obtained.

[0055] In the process of searching for the maximum value of the lower n / 2 bits, the modulation counter pulse PULSEFALL_MODULATED_B is used to perform D flip-flop DFF sampling on the target modulation pulse PULSEFALL_MODULATED_MAX. Finally, among the rows that are not skipped in the high-order cells, the TAG2 of the row with the largest value of the upper n / 2 bits and the largest value of the lower n / 2 bits will be reduced from 1 to 0, and the final maximum value search result will be obtained.

[0056] Furthermore, the low-bit unit will also generate the pulse width difference between the pulse PULSEFALL and the pulse PULSEFALL_MODULATED_MAX_B, and input it into the counter CNT2 to generate the low n / 2bit difference LOW<3:0>. Since there is a situation where the high n / 2bit is smaller than the maximum value but the low n / 2bit is larger than the maximum value, the low n / 2bit difference is signed. While generating the low n / 2bit difference, based on the second flip-flop DFF2, the pulse PULSEFALL_B is used to perform D flip-flop sampling on the pulse PULSEFALL_MODULATED_MAX to generate the numerical sign LOW_SIGN of the low n / 2bit difference.

[0057] In one embodiment, referring to Figure 5 The timing diagram shown, Figure 5 The timing flow of exponential sum calculation of floating-point numbers in one calculation cycle is given. In any calculation cycle, the exponential sum calculation of floating-point numbers mainly includes the exponential calculation of the upper n / 2 bits and the exponential calculation of the lower n / 2 bits.

[0058] like Figure 5 As shown in FIG. 1 , it is assumed that four delayed output pulses PULSEOUT<3:0> are generated according to the input pulse PULSEIN, wherein the rising edge portion PULSEOUT <3> and PULSEOUT <1> At the same time, it is the first to arrive, the falling edge part PULSEOUT <2> Is the first to arrive, PULSEOUT <2> Since the difference between the high n / 2bit part and the maximum value is greater than 1, the remaining part is skipped, and the maximum value finally screened out is PULSEOUT <1> .

[0059] In the high n / 2bit exponential calculation stage, the high-order unit generates four pulses PULSERISE<3:0> with different pulse widths to represent four output pulses based on the pulse width difference between the rising edge of the input pulse PULSEIN and the rising edge of PULSEOUT<3:0>, and inputs the four output pulses into the AND gate at the same time to obtain the pulse RISE_MAX with the smallest pulse width, which is also the maximum value of the four output pulses. According to the in-memory calculation structure, each row will use the pulse PULSERISE_B to perform D-type flip-flop sampling on the pulse RISE_MAX. If the pulse PULSERISE is the pulse RISE_MAX with the smallest pulse width, the corresponding TAG1 will change from 1 to 0, that is, Figure 5TAG1 in <3> and TAG1 <1> , these two rows of pulses are the rows where the maximum value of the high n / 2bit exponent sum is located. The subsequent low-order units need to select the one with the larger value of the low n / 2bit from these two rows according to the low n / 2bit. At the same time, each pulse PULSERISE will perform a logical operation with the pulse RISE_MAX to obtain the distance between the falling edges of the two, that is, the pulse width difference. This distance is sent to the counter CNT1 to obtain the difference between the high n / 2bit exponent sum of each row and the maximum value of the high n / 2bit exponent sum. PULSEOUT <2> Since the difference between the high n / 2 bit part and the maximum value is greater than 1, the corresponding low n / 2 bit exponent calculation stage is directly skipped.

[0060] In the low n / 2bit exponent calculation stage, the low bit units are calculated based on the falling edge of the input pulse PULSEIN and the PULSEOUT<3:0> bits except the skipped PULSEOUT <2> The distance between the three falling edges other than the PULSEFALL<3:0> pulses with three different pulse widths is used to represent four output pulses (PULSEFALL<3:0> <2> The four pulses are ORed with the corresponding TAG1, so that the high n / 2 bit value is not the largest pulse PULSEOUT <2> and pulse PULSEOUT <0> After filtering out, we finally get two modulated falling edge delay pulses PULSEFALL_MODULATED which are always 1. <2> and PULSEFALL_MODULATED <0> , and two normal output falling edge delay pulses PULSEFALL_MODULATED <3> and PULSEFALL_MODULATED <1> The four modulated falling edge delay pulses pass through the AND gate to obtain the pulse PULSEFALL_MODULATED_MAX with the smallest modulated pulse width, which is the maximum value among the four modulated pulses. According to the in-memory calculation structure, each row uses pulse PULSEFALL_MODULATED_B to perform D-type flip-flop sampling on pulse PULSEFALL_MODULATED_MAX. At this time, the valid pulse PULSEFALL_MODULATED_B has only <3> and <1> So in fact, we find the pulse with the lower n / 2 bits between these two pulses, and its corresponding TAG2 will also drop from 1 to 0, that is, Figure 5TAG2 in <1> At the same time, each pulse PULSEFALL will perform a logic operation with the pulse PULSEFALL_MODULATED_MAX_B to obtain the distance between the falling edges of the two, that is, the pulse width difference between the two. This distance is sent to the counter CNT2 to obtain the difference between the high n / 2bit exponent sum of each row and the high n / 2bit exponent sum maximum value.

[0061] Since there is a row with a high n / 2 bit value smaller than <3> and <1> The high n / 2bit value of the row is smaller, but its low n / 2bit value is greater than the low n / 2bit value of the two. Therefore, although the overall n-bit value of the row is smaller, the low n / 2bit value is larger. At this time, a sign bit is needed to describe this difference. Therefore, in the low n / 2bit exponential calculation stage, based on the second flip-flop DFF2, the pulse PULSEFALL_B is used to perform D flip-flop sampling on the pulse PULSEFALL_MODULATED_MAX, and the result LOW_SIGN is the sign bit of the corresponding low n / 2bit difference.

[0062] In the relevant floating-point time-domain in-memory computing architecture, it is often necessary to fully expand the exponential calculation results of n bits, so more circuit area, longer computing time and greater computing power consumption are usually required. In this embodiment, the sum of the n-bit exponent is divided into two n / 2-bit exponential sums for calculation, which greatly reduces the circuit area, computing time and computing power consumption while ensuring that exponential addition, maximum value search and difference generation are performed simultaneously. At the same time, more efficient sparse processing is achieved through the bit separation architecture, and the processing of the low n / 2 bits is directly skipped when the high n / 2 bit difference is large, further reducing computing power consumption.

[0063] Furthermore, the in-memory calculation method of the floating-point exponent provided by the embodiment of the present invention divides the sum of the exponent of the floating-point number into two different parts, the high-order bits and the low-order bits, and performs summation, maximum value search and difference generation respectively, thereby reducing the amount of data that needs to be stored, thereby reducing the number of storage units and calculation units, which is beneficial to reducing the area of ​​the in-memory calculation circuit, improving the integration, and reducing the calculation time and power consumption.

[0064] Furthermore, by integrating the maximum value search and the difference generation, the additional data transmission consumption and data transmission time required in the maximum value search and the difference generation process are reduced. In addition, by adopting a sparse processing method of separating high and low bits, when the difference of the high bits is large, the processing of the corresponding low bits is skipped, thereby further reducing power consumption.

[0065] Figure 6An example of a physical structure diagram of an electronic device is shown in FIG. Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630 and a communication bus 640, wherein the processor 610, the communication interface 620 and the memory 630 communicate with each other through the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute the steps of the in-memory calculation method of the floating point exponent, for example including: The input floating-point exponent to be calculated and the weighted floating-point exponent are equally divided into high-order bits and low-order bits, and the high-order bits are converted into high-order thermometer codes and stored in the SRAM row, and the low-order bits are converted into low-order thermometer codes and stored in the SRAM row; One bit of the high-order thermometer code and the low-order thermometer code is respectively taken from the SRAM row and input into the first delay chain for calculation, and the corresponding output pulse is input into the high-order unit of the maximum value search and difference generation module; the high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and the target pulse of the output pulse is screened out and input into the low-order unit of the maximum value search and difference generation module; The low-order unit searches for a maximum value and generates a difference for the target pulse at the falling edge of the output pulse to obtain an exponent and a difference corresponding to the input floating-point number exponent.

[0066] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0067] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer can execute the steps of the in-memory calculation method of the floating-point exponent provided by the above methods, for example, including: The input floating-point exponent to be calculated and the weighted floating-point exponent are equally divided into high-order bits and low-order bits, and the high-order bits are converted into high-order thermometer codes and stored in the SRAM row, and the low-order bits are converted into low-order thermometer codes and stored in the SRAM row; One bit of the high-order thermometer code and the low-order thermometer code is respectively taken from the SRAM row and input into the first delay chain for calculation, and the corresponding output pulse is input into the high-order unit of the maximum value search and difference generation module; the high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and the target pulse of the output pulse is screened out and input into the low-order unit of the maximum value search and difference generation module; The low-order unit searches for a maximum value and generates a difference for the target pulse at the falling edge of the output pulse to obtain an exponent and a difference corresponding to the input floating-point number exponent.

[0068] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the in-memory calculation method of the floating-point exponent provided by the above methods, for example, including: The input floating-point exponent to be calculated and the weighted floating-point exponent are equally divided into high-order bits and low-order bits, and the high-order bits are converted into high-order thermometer codes and stored in the SRAM row, and the low-order bits are converted into low-order thermometer codes and stored in the SRAM row; One bit of the high-order thermometer code and the low-order thermometer code is respectively taken from the SRAM row and input into the first delay chain for calculation, and the corresponding output pulse is input into the high-order unit of the maximum value search and difference generation module; the high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and the target pulse of the output pulse is screened out and input into the low-order unit of the maximum value search and difference generation module; The low-order unit searches for a maximum value and generates a difference for the target pulse at the falling edge of the output pulse to obtain an exponent and a difference corresponding to the input floating-point number exponent.

[0069] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0070] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for calculating floating point exponents in memory, characterized in that: An in-memory calculation structure applied to a floating-point number exponent, the in-memory calculation structure of the floating-point number exponent comprises a static random access memory SRAM row, a first delay chain and a maximum value search and difference generation module, wherein the first delay chain is composed of N in-memory calculation units CIM connected in series; the in-memory calculation method of the floating-point number exponent comprises: The input floating-point exponent to be calculated and the weighted floating-point exponent are equally divided into high-order bits and low-order bits, and the high-order bits are converted into high-order thermometer codes and stored in the SRAM row, and the low-order bits are converted into low-order thermometer codes and stored in the SRAM row; One bit of the high-order thermometer code and the low-order thermometer code is respectively taken from the SRAM row and input into the first delay chain for calculation, and the corresponding output pulse is input into the high-order unit of the maximum value search and difference generation module; the high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and the target pulse of the output pulse is screened out and input into the low-order unit of the maximum value search and difference generation module; The low-order unit searches for a maximum value and generates a difference for the target pulse at a falling edge of the output pulse to obtain an exponent and a difference corresponding to the input floating-point number exponent.

2. The in-memory calculation method of floating point exponent according to claim 1, characterized in that: The in-memory computing unit CIM comprises a first-stage inverter, a second-stage inverter, a third-stage inverter and a fourth-stage inverter connected in series in sequence; The first-stage inverter includes a transistor PM2 and a transistor NM2 connected in parallel, the second-stage inverter includes a transistor PM3 and a transistor NM3 connected in parallel, the third-stage inverter includes a transistor PM6 and a transistor NM6 connected in parallel, and the fourth-stage inverter includes a transistor PM7 and a transistor NM7 connected in parallel; A transistor NM0 and a transistor NM1 are connected in parallel between the source end of the transistor NM2 and the ground end of the first-stage inverter, and a transistor PM0 and a transistor PM1 are connected in parallel between the source end of the transistor PM2 and the power supply; The gate terminal of the transistor NM0 is connected to a first bias voltage, the first bias voltage is used to perform exponential sum calculation on the high bits of the input floating-point number exponent, and the gate terminal of the transistor NM1 is connected to the value of the high bits of the input floating-point number exponent; the gate terminal of the transistor PM0 is connected to a second bias voltage, the second bias voltage is used to perform exponential sum calculation on the low bits of the input floating-point number exponent, and the transistor PM1 is connected to the value of the low bits of the input floating-point number exponent; A transistor NM4 and a transistor NM5 are connected in parallel between the source end of the transistor NM6 and the ground end of the three-stage inverter, and a transistor PM4 and a transistor PM5 are connected in parallel between the source end of the transistor PM6 and the power supply; The gate terminal of the transistor NM4 is connected to the first bias voltage, and the gate terminal of the NM5 is connected to the value of the high bit of the weighted floating point exponent; the gate terminal of the transistor PM4 is connected to the second bias voltage, and the transistor PM5 is connected to the value of the low bit of the weighted floating point exponent.

3. The in-memory calculation method of floating point exponent according to claim 2, characterized in that: The step of taking one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row and inputting them into the first delay chain for calculation comprises: Take one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row as the target thermometer code, and input the target thermometer code and the input pulse into the in-memory calculation unit in the first delay chain; In the in-memory calculation unit, when the rising edge of the input pulse signal arrives, the transistor NM2 and the transistor NM6 are turned on and generate a pull-down current, and start calculating the first exponential sum of the high-order bits of the input floating-point exponent and the high-order bits of the weighted floating-point exponent; The on-state of the transistor NM1 is controlled by the value of the high-order bit of the input floating-point exponent, and the on-state of the transistor NM5 is controlled by the value of the high-order bit of the weighted floating-point exponent.

4. The in-memory calculation method of floating point exponent according to claim 2, characterized in that: The step of taking one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row and inputting them into the first delay chain for calculation comprises: Take one bit of the high-order thermometer code and one bit of the low-order thermometer code from the SRAM row as the target thermometer code, and input the target thermometer code and the input pulse into the in-memory calculation unit in the first delay chain; In the in-memory calculation unit, when the falling edge of the input pulse arrives, the transistor PM2 and the transistor PM6 are turned on and charged and pulled up, and the second exponential sum of the low-order bits of the input floating-point exponent and the low-order bits of the weighted floating-point exponent is calculated; The on-state of the transistor PM1 is controlled by the value of the low-order bit of the input floating-point exponent, and the on-state of the transistor PM5 is controlled by the value of the low-order bit of the weighted floating-point exponent.

5. The in-memory calculation method of floating point exponent according to claim 1, characterized in that: The high-order unit of the maximum value search and difference generation module includes an inverter INV1, a NAND gate NAND1, an inverter INV2, a second delay chain, an AND gate AND, and a counter CNT1 connected in series in sequence; wherein the second delay chain is composed of a plurality of inverters connected in series; a first trigger is connected in parallel between the NAND gate NAND1 and the inverter INV2; The low-order unit of the maximum value search and difference generation module includes an inverter INV3, a NAND gate NAND2 and an inverter INV4 which are connected in series in sequence, the inverter INV4 is connected to the first branch and the second branch respectively, the first branch is connected in parallel with the second branch; a second trigger is connected in parallel between the NAND gate NAND2 and the inverter INV4; The first branch includes an OR gate OR, a NAND gate NAND3 and a third trigger connected in series in sequence; the second branch includes a third delay chain, an XNOR gate XNOR and a counter CNT2 connected in series in sequence; wherein the third delay chain is composed of a plurality of inverters connected in series.

6. The in-memory calculation method of floating point exponent according to claim 5, characterized in that: The high-order unit performs maximum value search and difference generation on the rising edge of the output pulse, and selects the target pulse of the output pulse and inputs it into the low-order unit of the maximum value search and difference generation module, including: When the rising edge of the output pulse arrives, the high-order unit determines the first pulse and the second pulse, as well as the first inverse pulse of the first pulse and the second inverse pulse of the second pulse according to the output pulse and the input pulse of each of the in-memory computing units CIM; the pulse width of the first pulse is the delay time between the rising edge of the output pulse and the input pulse, and the pulse width of the second pulse is the delay time between the falling edge of the output pulse and the input pulse; Inputting the first pulses corresponding to the N in-memory computing units CIM into the AND gate AND, screening out the first target pulse with the smallest pulse width and the first target anti-pulse corresponding to the first target pulse; Based on the first trigger, using the first anti-pulse to perform trigger sampling on the first target pulse to obtain a second target pulse; Using the AND gate AND, generating a first pulse width difference between the first pulse and the first target pulse, and inputting the first pulse width difference into the counter CNT1 to obtain a target difference between the first pulse and the first target pulse; According to the target difference, a third target pulse is selected from the second target pulse and input into the low-order unit of the maximum value search and difference generation module; the third target pulse is a pulse whose target difference corresponding to the second target pulse is greater than a preset value.

7. The in-memory calculation method of floating point exponent according to claim 6, characterized in that: The low-order unit searches for a maximum value and generates a difference for the target pulse at the falling edge of the output pulse to obtain an exponent and a difference corresponding to the input floating-point number exponent, including: When the falling edge of the output pulse arrives, the low-order unit selects a fourth target pulse with the largest low-order bit from the third target pulse; modulating a fifth target pulse to obtain a modulated pulse and a modulated inverse pulse of the modulated pulse; the fifth target pulse is a pulse in the third target pulse except the fourth target pulse; Selecting a target modulated pulse with the largest low-order bit from the modulated pulses, and based on the third trigger, using the modulated anti-pulse to perform trigger sampling on the target modulated pulse to obtain a sixth target pulse and a sixth target anti-pulse of the sixth target pulse; A second pulse width difference between the second pulse and the sixth target counter pulse is generated, and the second pulse width difference is input into the counter CNT2 to obtain an index and a difference value corresponding to the input index.

8. The in-memory calculation method of floating point exponent according to claim 7, characterized in that: After inputting the second pulse width difference into the counter CNT2 to obtain the index and the difference corresponding to the input index, the method further includes: Based on the second trigger, the target modulation pulse is triggered by the second anti-pulse to generate the numerical sign of the index and the difference.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: It also includes the in-memory calculation structure of the floating-point exponent as described in claim 8, and when the processor executes the program, the steps of the in-memory calculation method of the floating-point exponent as described in any one of claims 1 to 8 are implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the in-memory calculation method of floating-point exponents as described in any one of claims 1 to 8 are implemented.

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