Clock control circuit, clock switching method and electronic equipment

Abstract

The embodiment of the invention discloses a clock control circuit, a control method and electronic equipment, and relates to the field of power circuits. By integrating various clock sources (including internal low-speed, high-speed, external and PLL enhanced clocks) and the intelligent clock management module, the reliability of system clock signals is remarkably enhanced. The multi-source clock design provides redundant backups of the clock sources, so that the system can be quickly switched to a standby source when any clock source fails, and clock interruption is avoided. An intelligent clock selection and detection mechanism can monitor the state of a clock source in real time, and once an abnormality is found, the stable and reliable clock source is switched to immediately and automatically, so that the continuity and the stability of a system clock are ensured.

Description

Technical Field

[0001] The present invention relates to the field of power supplies, and in particular to a clock control circuit, a chip and an electronic device. Background Art

[0002] With the advancement and development of semiconductor technology, the reliability requirements for chips are becoming increasingly higher in chip applications, especially in industrial and automotive-grade environments. During chip operation, the clock system is the pulse of the entire chip and provides a stable trigger rhythm for each timing logic block in the chip. Its importance is as important as the human heart.

[0003] The clock network of the SOC chip generally chooses to use an external crystal oscillator directly or indirectly as the system clock. Once the external crystal oscillator causes the crystal oscillator clock to stop or become discontinuous due to some reason, the entire chip will hang, causing abnormal operation of peripherals and bringing devastating disasters to various applications. Summary of the invention

[0004] The clock control circuit, chip and electronic device provided in the embodiments of the present application can reduce power consumption and simplify the circuit structure. The technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a clock control circuit, including:

[0006] An internal low-speed clock circuit, an internal high-speed clock circuit, an external clock circuit, a first switch selector, a phase-locked loop clock circuit, a clock detection module, a first switch selector, a crystal oscillator, and a second switch selector;

[0007] Wherein, the output end of the low-speed internal clock circuit is connected to the first input end of the first switch selector, and the output end of the high-speed internal clock circuit is respectively connected to the second input end of the second switch selector, the first input end of the clock detection module, and the second input end of the first switch selector; the crystal oscillator is connected between the first input end and the second input end of the external clock circuit, and the output end of the external clock circuit is respectively connected to the first input end of the second switch selector, the second input end of the clock detection module, and the third input end of the first switch selector; the input end of the phase-locked loop clock circuit is connected to the output end of the second switch selector, and the output end of the phase-locked loop clock circuit is connected to the fourth input end of the first switch selector; the first control end of the clock detection module is connected to the control end of the first switch selector, and the second control end of the clock detection module is connected to the control end of the second switch selector; the output end of the first switch selector is connected to the system circuit;

[0008] The clock detection module is used to instruct the first switch selector to conduct between the third input terminal and the output terminal of the first switch selector when entering the normal working stage after successful power-on;

[0009] During the normal working stage, the external clock circuit is detected for abnormality. When an abnormality is detected in the external clock circuit, the second switch selector is instructed to conduct between the second input terminal and the output terminal, and the fourth input terminal and the output terminal of the first switch selector are instructed to conduct; or the first switch selector is instructed to conduct between the second input terminal and the output terminal.

[0010] In a second aspect, the present application provides an electronic device comprising the above-mentioned clock control circuit.

[0011] In a third aspect, the present application provides a clock switching method, which is applied to the above-mentioned clock control circuit, and the method includes:

[0012] When the clock detection module enters a normal working stage after being successfully powered on, it instructs the first switch selector to conduct between the third input terminal and the output terminal of the first switch selector;

[0013] The clock detection circuit performs abnormality detection on the external clock circuit during the normal working stage. When an abnormality is detected in the external clock circuit, the clock detection circuit instructs the second switch selector to conduct between the second input terminal and the output terminal, and instructs the first switch selector to conduct between the fourth input terminal and the output terminal; or instructs the first switch selector to conduct between the second input terminal and the output terminal.

[0014] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0015] By integrating multiple clock sources (including internal low-speed, high-speed, external and PLL enhanced clocks) and intelligent clock management modules, the reliability of the system clock signal is significantly enhanced. The multi-source clock design provides redundant backup of the clock source, ensuring that when any clock source fails, the system can quickly switch to the backup source to avoid clock interruption. The intelligent clock selection and detection mechanism can monitor the clock source status in real time. Once an abnormality is found, it will automatically switch to a stable and reliable clock source to ensure the continuity and stability of the system clock. In addition, this solution simplifies system design and maintenance, reduces dependence on external components, and improves the overall reliability and maintainability of the system. In short, this technical solution effectively improves the intelligence and reliability level of system clock management. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 is a structural diagram of a clock control circuit provided in an embodiment of the present application;

[0018] Figure 2 is a flow chart of a calibration method for a clock control circuit provided in an embodiment of the present application;

[0019] Figure 3 This is an abnormal waveform diagram of clock detection provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] See also Figure 1 The present invention provides a schematic diagram of the structure of a clock signal control circuit of an embodiment, including: an internal low-speed clock circuit LSI, an internal high-speed clock circuit HSI, an external clock circuit HSE, a crystal oscillator, a first switch selector SW1, a phase-locked loop clock circuit PLL, a clock detection module, and a second switch selector SW2. The internal low-speed clock circuit LSI is used to output an internal low-speed clock signal, and the internal high-speed clock signal is used to output an internal high-speed clock signal. Obviously, the frequency of the internal low-speed clock signal is lower than that of the internal high-speed clock signal. The external clock circuit HSE and the crystal oscillator OSC are used to output an external clock signal, and the phase-locked loop clock circuit PLL is used to output a phase-locked loop clock signal based on an input reference clock signal. The first switch selector SW1 is used to select one input end from four input ends to be connected to the output end, and the second switch selector SW2 is used to select one input end from two input ends to be connected to the output end.

[0022] The connection relationship of the above-mentioned units is as follows: the output end of the low-speed internal clock circuit LSI is connected to the first input end 1 of the first switch selector SW1, and the output end of the high-speed internal clock circuit HSI is respectively connected to the second input end 2 of the second switch selector SW2, the first input end of the clock detection module, and the second input end 2 of the first switch selector SW1. The crystal oscillator OSC is connected between the first input end and the second input end of the external clock circuit HSE, and the output end of the external clock circuit HSE is respectively connected to the first input end of the second switch selector SW2, the second input end of the clock detection module, and the third input end of the first switch selector SW1. The input end of the phase-locked loop clock circuit PLL is connected to the output end of the second switch selector SW2, and the output end of the phase-locked loop clock circuit PLL is connected to the fourth input end of the first switch selector SW1. The first control end of the clock detection module is connected to the control end of the first switch selector SW1, and the second control end of the clock detection module is connected to the control end of the second switch selector SW2. The output end of the first switch selector SW1 is connected to the system circuit.

[0023] The working process of the clock control circuit of the present application includes: in the power-on stage, the clock detection module sends a channel switching signal to the first switch selector SW1 to indicate that the first input terminal 1 and the output terminal of the first switch selector SW1 are connected, so that the internal low-speed clock signal generated by the internal low-speed clock circuit is used as the system clock signal and output to the system circuit. After successful power-on, it enters the normal working stage, and the clock detection module sends a channel switching signal to the first switch selector SW1 to indicate that the third input terminal 3 and the output terminal of the first switch selector SW1 are connected, so that the external clock signal generated by the external clock circuit is output to the system circuit as the system clock signal; or after successful power-on, the clock detection module indicates that the first input terminal and the output terminal of the second switch selector SW2 are connected, and indicates that the fourth input terminal 4 and the output terminal of the first switch selector are connected, so that the external clock signal generated by the external clock circuit is used as the reference clock signal of the phase-locked loop clock circuit PLL, and the phase-locked loop clock circuit PLL generates a phase-locked loop clock signal according to the reference clock signal, and outputs the phase-locked loop clock signal to the system circuit as the system clock signal. In the normal working stage, the clock detection module detects abnormalities in the external clock signal. When the external clock signal is detected to be abnormal, the clock detection module instructs the second switch selector SW2 to conduct between the second input terminal 2 and the output terminal, and instructs the fourth input terminal 4 of the first switch selector SW2 to conduct between the output terminal, so that the internal high-speed clock signal generated by the internal high-speed clock HSI is output to the reference terminal of the phase-locked loop clock circuit PLL, and the phase-locked loop clock circuit PLL uses the internal high-speed clock signal as a reference clock signal to generate a phase-locked loop clock signal, and outputs the generated phase-locked loop clock signal to the system circuit as a system clock signal. Or when the external clock signal is detected to be abnormal, the first switch selector SW1 is instructed to conduct between the second input terminal 2 and the output terminal, so that the internal high-speed clock signal generated by the internal high-speed clock circuit HSI will be output to the system circuit as a system clock signal.

[0024] In some embodiments of the present application, the channel switching signal sent by the clock detection module to the first switch selector SW1 and the second switch selector SW2 is represented by switch bit information, and the switch indication information includes multiple bits, and the number of bits is the same as the number of channels of the switch selector, that is, one bit corresponds to one channel, and when the value of the bit is high, it indicates that the corresponding channel is in the on state, otherwise the channel is in the off state, and only one bit value in the switch indication information is high at any time. For example: for the first switch selector SW1, the switch bit information is 4 bits, and when the switch bit information is 1000, it indicates that the first channel is controlled to be in the on state, that is, the first input terminal and the output terminal are controlled to be connected; when the switch bit information is 0100, it indicates that the second channel is controlled to be in the on state, that is, the second input terminal and the output terminal are controlled to be connected.

[0025] In some embodiments of the present application, the method for the clock detection module to detect anomalies in an external clock signal includes:

[0026] Configure the length of the current detection window according to the current frequency of the internal high-speed clock signal;

[0027] Calculating the number of ideal levels within the current detection window according to the clock frequency of the external clock circuit;

[0028] Counting the actual level number of the external clock circuit in the current detection window;

[0029] If the error between the actual level number and the ideal level number is not within a preset error range, it is determined that an abnormality occurs in the external clock circuit.

[0030] Among them, the clock detection module clearly knows the current frequency of the internal high-speed clock signal, and dynamically calculates or configures a suitable detection window length according to the frequency of the internal high-speed clock. The length of the detection window should be long enough to include enough external clock cycles for accurate statistics and comparison, but short enough to avoid excessive delay. The frequency of the external clock is obtained through the interface of the external clock circuit or a dedicated clock management module. Based on the frequency of the external clock and the length of the detection window, the number of levels that should theoretically appear in the window (usually the number of rising edges or falling edges, depending on the specific implementation) is calculated. For example, if the external clock frequency is 1MHz and the current detection window is 1ms, there should be 1000 level changes in theory (assuming it is a square wave signal). During the current detection window, the level changes of the external clock signal are monitored in real time by interrupts, polling or dedicated hardware counters. The number of level changes that actually occur in the detection window is recorded and counted. The percentage error between the actual level number and the ideal level number is calculated. Percentage error = (actual level number - ideal level number) / ideal level number × 100%. The calculated error is compared with the preset error range (for example: ±5%). If the error exceeds this range, it is considered that the external clock circuit is abnormal.

[0031] In an embodiment of the present application, a method for configuring the length of the detection window may be to calculate the current cycle according to the current frequency and use the length of 1000 cycles as the length of the current detection window.

[0032] In an embodiment of the present application, an internal low-speed clock circuit LSI, an internal high-speed clock circuit HSI, an external clock circuit HSE, a first switch selector SW1, a second switch selector SW2, a phase-locked loop clock circuit PLL and a clock detection module are arranged inside the chip, and a crystal oscillator OSC is arranged outside the chip.

[0033] Among them, integrating clock-related circuits and modules inside the chip can significantly reduce the number of external components, simplify circuit design, and improve the integration of the system. This helps to reduce the chip size, reduce manufacturing costs, and improve the overall reliability of the system. The external clock source is easily affected by environmental factors, such as electromagnetic interference, temperature changes, etc., which leads to fluctuations and instability of the clock signal. Integrating the clock circuit and module inside the chip can effectively reduce these external interferences and improve the stability and reliability of the clock signal. Through the internally set HSI, HSI and HSE clock sources, as well as the first switch selector SW1 and the second switch selector SW2, the system can select the most suitable clock source as needed. This flexibility helps to meet the requirements of different application scenarios for clock signals. The phase-locked loop clock circuit PLL can dynamically adjust the frequency and phase of the clock signal as needed to adapt to changes in system performance. This dynamic adjustment capability helps to optimize the operating efficiency and stability of the system. The external clock circuit HSE is usually able to provide a high-precision and stable clock signal, which is crucial to improving the system's computing speed and data processing capabilities. At the same time, the internal high-speed clock circuit HSI can also provide a backup clock signal when the HSE fails to ensure the continuous operation of the system. By monitoring and managing the clock signal in real time through the clock detection module, the system can automatically switch to low power mode in scenarios where high-precision clock signals are not required, thereby reducing the overall power consumption of the system. Integrating the clock circuit and module inside the chip can greatly simplify the hardware design of the system. Designers do not need to consider the selection and layout of external clock sources, but only need to focus on the clock management strategy inside the chip. When the system fails, since the clock circuit and module are integrated inside the chip, it is easier to troubleshoot and repair the fault. At the same time, since the number and complexity of external components are reduced, the difficulty and cost of system maintenance are also reduced.

[0034] See also Figure 2 As shown, it is a flow chart of the clock switching method provided in an embodiment of the present application, including:

[0035] S201 . When the clock detection module enters a normal working stage after being successfully powered on, it instructs the first switch selector to conduct between the third input terminal and the output terminal of the first switch selector.

[0036] S202. During the normal working stage, an abnormality detection is performed on the external clock circuit. When an abnormality is detected in the external clock circuit, the second switch selector is instructed to conduct between the second input terminal and the output terminal, and the fourth input terminal and the output terminal of the first switch selector are instructed to conduct; or the first switch selector is instructed to conduct between the second input terminal and the output terminal.

[0037] in, Figure 2 Method embodiments and Figure 1 The structural embodiments are based on the same concept, and the technical effects they bring are also the same. The specific process can be referred to Figure 1 The embodiments of the present invention will not be described in detail here.

[0038] See also Figure 3 As shown, Figure 3 The abnormal waveform diagram of the clock detection provided in the embodiment of the present application mainly includes initialization, sampling, comparison and reset. During the initialization phase, the HSI clock frequency of the current chip will be adaptively adapted and latched, and then the sampling phase will be entered. The sampling count will be performed according to the configured window length under the HSE clock. After completion, the comparison phase will be entered. By comparing with the latch in the initialization phase, it is determined whether the clock is abnormal. When the clock is abnormal, the abnormal flag is set high; finally, the asynchronous reset phase will be entered to prepare for the initialization of the next cycle sliding detection.

[0039] The ADC real-time calibration circuit in the present application has the following technical effects.

[0040] The solution has designed a variety of clock sources, including internal low-speed and high-speed clock circuits as basic backup, a stable clock source provided by an external crystal oscillator, and a clock signal enhanced by a phase-locked loop (PLL). This multi-source design ensures that when any single clock source fails, the system can quickly switch to other available clock sources, thereby avoiding system paralysis due to clock signal interruption.

[0041] By introducing the first and second switch selectors, as well as the clock detection module, the intelligent selection and dynamic switching of the clock source are realized. The clock detection module can monitor the status of the external clock circuit in real time. Once an abnormality (such as signal loss, frequency deviation, etc.) is detected, it will immediately instruct the selector to switch to other reliable clock sources. This instant response capability greatly improves the system's ability to cope with clock anomalies.

[0042] In normal operation, the external clock circuit is used as the main clock source by default, because it usually provides higher accuracy and stability. However, when there is a problem with the external clock source, the system can seamlessly switch to the internal high-speed clock or the clock enhanced by the PLL to ensure the continuity and stability of the system clock and avoid system performance degradation or data errors caused by clock signal problems.

[0043] The multi-clock source design and intelligent switching mechanism provide the system with higher redundancy and fault tolerance. Even in harsh working environments, such as power fluctuations, electromagnetic interference, etc., the system can maintain normal operation by automatically selecting the most reliable clock source, enhancing the overall reliability and stability of the system.

[0044] The integrated clock management solution reduces the reliance on external components and simplifies the complexity of system design. At the same time, the intelligent clock detection and switching mechanism also reduces the difficulty of system maintenance and improves the maintainability and scalability of the system.

[0045] In summary, this technical solution significantly improves the reliability of system clock signal input through multi-source clock backup, intelligent clock switching and enhanced system stability design, providing a strong guarantee for the stable operation of the system.

[0046] The electronic device provided in the embodiments of the present application includes but is not limited to communication equipment, terminal equipment, computer equipment, etc. In addition to the above-mentioned clock control circuit, the electronic device may also include: a housing for accommodating various components, a display screen and an input device (for example: a keyboard, a mouse or a touch screen), etc.

[0047] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A clock control circuit, characterized in that: include: An internal low-speed clock circuit, an internal high-speed clock circuit, an external clock circuit, a first switch selector, a phase-locked loop clock circuit, a clock detection module, a first switch selector, a crystal oscillator, and a second switch selector; Wherein, the output end of the low-speed internal clock circuit is connected to the first input end of the first switch selector, and the output end of the high-speed internal clock circuit is respectively connected to the second input end of the second switch selector, the first input end of the clock detection module, and the second input end of the first switch selector; the crystal oscillator is connected between the first input end and the second input end of the external clock circuit, and the output end of the external clock circuit is respectively connected to the first input end of the second switch selector, the second input end of the clock detection module, and the third input end of the first switch selector; the input end of the phase-locked loop clock circuit is connected to the output end of the second switch selector, and the output end of the phase-locked loop clock circuit is connected to the fourth input end of the first switch selector; the first control end of the clock detection module is connected to the control end of the first switch selector, and the second control end of the clock detection module is connected to the control end of the second switch selector; the output end of the first switch selector is connected to the system circuit; The clock detection module is used to instruct the first switch selector to conduct between the third input terminal and the output terminal of the first switch selector when entering the normal working stage after successful power-on; During the normal working stage, the external clock circuit is detected for abnormality. When an abnormality is detected in the external clock circuit, the second switch selector is instructed to conduct between the second input terminal and the output terminal, and the fourth input terminal and the output terminal of the first switch selector are instructed to conduct; or the first switch selector is instructed to conduct between the second input terminal and the output terminal.

2. The circuit according to claim 1, characterized in that The performing abnormality detection on the external clock circuit includes: Configure the length of the current detection window according to the current frequency of the internal high-speed clock signal; Calculating the number of ideal levels within the current detection window according to the clock frequency of the external clock circuit; Counting the actual level number of the external clock circuit in the current detection window; If the error between the actual level number and the ideal level number is not within a preset error range, it is determined that an abnormality occurs in the external clock circuit.

3. The circuit according to claim 2, characterized in that The length of the current detection window is equal to 1000 times the reciprocal of the current frequency.

4. The circuit according to claim 1, 2 or 3, characterized in that: The clock detection module is also used for: When power-on is detected, the first switch selector is instructed to conduct between the first input terminal and the output terminal.

5. The circuit according to claim 4, characterized in that The clock detection module controls the first switch selector or the second switch selector through switch bit information, the number of bits of the switch bit information is equal to the number of channels of the switch selector, each bit corresponds to a channel, and when the bit is at a high level, the corresponding channel is in an on state, and when the bit is at a low level, the corresponding channel is in an off state.

6. The circuit according to claim 1 or 2 or 3 or 5, characterized in that: The internal low-speed clock circuit, the internal high-speed clock circuit, the external clock circuit, the first switch selector, the phase-locked loop clock circuit, the clock detection module, the first switch selector, and the second switch selector are arranged inside the chip, and the crystal oscillator is arranged outside the chip.

7. A clock switching method, characterized in that: A clock control circuit as claimed in any one of claims 1 to 5; Wherein, the method comprises: When the clock detection module enters a normal working stage after being successfully powered on, it instructs the first switch selector to conduct between the third input terminal and the output terminal of the first switch selector; The clock detection circuit performs abnormality detection on the external clock circuit during the normal working stage. When an abnormality is detected in the external clock circuit, the clock detection circuit instructs the second switch selector to conduct between the second input terminal and the output terminal, and instructs the first switch selector to conduct between the fourth input terminal and the output terminal; or instructs the first switch selector to conduct between the second input terminal and the output terminal.

8. An electronic device, characterized in that: A clock control circuit comprising any one of claims 1 to 6.

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