Simulation method and device of chip system and related equipment

Abstract

The embodiment of the invention provides a simulation method and device of a chip system and related equipment, and the method comprises the steps: obtaining the connection data of the chip system; the connection data comprises physical connection data, and the physical connection data is formed based on physical connection relations among chips in the chip system; extracting a power supply network simulation node of the chip system from the physical connection data, and constructing a power supply network structure of the chip system based on the extracted power supply network simulation node; and simulating the chip system based on the power network structure. According to the technical scheme provided by the embodiment of the invention, the reliability of a voltage drop electromigration simulation result can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a simulation method, device and related equipment for a chip system. Background Art

[0002] As the design integration of chip systems increases, wire resistance becomes more dominant, increasing the problems of electromigration and voltage drop, which play an important role in shortening the life of electronic devices. By performing voltage drop electromigration simulation on chip systems, the voltage drop electromigration simulation results can predict and analyze these problems, so as to take corresponding design measures to improve the circuit reliability of chip systems. Therefore, in this context, how to provide a technical solution to improve the reliability of voltage drop electromigration simulation results has become a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a simulation method, device and related equipment of a chip system to improve the reliability of voltage drop electromigration simulation results.

[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0005] In a first aspect, an embodiment of the present invention provides a simulation method for a chip system, comprising:

[0006] Acquire connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system;

[0007] Extracting power network simulation nodes of the chip system from the physical connection data, and constructing a power network structure of the chip system based on the extracted power network simulation nodes;

[0008] A voltage drop electromigration simulation is performed on the chip system based on the power supply network structure.

[0009] In a second aspect, an embodiment of the present invention provides a simulation device for a chip system, comprising:

[0010] A data acquisition module, used to acquire connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system;

[0011] A power network structure construction module, used to extract power network simulation nodes of the chip system from the physical connection data, and to construct a power network structure of the chip system based on the extracted power network simulation nodes;

[0012] A simulation module is used to perform voltage drop electromigration simulation on the chip system based on the power network structure.

[0013] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the simulation method of the chip system as described in the first aspect.

[0014] In a fourth aspect, an embodiment of the present invention provides a storage medium, wherein the storage medium stores a program, and when the program is executed, the simulation method of the chip system as described in the first aspect is implemented.

[0015] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements the simulation method of the chip system as described in the first aspect.

[0016] A simulation method for a chip system provided by an embodiment of the present invention includes: obtaining connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system; extracting the power network simulation nodes of the chip system from the physical connection data, and constructing the power network structure of the chip system based on the extracted power network simulation nodes; and performing voltage drop electromigration simulation on the chip system based on the power network structure.

[0017] It can be seen that according to the technical solution provided by the embodiment of the present invention, when performing voltage drop and electromigration simulation of a chip system, the connection data of the chip system includes: physical connection data formed based on the physical connection relationship between each chip in the chip system; therefore, when extracting the power network simulation node based on the physical connection data, the power network simulation node can reflect the physical connection relationship between each chip; and then the power network structure constructed based on the extracted power network simulation node can be close to the power network distribution in the real physical structure of the chip system, so that when simulating based on the power network structure, the obtained simulation result can more reliably reflect the power network distribution of the chip system, which is convenient for adjusting the power network distribution of the chip system and extending the service life of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0019] Figure 1is a schematic diagram of a flow chart of a simulation method of a chip system provided by an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of a chip system formed by multiple chips provided in an embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of an implementation process of isolating chips from each other to build a power supply network structure for chip system simulation provided by an embodiment of the present invention;

[0022] Figure 4 yes Figure 3 The flowchart corresponding to the implementation process shown;

[0023] Figure 5 is another schematic flow chart of the simulation method of the chip system provided by an embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of a chip and a connection structure between chips provided by an embodiment of the present invention;

[0025] Figure 7 yes Figure 6 A schematic diagram of the connection structure in the structure shown;

[0026] Figure 8 It is a schematic diagram of an implementation process of obtaining connection data in the simulation method of the chip system provided by an embodiment of the present invention;

[0027] Fig. 9 It is a structural schematic diagram of a simulation device for a chip system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The use of 2.5D / 3D integrated circuit packaging technology has revitalized the microchip industry, especially in high-end areas such as central processing units (CPUs), graphics processing units (GPUs) and system on chip (SoCs), avoiding the problem of diminishing returns brought about by advances in ultra-deep submicron process nodes.

[0030] However, with the continuous development of process nodes, the packaging technology of integrated circuits is becoming more and more complex. As an important item in chip sign-off, the solution of voltage drop electromigration joint simulation between multiple chips (dies) is particularly important.

[0031] The current voltage drop electromigration simulation solution can support the joint simulation of 2.5D chip systems. For the connection structure: TSV (Through-Silicon Via) and RLC (Resistance Inductance Capacitance) parameters of micro-bumps are directly provided by the process factory and packaging factory. Among them, the connection structure is the structure used to connect each chip when the chips are combined in a stacking layer specified according to the design requirements of the chip system.

[0032] The simulation tool (voltage drop electromigration simulation tool) extracts the power network nodes of each die separately. When the connection structure cannot be seen, the simulation tool connects the RLC circuit model nodes of the connection components such as mbump to the metal connection lines of the corresponding chip, and builds a circuit path from the solder bump at the package level to the power network nodes of all chips to obtain the power network structure of the chip system. This allows the next step of multi-chip (multi-die) joint simulation analysis. Such simulation is crucial for optimizing the power integrity (PI) and signal integrity (SI) of the chip system.

[0033] However, in the above scheme, when constructing the power network structure of the chip system, the dies in the chip system are isolated from each other, and the power network nodes of each die are extracted independently. It is impossible to use the connection structure between the chips, and thus it is impossible to consider the connection nodes generated by the coupling according to the connection structure, and to consider the corresponding RLC and other circuit structures generated by the coupling. As a result, when the chip system performs voltage drop and electromigration simulation, the power network structure cannot accurately reflect the actual power network distribution of the chip system, affecting the authenticity and reliability of the voltage drop and electromigration simulation results.

[0034] To solve the above problems, an embodiment of the present invention provides a simulation method for a chip system to improve the reliability of voltage drop electromigration simulation results.

[0035] Please refer to Figure 1 , Figure 1 It is a flow chart of a simulation method of a chip system provided by an embodiment of the present invention.

[0036] like Figure 1 As shown, the method comprises the following steps:

[0037] Step S101, obtaining connection data of a chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system.

[0038] The connection data is data that reflects the connection relationship of the chip system, and in addition to the physical connection data, it may also include logical connection data. The logical connection data may refer to the electrical connection relationship between various logic gates or circuit elements in the circuit of the chip system. The logical connection data defines the path of the current, including how the current flows through various logic gates and circuit elements, and the interaction between them.

[0039] The physical connection data is formed based on the physical connection relationship of the chip system, and thus can reflect the physical implementation form of the chip system. That is, the physical connection relationship corresponds to the physical implementation form of the chip system, and thus the physical connection relationship can refer to the combined connection relationship of each chip in the chip system. The physical connection data can be regarded as data describing the three-dimensional structure of the chip system on a two-dimensional plane.

[0040] Step S102 , extracting power network simulation nodes of the chip system from the physical connection data, and constructing a power network structure of the chip system based on the extracted power network simulation nodes.

[0041] Since the physical connection data is formed based on the physical connection relationship, it can reflect the combined connection relationship of each chip in the chip system. Therefore, when the power network simulation nodes are extracted based on the physical connection data, each node in the complete power network structure of the chip system can be reflected. At the same time, the circuit nodes and RLC circuit parameters generated by the coupling of the connection structure (connection) between chips can be considered, and finally an accurate power network structure of the chip system can be obtained.

[0042] Step S103 , performing voltage drop electromigration simulation on the chip system based on the power network structure.

[0043] After extracting the power network simulation nodes, the coupled parasitics can be considered according to the process file, and the RLC parasitic parameter circuit of the power network of the chip system can be extracted. Each power network simulation node can be connected to the connection position of the resistance, inductance and capacitance model formed by the RLC parasitic parameter circuit of the power network to form the power network structure of the chip system.

[0044] The power network structure formed in the embodiment of the present invention can take into account the circuit structure such as RLC generated by the coupling of the connection structure. It is ensured that the constructed power network structure can more accurately reflect the path impedance effect when performing voltage drop electromigration simulation, obtain a more accurate power network distribution (such as current distribution and direction), and improve the reliability of the voltage drop electromigration simulation results.

[0045] To further illustrate that the simulation method of the chip system provided by the embodiment of the present invention can improve the reliability of the voltage drop electromigration simulation result, the commonly used voltage drop electromigration simulation scheme is used as a comparative example for illustration below.

[0046] Please refer to Figure 2 and Figure 3 , Figure 2 is a schematic diagram of a chip system formed by multiple chips according to an embodiment of the present invention. Figure 3 It is a schematic diagram of an implementation process of isolating chips from each other to construct a power supply network structure for chip system simulation provided by an embodiment of the present invention.

[0047] like Figure 2 As shown in the figure, the chip system formed by multiple dies mainly includes the following parts:

[0048] si_interposer (silicon interposer), including the bottom bare chip (Interposer Bottom Die, ibotdie);

[0049] memory die (storage chip), including instruction memory (IMEM);

[0050] asic die: general purpose (GENERIC) chip, including specific types of application-specific integrated circuit chips (Application-Specific Integrated Circuit, ASIC);

[0051] Among them, the memory die and the asic die are connected through: AP layer (Access Point, interconnection layer) -> mbump -> AP layer -> wiring layer -> TSV -> BMET layer (Bottom Metal Layer, bottom metal layer) connected to the bump -> bump structure and si_interposer to achieve 2.5D interconnection. The memory die, asic die and si_interposer can be formed by different processes.

[0052] For Figure 2 The structure of the chip system shown in FIG. 1 is used in the voltage drop electromigration simulation. Figure 3 As shown:

[0053] Form the power network nodes of the memory die;

[0054] Form the power network nodes of ASIC die;

[0055] Construct an RLC circuit model of the connection structure.

[0056] Then, the power network nodes of the memory die and the power network nodes of the asic die are connected to the RLC model to form the power network structure of the chip system.

[0057] The process of building a chip system power network structure based on the power network nodes of each chip can be referred to Figure 4 , Figure 4 yes Figure 3 The flowchart corresponding to the implementation process shown in FIG.

[0058] like Figure 4 As shown, the process includes:

[0059] 1.1. Obtain the DEF file or chip power consumption model of each chip.

[0060] The DEF (Design Exchange Format) file of the chip contains the TSV pattern location and the pattern location information of mbump and bump.

[0061] The chip power consumption model is a full-chip power-ground network model with spice (simulation program with integrated circuit emphasis) accuracy. It simulates the entire power distribution network of the port at the chip power supply point, accurately reflects the instantaneous power consumption distribution of a chip and the RC network structure of the entire chip. Therefore, using the chip power consumption model as input is helpful for voltage drop and electromigration simulation analysis.

[0062] 1.2. Get the power ground or signal bump coordinate information.

[0063] The coordinate information of the bump can be obtained from the design file and data manual, or it can be obtained from the GDS (Graphic Data System, standard format) file, which is used to store and transmit IC layout information, including the location and layer information of the bump.

[0064] 2. Create virtual position alignment for multiple chips and relative coverage areas through chip-to-chip relative coordinates.

[0065] 3. Obtain the RLC parameter information of the mbump of the connection components between the package and the chip.

[0066] 4. Extract the PG node for each chip to form the power network node of each chip.

[0067] The power grid nodes are modeled and parameters are extracted to obtain the power grid nodes of each chip.

[0068] 5. Connect the PG node of each chip to the corresponding position of the RLC model to form the power network structure of the chip system.

[0069] The RLC model is a resistance, inductance and capacitance model formed by RLC parameters, which realizes the connection of the PG nodes of each chip.

[0070] 6. Perform voltage drop and electromigration simulation on the power network structure of the chip system.

[0071] It can be seen that in Figure 4 In the process shown, when creating a complete power network structure in step 5, the dies are isolated from each other to extract the single-die power network nodes. It is not possible to consider the nodes generated by the coupling based on the physical structure of the connection between the chips, and the RLC parameters generated by the coupling.

[0072] and Figure 4 The process shown requires that each die corresponding to the fab (fabrication, a semiconductor product manufacturing plant) provide a fixed format process file that can be read by the simulation tool, and each die corresponding to the fab provides a fixed format process file that can be read by the parasitic parameter extraction tool.

[0073] On the other hand, since backside power supply technology involves transferring the power supply network to the back side of the chip system, it is necessary to add a metal layer on the back side of the wafer and to process the ability of nano-silicon vias that electrically connect the back side of the device wafer to the front side. This backside power supply technology requires a dedicated wafer thinning process and complex physical and electrical simulation and design, which may be beyond the capabilities of traditional voltage drop electromigration simulation tools and therefore cannot support the simulation requirements of backside power supply design.

[0074] In the simulation method of the chip system provided in an embodiment of the present invention, the physical connection data in the connection data of the chip system can be formed based on the physical connection relationship between the chips in the chip system, that is, the connection data of the chip system can be the connection data of the chip system designed with back power supply.

[0075] Therefore, even if the chip system is formed by a back power supply design, physical connection data can be formed based on the physical connection relationship of the chip system generated by the back power supply design. Therefore, the embodiment of the present invention can support the voltage drop electromigration simulation of the chip system obtained by the back power supply design.

[0076] It can be seen that according to the technical solution provided by the embodiment of the present invention, when performing voltage drop and electromigration simulation of a chip system, the connection data of the chip system includes: physical connection data formed based on the physical connection relationship between each chip in the chip system; therefore, when extracting power network simulation nodes based on the physical connection data, the power network simulation nodes can reflect the nodes of the physical connection relationship between each chip; and then the power network structure constructed based on the extracted power network simulation nodes can be close to the power network distribution in the real physical structure of the chip system, so that when simulating based on the power network structure, the obtained simulation results can more reliably reflect the power network distribution of the chip system, which is convenient for adjusting the power network distribution of the chip system and extending the service life of the chip system.

[0077] In order to form accurate and reliable physical connection data, in one implementation, the physical connection data may be formed by referring to the combined connection relationship of each chip in a real chip system.

[0078] Please refer to Figure 5 , Figure 5 It is another flowchart diagram of the simulation method of the chip system provided by an embodiment of the present invention.

[0079] like Figure 5 As shown, the method may also include:

[0080] Step S200, redefine the names of the chips in the chip system and the submodules constituting the chips, thereby obtaining the renaming of the chips and the submodules; and redefine the names of the connection structures connecting the chips, thereby obtaining the renaming of the connection structures.

[0081] The names of the chips and the submodules constituting the chips are redefined so that different chips and submodules have different names.

[0082] The stacking level is a level formed after each chip in the chip system is arranged at a corresponding hierarchical position according to the design requirements of the chip system.

[0083] To illustrate the connection structure and the hierarchical position of each chip, please refer to Figure 6 and Figure 7 , Figure 6 is a schematic diagram of a chip and a connection structure between chips provided in an embodiment of the present invention, Figure 7 yes Figure 6 Schematic diagram of the connection structure in the shown structure.

[0084] For ease of explanation, Figure 6 A hybrid bonding 3DIC stacking structure design is shown as an example.

[0085] like Figure 6 As shown, the structure of the chip system in the figure includes a lower chip (main die) located at a lower hierarchical position, an upper chip (top die) connected to the lower chip and correspondingly located at an upper hierarchical position, and a connection structure (connection) connecting the two chips in the middle.

[0086] Among them, the connection structure mainly refers to: through silicon via (TSV) -> HBM layer (Hybrid Bonding Metal layer) -> HBV hole (Hybrid Bonding Via).

[0087] HBV holes are holes that connect the HBM layer to the metal layer of the top die. TSV is connected to the HBV hole through the HBM layer. TSV will make contact with the high-level metal side of the main die, such as Figure 6 In the TSV landing layer, a thick metal layer above the redistribution layer (RDL) on the chip is usually selected as the TSV landing layer.

[0088] like Figure 7 As shown, the upper and lower metal layers and hole connection relationship of the bonding plane (Hybrid Bonding interface) of a hybrid bonding stacking structure are shown.

[0089] TSV is connected to HBV through HBM to achieve interconnection between the upper chip and the lower chip.

[0090] Step S201 , sorting the renamed chips, sub-modules of the chips, and connection structures in the vertical direction of the stacking level of the chip system to form a physical connection relationship of the chip system.

[0091] The simulation input file can be Figure 4 The various files used in the flowchart shown in the figure, however, since the connection data in the embodiment of the present invention needs to include physical connection data. Therefore, in order to obtain accurate physical connection data, the names of the chip and its submodules and the names of the connection structures in the simulation input file are modified and replaced to obtain an updated simulation input file, so that the simulation input files of different chips have obvious differences, which is convenient for the simulation device to recognize, and then the connection data including accurate physical connection data is obtained according to the updated simulation input file.

[0092] In the process of re-establishing the physical connection relationship, all relevant process metal layers (including metal layers in the chip and metal layers in the connection structure) and hole layers can be renamed and sorted according to the stacking level of the chip system (3D-IC). In order to facilitate the distinction of the definition of metal layers in different dies, the names of the metal layers included can be named according to the name of the die, or they can be named according to the interconnection relationship between chips (for example, according to the stacking relationship from bottom to top). Different dies can be of different processes or the same process, and ultimately ensure that the names of all layer layers are not repeated.

[0093] For example, the names of each chip and its submodules and connection structures are named according to the interconnection relationship between dies, as shown in the following table:

[0094] Original process metal layer naming Rename metal1 itop_m1 HBM iconn_HBM M1 m1

[0095] In the above table, "itop" indicates the renaming of the upper chip located at the upper hierarchical position, "iconn_HBM" indicates the renaming of the HBM layer in the connection structure, and "m1" may indicate the renaming of the lower chip.

[0096] Since it is only necessary to distinguish the chips and the connection structures, when the renaming of the upper-layer chip is updated, the renaming of the lower-layer chip can also remain unchanged, that is, still be the original name.

[0097] After redefining the names of each chip and its submodules and connection structures in the chip system, in the vertical direction of the stacking level of the chip system, starting from the bottom metal layer of the imain die below, the connection structures are described layer by layer. "iconn_TSV, iconn_HBM and iconn_HBV" represent the metal and holes in the middle connection part. The final physical connection relationship is as follows:

[0098] itop_m1

[0099] itop_v1

[0100] itop_m2

[0101] itop_v2

[0102] itop_m3

[0103] itop_v3

[0104] itop_m4

[0105] itop_v4

[0106] itop_ap

[0107] iconn_HBV

[0108] iconn_HBM

[0109] iconn_TSV

[0110] m1

[0111] v1

[0112] m2

[0113] v2

[0114] m3

[0115] v3

[0116] m4

[0117] v4

[0118] ap.

[0119] Among them, "itop_m1" indicates the first metal layer of the upper chip, "itop_v1" indicates the first connection hole of the upper chip, and so on. The one with the "i_top" logo indicates that it is a submodule of the upper chip, and the number indicates how many layers the upper chip has. The above is shown as an example of an upper chip with 4 metal layers.

[0120] Similarly, "mi (i = 1, 2, 3, 4)" represents the layer number of the lower chip.

[0121] In the above representation, updating the names of the upper chip and its submodules while keeping the names of the lower chip and its submodules unchanged is used as an example for explanation.

[0122] The renaming of each chip and its sub-modules and connection structure in the physical connection relationship serves as the basis for the subsequent updating of each simulation input file, so that each chip and connection structure can be clearly distinguished in each modified simulation input file, which is convenient for reflecting the physical connection relationship of the chip system and facilitating the simulation tool to identify chips of different levels and the connection structures connecting each chip.

[0123] Please continue to refer to Figure 5 , the method further comprises:

[0124] Step S202: based on the renaming of each chip and the submodules of each chip in the physical connection relationship, and the renaming of the connection structure, the simulation input file of the chip system is updated.

[0125] According to the aforementioned Figure 4The simulation input files used in the process shown in the figure show that the simulation input files include different types, and different types of simulation input files also contain different information. Therefore, the specific input simulation file can be updated according to the specific type.

[0126] Step S203, obtaining connection data of the chip system based on the updated simulation input file.

[0127] The updated simulation input file can clearly distinguish chips at different levels and connection structures, which facilitates the detailed description of the physical connection relationship and thus forms accurate physical connection data.

[0128] In one embodiment, the simulation input file is a set of files including circuit design, process parameters, device characteristics and working conditions; step S202 may include:

[0129] Based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the first simulation input file containing the circuit design to obtain an updated first simulation input file;

[0130] Based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the second simulation input file containing device characteristics and working conditions to obtain an updated second simulation input file;

[0131] And, based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, the third simulation input file containing the process parameters is updated to obtain an updated third simulation input file.

[0132] Since the simulation input file is a group of files, when performing voltage drop and electromigration simulation of a chip system, the input files include multiple files, and this group of files contains circuit design, process parameters, device characteristics and working conditions, so that each file together provides the simulation tool with the necessary data to predict and analyze the voltage drop and electromigration problems of the power network structure of the chip system under actual working conditions.

[0133] Step S203 may include:

[0134] Based on the updated first simulation input file, the updated second simulation input file, and the updated third simulation input file, connection data of the chip system is acquired.

[0135] The updated simulation input files can reflect the connection structure of each chip in the chip system and between chips, so that the formed connection data can fully reflect the complete power network structure of the chip system, make the power network structure close to the actual physical structure of the chip system, and improve the reliability and authenticity of the voltage drop electromigration simulation analysis.

[0136] Step S204, based on the renaming of each chip and the sub-modules of each chip and the connection structure in the updated simulation input file, determine the internal data describing the physical connection relationship of each chip and the connection structure data describing the physical connection relationship between chips in the physical connection data.

[0137] The simulation input file is updated based on the renaming of each chip and the sub-modules of each chip in the physical connection relationship, as well as the renaming of the connection structure. Therefore, in the updated simulation input file, each chip in the chip system and the connection structure between chips can be clearly distinguished, so that the internal data of each chip and the connection structure data can be determined based on the physical connection data obtained based on the updated simulation input file.

[0138] Step S205 , abstractly generating an internal simulation node of each chip according to the internal data, and abstractly generating a simulation node of a connection structure for connecting chips according to the connection structure data.

[0139] The internal data is used to form each simulation node inside the chip, and the connection structure data is used to form the simulation node of the connection structure. Since the simulation node is finally connected with the resistance, inductance and capacitance model to form the final power network structure. Therefore, in the embodiment of the present invention, in the process of connecting to the resistance, inductance and capacitance model, the connection structure simulation node of the connection structure is taken into account, so that when constructing the power network structure, the RLC generated by the connection structure coupling can be considered to ensure that the power network structure finally established fits the actual physical structure of the chip system.

[0140] Step S206 , forming a power supply network simulation node of the chip system based on the generated internal simulation nodes of each chip and the simulation nodes of the connection structure.

[0141] Both the internal simulation nodes and the simulation nodes of the connection structure are used to form a power network structure, and therefore are collectively referred to as power network simulation nodes of the chip system.

[0142] In one implementation, step S205 may include:

[0143] Based on the data of the metal layer describing the connection structure and the data of the relative position relationship of the connection holes connecting the metal layers in the connection structure data, a connection structure simulation node is abstractly generated.

[0144] based on Figure 6 As can be seen from the structure shown, the connection structure mainly refers to: through silicon via -> HBM layer -> HBV hole; therefore, the connection structure data describing the connection structure includes data describing the metal layer (ie, HBM layer), data describing the connection holes (ie, through silicon via and HBV hole), and data on the relative position relationship of the connection holes, so that the connection structure simulation nodes can be accurately abstracted and generated.

[0145] Step S207, adding the internal simulation nodes of the chip and the simulation nodes of the connection structure to the corresponding connection positions in the resistance, inductance and capacitance model of the chip system to construct the power network structure of the chip system.

[0146] The RL model is used to describe and simulate the circuit connection between the internal simulation nodes of the chip and the simulation nodes of the connection structure.

[0147] After obtaining the internal simulation nodes of the chip and the simulation nodes of the connection structure, the resistance, inductance and capacitance model can be used to describe and simulate the circuit connection between these nodes. That is, each connection position of the resistance, inductance and capacitance model will have its corresponding resistance, inductance and capacitance values, which will affect the performance of the circuit, such as signal transmission delay, power integrity and electromagnetic compatibility.

[0148] Therefore, after completing the connection of the corresponding positions in the resistance, inductance and capacitance model based on the internal simulation nodes and the simulation nodes of the connection structure, the power supply network structure of the chip system obtained can approximately express the real power supply network of the chip system.

[0149] Step S208 , performing voltage drop electromigration simulation on the chip system based on the power network structure.

[0150] To facilitate the updating of simulation input files containing different contents, in one embodiment, the first simulation input file is a design file; the design file is a design exchange format file, and the design exchange format file contains a circuit design, which is used to describe the layout, circuit and physical information of the chip system;

[0151] The renaming of each chip and the submodule of each chip in the physical connection relationship and the renaming of the connection structure, updating the first simulation input file containing the circuit design, and obtaining the updated first simulation input file, comprises:

[0152] Based on the renaming of each chip and each chip's sub-module, the name of each chip and each chip's sub-module in the design exchange format file is updated; and based on the renaming of the connection structure, the name of the connection structure in the design exchange format file is updated to obtain an updated design exchange format file.

[0153] The design exchange format file is an ASCII file that describes the actual design of the chip system. It lists the library units and their locations and connections. The design exchange format file is used to transfer the design between different design systems while keeping the design content unchanged. The design exchange format file is different from GDSII, which only transfers geometric information. It can pass the logical information and physical information of the design to the layout and routing tool. The logical information includes the logical connection relationship (represented by the netlist), grouping information, and physical constraints. The physical information includes layout planning, layout location and direction, and routing geometry data.

[0154] Library cells refer to predefined circuit modules used in integrated circuit design, which are usually used in automatic placement and routing (P&R) tools. Library cells can be standard cells, such as logic gates, triggers, etc., or larger modules, such as memory blocks, processor cores, and other hard macros.

[0155] The physical connection relationship includes the renaming of each chip and its submodules and connection structures within the chip system; that is, the physical connection relationship is redefined according to the stacking level of the chip system, for chips at different levels, submodules in chips at different levels, metal layers in the metal structure connecting chips at different levels, and through holes. Thus, the physical connection relationship of the chip system (i.e., the combined connection relationship of each chip) can be reflected through renaming. The stacking level of the chip system can be regarded as: the structural level reflected in the vertical direction of the actual structure of the chip system. Therefore, the embodiment of the present invention can reflect the three-dimensional structure of the chip system on a two-dimensional plane (a plane formed in the vertical direction) by renaming.

[0156] Since the actual physical structure of the chip system is reflected in the design exchange format file, it includes the name definitions of each chip of the chip system, the submodules of each chip, and the connection structure. Therefore, the names of the chip, its submodules, and the connection structure in the design exchange format file can be updated according to the renaming of the chip and its submodules and the renaming of the connection structure in the physical connection relationship.

[0157] To update the Design Interchange Format file, refer to Figure 8 , Figure 8 It is a schematic diagram of an implementation process of obtaining connection data in the simulation method of the chip system provided by an embodiment of the present invention.

[0158] like Figure 8As shown, in the case where the first simulation input file is an exchange design format file, the chip may include: an upper chip in an upper hierarchical position in the chip system, and a lower chip relative to the upper chip according to the stacking hierarchy of the chip system; the renaming of the chip is a renaming with a hierarchical position identifier added, and the renaming of the submodule is a renaming with a hierarchical position identifier added to the chip; the design exchange format file includes: a design exchange format file of the upper chip, a design exchange format file of each first submodule in the upper chip, and a design exchange format file of a connection structure; a design exchange format file of the lower chip and a design exchange format file of each second submodule in the lower chip;

[0159] The renaming of each chip and each chip's submodule based on the chip, updating the name of each chip and each chip's submodule in the design exchange format file, comprises:

[0160] Step 2.1: Based on the renaming of each chip and each chip's sub-module, update the name of each chip and each chip's sub-module in the design exchange format file; and based on the renaming of the connection structure, update the name of the connection structure in the design exchange format file to obtain an updated design exchange format file.

[0161] When updating the design exchange format file, the design exchange format file of the upper chip, the design exchange format file of the lower chip, and the design exchange format file of the connection structure can all be updated. Alternatively, one of the design exchange format file of the upper chip and the design exchange format file of the lower chip can be selected for updating. Of course, the design exchange format file of the connection structure must be updated.

[0162] The update of the design exchange format file of the upper chip and / or the lower chip in step 2.1 may be:

[0163] The update of the design exchange format file of the upper-layer chip can be as follows: based on the renaming of each chip and the sub-modules of each chip, the upper-layer hierarchical position identifier is added to the name of the chip and its sub-modules in the design exchange format file of the upper-layer chip, and the upper-layer hierarchical position identifier is added to the name of the first sub-module in the exchange design format file of the first sub-module.

[0164] The updating of the design exchange format file of the lower-level chip can be as follows: based on the renaming of each chip and the sub-module of each chip, the name of the chip and its sub-modules is added with the lower-level hierarchical position identifier in the design exchange format file of the lower-level chip, and the name of the second sub-module in the exchange design format file of the second sub-module is added with the lower-level hierarchical position identifier.

[0165] The hierarchical position identifier indicates the hierarchical position of the chip. For example, the top die mentioned above is a chip at an upper hierarchical position, and the main die is a chip at a lower hierarchical position relative to the top die. Therefore, each chip can be distinguished based on the hierarchical position. Of course, the chips can also be distinguished by their names or by numbering them.

[0166] When the chips and submodules in the chips are distinguished by hierarchical position identifiers, the submodule of the upper chip at the upper hierarchical position is called a first submodule, and the submodule of the lower chip is called a second submodule.

[0167] Since the renaming of chips is mainly used to distinguish each chip and its internal sub-modules when forming a physical connection relationship, you can choose to rename the chip at the upper level and keep the name of the chip at the lower level unchanged (for example, as shown above: the first sub-module with the upper level hierarchical position identifier is renamed as: "itop_m3", and the name of the lower chip remains unchanged: "m3"); you can also choose to rename the chip at the lower level and keep the name of the chip at the upper level unchanged, so that each chip can be distinguished. Of course, you can also rename both the upper and lower chips to facilitate the simulation tool to identify different chips.

[0168] Therefore, when updating the exchange design format file, it can be updated according to the renaming of specific chips and submodules in the physical connection relationship. For example, taking the renaming of chips and submodules in the above-mentioned physical connection relationship as an example, when updating the design exchange format file, the names of the chips, their submodules and connection structures in the DEF file of the top die and the DEF file of the submodules included in the top die and the DEF file of the connection can be replaced with the renaming in the physical connection relationship. That is, the names of the metal layers and holes of the top die are replaced, the names of the metal layers and holes in the submodules that make up the top die are replaced, and the names of the metal layers and holes of the connection structure are replaced.

[0169] In other embodiments, the second simulation input file can be a library file; the library file includes: a library exchange format file, a timing library file (Timing Library File, .lib library file) and a current model file; wherein the library exchange format file contains device characteristics, which are used to describe the various standard unit modules and integrated circuit design modules that constitute the chip system; the timing library file contains device characteristics and process conditions, which are used to describe the timing and power consumption information of the various standard unit modules and integrated circuit design modules in the chip system; the current model file contains device characteristics, which are used to describe the flipping current conditions of the standard unit modules and the analog integrated circuit design modules under different output states.

[0170] Of course, the current model file may also include information such as equivalent resistance and capacitance leakage current, which can accurately reflect the instantaneous power consumption of the module.

[0171] Please continue to refer to Figure 8 ,like Figure 8 As shown, when the second simulation input file is a library file, the renaming of each chip and the submodule of each chip based on the physical connection relationship, and the renaming of the connection structure, updating the second simulation input file containing device characteristics and process conditions, and obtaining the updated second simulation input file, includes:

[0172] Step 3.1: Based on the renaming of each chip and the sub-module of each chip, for the library exchange format file of the sub-module used to constitute the chip and instantiated in the constituted chip, add the hierarchical position identifier of the corresponding chip to the name of the sub-module to obtain an updated library exchange format file with the hierarchical position identifier.

[0173] Step 3.2: Based on the renaming of each chip and the sub-module of each chip, for the timing library file of the sub-module used to constitute the chip and instantiated in the constituted chip, add the hierarchical position identifier of the corresponding chip to the name of the sub-module to obtain an updated timing library file with the hierarchical position identifier.

[0174] Step 3.3: Based on the renaming of each chip and the sub-module of each chip, for the current model file of the sub-module that is used to constitute the chip and is instantiated in the constituted chip, add the hierarchical position identifier of the corresponding chip to the name of the sub-module to obtain an updated current model file with the hierarchical position identifier.

[0175] When processing library type files, the LEF file is processed first because it contains the physical information of the standard cell library, such as the size, shape, hierarchy, pin location, etc. of the cell. This information is what layout tools (such as layout and routing tools) must know when placing cells.

[0176] The LEF file also contains information about the process layer, which is also necessary for subsequent wiring and verification steps.

[0177] After the LEF file is read, the next step is to process the ".lib library file". The ".lib library file" contains the timing information of the standard cell module, such as the cell's delay, fan-out number, load, etc. This information is crucial for timing analysis and optimization. The timing analysis tool will use the data in the ".lib library file" to calculate the timing characteristics of the circuit to ensure that the circuit meets the performance requirements.

[0178] When layout and timing analysis are complete, current model files are processed. These files contain the current characteristics of various parts of the circuit for signal integrity (SI) and power integrity (PI) analysis.

[0179] Current model files are usually extracted after layout design is complete because they require detailed information from the layout to accurately simulate the behavior of the circuit under actual operating conditions.

[0180] Ensure that the physical and electrical characteristics of the chip system design are properly considered and analyzed to achieve a high-performance, high-reliability chip system design.

[0181] Therefore, when updating library-type files based on the renaming of chips and submodules in the physical connection relationship, they are also updated in sequence according to the above processing order.

[0182] For example, the metal layer naming of the LEF file of the first submodule instantiated in the top die is replaced and a new LEF file is created. The updated LEF file can handle the submodule instantiation problem when the main die and the top die use the same logic unit library and IP library. For example, the same IP "macro" is instantiated in both the top die and the main die. Since the updated LEF file is based on the renaming of the chip and submodule in the physical connection information, the metal layer description of the pin in the original LEF file "macro.lef" of the IP is replaced to generate a new LEF file "itop_macro.lef". At the same time, the name of the commonly used IP is modified from "macro" -> "itop_macro", which will generate two LEF files with the same graphics for instantiation of the main die and the top die respectively.

[0183] After completing the update of the LEF file, perform the same renaming update on the lib library file and the current model file to generate new lib library files and current model files to ensure that the naming of the created logic units and analog module units is consistent in different library files.

[0184] In other embodiments, the third simulation input file is a process file; the process file includes: a layout and wiring process library exchange format file (layout and wiring process library LEF file), the layout and wiring process library exchange format file contains process parameters, which are used to describe the process layer and standard unit module of the chip system and the layout information of the integrated circuit design module.

[0185] Please continue to refer to Figure 8 ,like Figure 8 As shown, when the third simulation input file is a layout and routing process library exchange format file, the renaming of each chip and the submodule of each chip based on the physical connection relationship, and the renaming of the connection structure, update the third simulation input file containing the process parameters, and obtain the updated third simulation input file, including:

[0186] Step 4.1: Based on the renaming of each chip, submodule and connection structure, the names of each chip, submodule and connection structure in the layout and wiring process library exchange format file are updated to obtain an updated layout and wiring process library exchange format file.

[0187] Step 4.2: Merge the updated layout and routing process library exchange format file, the layout and routing process library exchange format file of the upper chip, the layout and routing process library exchange format file of the lower chip, and the layout and routing process library exchange format file of the connection structure connecting the upper chip and the lower chip.

[0188] First, based on the renaming of chips, submodules and connection structures in the physical connection relationship, the names of chips, submodules and connection structures in the layout and wiring process LEF file provided by each fab are replaced to generate a new layout and wiring process LEF file.

[0189] Then, merge the updated layout and wiring process library exchange format file, the layout and wiring process library exchange format file of the upper chip, the layout and wiring process library exchange format file of the lower chip, and the layout and wiring process library exchange format file of the connection structure connecting the upper chip and the lower chip. That is, the updated layout and wiring process library exchange format file of the upper chip, the layout and wiring process library exchange format file of the lower chip, and the layout and wiring process library exchange format file of the connection structure are "merged" to finally generate a LEF file containing all the merged information, which will be used in the subsequent physical design and verification process. The "merge" step is a key link to ensure that all design elements can be properly integrated and interacted in the physical design stage. Through this process, the consistency and manufacturability of the design can be ensured.

[0190] The merged layout and wiring process library exchange format file is mainly used for the voltage drop electromigration analysis simulation tool to identify the width information of the wiring layer. Since this technical solution is to perform voltage drop electromigration analysis on the power network, the power ground network wiring line width comes from the DEF file description. The layout and wiring process LEF file will not affect the tool to restore the power ground network wiring graphics, and is only used as a necessary file for the simulation tool input.

[0191] In some other implementations, the process file further includes: a voltage drop electromigration process file, wherein the voltage drop electromigration process file includes process parameters, a set of process parameters and rules for describing and controlling electromigration and voltage drop problems.

[0192] Please continue to refer to Figure 8 ,like Figure 8 As shown, when the third simulation input file is a voltage drop electromigration process file, the renaming of each chip and the submodule of each chip based on the physical connection relationship, and the renaming of the connection structure, update the third simulation input file containing the process parameters, and obtain the updated third simulation input file, including:

[0193] Step 5.1: Based on the renaming of each chip, submodule and connection structure, the name of each chip, submodule and connection structure in the voltage drop electromigration process file is updated to obtain an updated voltage drop electromigration process file.

[0194] Step 5.2: Merge the updated voltage drop electromigration process file, the voltage drop electromigration process file of the upper chip, the voltage drop electromigration process file of the lower chip, and the voltage drop electromigration process file of the connection structure connecting the upper chip and the lower chip.

[0195] First, based on the renaming of chips, sub-modules and connection structures in the physical connection relationship, the names of chips, sub-modules and connection structures in the voltage drop electromigration process file provided by each fab for voltage drop electromigration analysis are replaced to generate a new voltage drop electromigration process file.

[0196] Then, the updated voltage drop electromigration process file of the upper chip, the voltage drop electromigration process file of the lower chip, and the voltage drop electromigration process file of the connection structure are "merged" to finally generate a voltage drop electromigration process file containing all the merged information.

[0197] Among them, in the process of merging the updated voltage drop electromigration process files, the focus is on processing the relationship description of dies to connections at different hierarchical positions, and the connection relationship can be clarified in a fixed format. Information such as metal width, thickness, etching line width process table, block resistance, and dielectric layer definition does not need to be modified.

[0198] For example, the upper metal of TSV is connected to the HBM layer of connection, and the lower metal is connected to the thick metal side of main die. The upper metal of HBV is connected to the AP layer of top die, and the lower metal is connected to the HBM layer of connection.

[0199] After completing the update processing of the above simulation input files based on the physical connection relationship, the physical connection data of the chip system can be obtained. The updated lib library files, current model files, DEF files, LEF files, layout and wiring process LEF files, voltage drop electromigration process files and all library files originally used in the design (such as the aforementioned SPEF files and timing files that do not need to be modified) are read into the simulation tool (voltage drop electromigration simulation tool) to obtain the physical connection data of the chip system, complete the conversion of the stacking structure of the multi-die chip system to 2D graphics, and complete the logical connection and physical connection of the chip system.

[0200] After completing the update of each file in the simulation input file, please continue to refer to Figure 8 , the obtaining the connection data of the chip system based on the updated first simulation input file, the updated second simulation input file, and the updated third simulation input file includes:

[0201] Step 2.2: Determine the updated file status of the design exchange format file, instantiate each exchange design format file based on the updated file status, and extract data of the instantiated design exchange format file to obtain first connection data.

[0202] The main purpose of updating the simulation input file is to distinguish the various chips and connection structures in the chip system, and the design exchange format file includes different files for the upper chip, the lower chip and the connection structure. Therefore, after completing the step of updating the design exchange format file, the instantiation processing of each subsequent design exchange format file can be performed based on the specific updated file (i.e., the updated file status of the design exchange format file).

[0203] In one embodiment, step 2.2 may include:

[0204] When it is determined that the updated file situation is that the design exchange format file of the upper chip, the design exchange format file of the lower chip, and the design exchange format file of the connection structure are all updated, instantiate the updated design exchange format file of the lower chip; instantiate the updated design exchange format file of the upper chip and the design exchange format file of the connection structure;

[0205] Extracting data of the instantiated design exchange format file to obtain first connection data;

[0206] When it is determined that the update file situation is that the design exchange format file of the upper chip and the design exchange format file of the connection structure are both updated, but the design exchange format file of the lower chip is not updated, instantiate the design exchange format file of the lower chip that has not been updated; instantiate the updated design exchange format file of the upper chip and the design exchange format file of the connection structure;

[0207] Extracting data of the instantiated design exchange format file to obtain first connection data;

[0208] When it is determined that the updated file situation is that the design exchange format file of the lower chip and the design exchange format file of the connection structure are updated, but the design exchange format file of the upper chip is not updated, instantiate the updated design exchange format file of the lower chip; instantiate the unupdated design exchange format file of the upper chip and the updated design exchange format file of the connection structure;

[0209] The data of the instantiated design exchange format file is extracted to obtain the first connection data.

[0210] The updated design exchange format file is instantiated so that the logical connection relationship and the physical connection relationship of the chip system are reflected in the same updated design exchange format file.

[0211] Based on the update selection of different design exchange format files, accurate instantiation processing of each design exchange format file is implemented to obtain the first connection data that can accurately describe the physical structure of the chip system.

[0212] Please continue to refer to Figure 8 , the method may further include:

[0213] Step 3.4: extract data of the updated library exchange format file, the updated timing library file, and the updated current model file to obtain second connection data.

[0214] Step 4.3: Extract the data of the merged layout and routing process library exchange format file to obtain the third connection data.

[0215] Step 5.3: Extract data from the combined voltage drop electromigration process file to obtain fourth connection data.

[0216] Step 6: Based on the first connection data, the second connection data, the third connection data and the fourth connection data, obtain the connection data of the chip system.

[0217] Since the content of each file is different, after updating, the connection data of each updated file is extracted respectively to finally form the connection data of the chip system.

[0218] In the case where the first simulation input file is a design exchange format file, after completing the update of the design exchange format file of the chip and its submodules and the connection structure, a new design exchange format file will be generated. In order to ensure the design correctness of the chip system, optimize the performance and prepare for subsequent manufacturing, after obtaining the new design exchange format file, the design exchange format file is instantiated.

[0219] In one implementation, when it is determined that the update file situation is that the design exchange format file of the upper chip and the design exchange format file of the connection structure are both updated, but the design exchange format file of the lower chip is not updated, instantiation processing is performed on the design exchange format file of the lower chip that has not been updated, including:

[0220] Instantiating the updated design exchange format file of the upper layer chip and the updated design exchange format file of the connection structure in the design exchange format file of the lower layer chip that has not been updated;

[0221] In the design exchange format file of the lower layer chip that has not been updated, the power ground network definition that has power connection with the updated upper layer chip is logically redefined;

[0222] Complete the instantiation process of the design exchange format file of the underlying chip that has not been updated.

[0223] Instantiate the top die and connection DEF files in the main die DEF file. When instantiating the top die DEF and connection DEF, you can add the top die and connection as secondary modules to the main die DEF according to the definition method of instantiating a module from DEF. By describing the physical location and the instantiation name, add the following two definitions to the "COMPONENT (module)" in the main die DEF:

[0224] -itop topdie+FIXED(500 50000)N;

[0225] -icon connection+FIXED(500 50000)N;

[0226] Complete the instantiation of main die's DEF.

[0227] When the origin coordinates are not aligned, the coordinate information needs to be converted based on the reserved TSV center position of the main die and the displacement of the relative position of the TSV in the connection to the HBV hole center.

[0228] TSV is instantiated in the main die's DEF using an IP LEF (Library Exchange Format) file with specific coordinate information, so coordinate conversion can be performed.

[0229] After instantiating the top die's DEF and the connection's DEF into the main die's DEF, further redefine the logic connection of the power ground network definition that is connected to the top die in the main die's DEF file. For example, to supply power from the main die's VDD1 to the top die's VDD and the connection's VDD_CON, supplement the logical connection relationship of VDD1 in the main die's DEF file according to the DEF syntax:

[0230] -VDD1

[0231] (PIN VDD1)

[0232] (*VDD1)

[0233] (itop VDD)

[0234] (iconn VDD_CON).

[0235] Of course, the simulation input files of the design type may also include SPEF (Standard Parasitic Extraction Format) files and timing files. However, due to the characteristics of the content recorded in the SPEF files and timing files themselves, they do not need to be updated. Therefore, the timing files and SPEF files can be used directly.

[0236] In one implementation, when it is determined that the update file situation is that the design exchange format file of the upper chip and the design exchange format file of the connection structure are both updated, but the design exchange format file of the lower chip is not updated, the instantiation processing of the updated design exchange format file of the upper chip includes:

[0237] In the updated design exchange format file of the upper-layer chip, the hierarchical position identifier of the upper layer is added to the naming of the instantiated standard cell module, and the hierarchical position identifier of the upper layer is added to the name of the instantiated integrated circuit design module; the standard cell module and the integrated circuit design module are the first sub-module constituting the upper-layer chip.

[0238] The instantiation of the design exchange format file of the upper chip refers to modifying the name of the instantiated IP (integrated circuit design module) or standard cell module in the DEF file of the top die. For example, add the prefix "itop_" to the names of the IP and standard cell modules that appear in the DEF of the top die to ensure that the design exchange format file of the upper chip can be used normally.

[0239] For example, when instantiating the top die's DEF file, you can make the following updates:

[0240] Replace "-aaa inv1+FIXED(10000 10000)N";

[0241] Modified to:

[0242] "-aaa itop_inv1+FIXED(10000 10000)N";

[0243] The above represents the instantiation information of a library unit.

[0244] "-aaa" is used to specify that the component has certain attributes.

[0245] "inv1" is the name of the library cell, indicating that this is a standard cell or macro cell named inv1.

[0246] "+FIXED" is a placement status mark, indicating that the location of the library cell is fixed and cannot be changed. In layout design, the FIXED state is usually used for cells with determined locations, such as macro cells or specific standard cells.

[0247] "(10000 10000)" is the coordinate position of the library unit in the overall layout of the chip system, indicating that the lower left corner of the library unit is located at the coordinate (10000, 10000). The coordinate unit depends on the unit defined in the DEF file (such as micrometers, nanometers, etc.).

[0248] "N" indicates the placement direction of the library cell. In the DEF file, N stands for North, which is the 0 degree direction, indicating that the library cell is placed in its original direction without rotation.

[0249] Of course, in other file update situations, the instantiation processing of the design exchange format file of the upper-layer chip, the design exchange format file of the lower-layer chip, and the design exchange format file of the connection structure is the same as the above-mentioned execution process, except that the design exchange format file of the upper-layer chip or the design exchange format file of the lower-layer chip that has not been updated is used.

[0250] Please continue to refer to Figure 8 , and may also include:

[0251] Step 7: Extract the power network simulation nodes of the chip system from the physical connection data, and construct the power network structure of the chip system based on the extracted power network simulation nodes.

[0252] Step 8: Perform voltage drop electromigration simulation on the chip system based on the power network structure.

[0253] An embodiment of the present invention further provides a simulation device for a chip system, which is used to implement the simulation method for the chip system described in the above embodiment.

[0254] Please refer to Fig. 9 , Fig. 9 It is a structural schematic diagram of a simulation device for a chip system provided in an embodiment of the present invention.

[0255] like Fig. 9 As shown, the device comprises:

[0256] A data acquisition module 91 is used to acquire connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system;

[0257] A power network structure building module 92, used to extract power network simulation nodes of the chip system from the physical connection data, and build the power network structure of the chip system based on the extracted power network simulation nodes;

[0258] The simulation module 93 is used to perform voltage drop electromigration simulation on the chip system based on the power network structure.

[0259] like Fig. 9 As shown, optionally, the device further includes:

[0260] The physical connection relationship forming module 90 is used to redefine the names of the chips in the chip system and the submodules constituting the chips, so as to rename the chips and submodules so that different chips have different names; and to redefine the names of the connection structures connecting the chips, so as to rename the connection structures; and to sort the renamed chips, submodules of the chips and connection structures in the vertical direction of the stacking level of the chip system, so as to form the physical connection relationship of the chip system;

[0261] The data acquisition module 91 is used to acquire the connection data of the chip system, including:

[0262] Based on the renaming of each chip and the submodule of each chip in the physical connection relationship and the renaming of the connection structure, according to the type of the simulation input file of the chip system, the simulation input file of the corresponding type is updated;

[0263] The connection data of the chip system is obtained based on the updated simulation input file.

[0264] Optionally, the type of the simulation input file includes: a design type; the simulation input file of the design type is a design exchange format file, and the design exchange format file is used to describe the layout, circuit and physical information of the chip system;

[0265] The data acquisition module 91 is used to update the corresponding type of simulation input file according to the type of the simulation input file of the chip system based on the renaming of each chip and the submodule of each chip in the physical connection relationship and the renaming of the connection structure, including:

[0266] Based on the renaming of the individual chips and the submodules of each chip, updating the names of the individual chips and the submodules of each chip in the design exchange format file, and based on the renaming of the connection structure, updating the names of the connection structures in the design exchange format file;

[0267] The data acquisition module 91 is used to acquire the connection data of the chip system based on the updated simulation input file, including:

[0268] Instantiate the updated design exchange format file;

[0269] The data of the instantiated design exchange format file is extracted to form connection data of the chip system.

[0270] Optionally, the types of simulation input files include: library type; simulation input files of library type include: library exchange format file, timing library file and current model file; wherein, the library exchange format file is used to describe each standard cell module and integrated circuit design module constituting the chip system; the timing library file is used to describe the timing and power consumption information of each standard cell module and integrated circuit design module in the chip system; the current model file is used to describe the flip current of the standard cell module and the analog integrated circuit design module under different output states;

[0271] The data acquisition module 91 is used to update the corresponding type of simulation input file according to the type of the simulation input file of the chip system based on the renaming of each chip and the submodule of each chip in the physical connection relationship and the renaming of the connection structure, including:

[0272] Based on the renaming of each chip and each chip's submodule, for the library exchange format file of each submodule that is used to constitute the chip and is instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the submodule to form a library exchange format file of the submodule with the hierarchical position identifier;

[0273] Based on the renaming of each chip and each chip's submodule, for the timing library file of each submodule that is used to constitute the chip and is instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the submodule to form a timing library file of the submodule with the hierarchical position identifier;

[0274] And, based on the renaming of each chip and each chip's submodule, for the current model file of each submodule that is used to constitute the chip and is instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the submodule to form a current model file of the submodule with the hierarchical position identifier;

[0275] The data acquisition module 91 is used to acquire the connection data of the chip system based on the updated simulation input file, including:

[0276] The data of the updated library exchange format file, the updated timing library file, and the updated current model file are extracted to form connection data of the chip system.

[0277] Optionally, the type of the simulation input file includes: process type; the simulation input file of the process type includes: a layout and wiring process library exchange format file, the layout and wiring process library exchange format file is used to describe the process layer and standard unit module of the chip system and the layout information of the integrated circuit design module;

[0278] The data acquisition module 91 is used to update the corresponding type of simulation input file according to the type of the simulation input file of the chip system based on the renaming of each chip and the submodule of each chip in the physical connection relationship and the renaming of the connection structure, including:

[0279] Based on the renaming of each chip, submodule and connection structure, updating the name of each chip, submodule and connection structure in the layout and routing process library exchange format file;

[0280] Merging the layout and wiring process library exchange format file of the upper chip, the layout and wiring process library exchange format file of the lower chip, and the layout and wiring process library exchange format file of the connection structure connecting the upper chip and the lower chip in the updated layout and wiring process library exchange format file;

[0281] The data acquisition module 91 is used to acquire the connection data of the chip system based on the updated simulation input file, including:

[0282] The data of the merged layout and routing process library exchange format file is extracted to form connection data of the chip system.

[0283] It can be seen that according to the technical solution provided by the embodiment of the present invention, when performing voltage drop and electromigration simulation of a chip system, the connection data of the chip system includes: physical connection data formed based on the physical connection relationship between each chip in the chip system; therefore, when extracting power network simulation nodes based on the physical connection data, the power network simulation nodes can reflect the nodes of the physical connection relationship between each chip; and then the power network structure constructed based on the extracted power network simulation nodes can be close to the power network distribution in the real physical structure of the chip system, so that when simulating based on the power network structure, the obtained simulation results can more reliably reflect the power network distribution of the chip system, which is convenient for adjusting the power network distribution of the chip system and extending the service life of the chip system.

[0284] An embodiment of the present invention provides an electronic device, such as a terminal device, a server device, or other computer device, comprising a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute a simulation method of a chip system as described in any of the aforementioned embodiments.

[0285] An embodiment of the present invention provides a storage medium storing a program, which, when executed, implements the simulation method of the chip system as described in any of the above embodiments.

[0286] An embodiment of the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements the simulation method of the chip system as described in any of the above embodiments.

[0287] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0288] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A simulation method for a chip system, characterized in that: include: Acquire connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system; Extracting power network simulation nodes of the chip system from the physical connection data, and constructing a power network structure of the chip system based on the extracted power network simulation nodes; A voltage drop electromigration simulation is performed on the chip system based on the power supply network structure.

2. The chip system simulation method according to claim 1, characterized in that: Before the step of obtaining the connection data of the chip system, the method further includes: Redefine the names of the chips in the chip system and the submodules constituting the chips, thereby renaming the chips and submodules, so that different chips and submodules have different names; and redefine the names of the connection structures connecting the chips, thereby renaming the connection structures; In the vertical direction of the stacking level of the chip system, the renamed chips, the submodules of the chips, and the connection structures are sorted to form a physical connection relationship of the chip system; The obtaining the connection data of the chip system includes: Based on the renaming of each chip and the submodules of each chip in the physical connection relationship, and the renaming of the connection structure, updating the simulation input file of the chip system; The connection data of the chip system is obtained based on the updated simulation input file.

3. The chip system simulation method according to claim 2, characterized in that: The simulation input file is a set of files including circuit design, process parameters, device characteristics and working conditions; the renaming of each chip and each chip's submodule in the physical connection relationship, and the renaming of the connection structure, updating the simulation input file of the chip system, includes: Based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the first simulation input file containing the circuit design to obtain an updated first simulation input file; Based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the second simulation input file containing device characteristics and working conditions to obtain an updated second simulation input file; And, based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating a third simulation input file containing process parameters to obtain an updated third simulation input file; The obtaining the connection data of the chip system based on the updated simulation input file includes: Based on the updated first simulation input file, the updated second simulation input file, and the updated third simulation input file, connection data of the chip system is acquired.

4. The chip system simulation method according to claim 3, characterized in that: The first simulation input file is a design file, the design file includes a design exchange format file, the design exchange format file contains a circuit design, and is used to describe the layout, circuit and physical information of the chip system; The renaming of each chip and the submodule of each chip based on the physical connection relationship and the renaming of the connection structure, updating the first simulation input file containing the circuit design, and obtaining the updated first simulation input file, comprises: Based on the renaming of each chip and each chip's sub-module, the name of each chip and each chip's sub-module in the design exchange format file is updated; and based on the renaming of the connection structure, the name of the connection structure in the design exchange format file is updated to obtain an updated design exchange format file.

5. The chip system simulation method according to claim 4, characterized in that: The chip comprises: an upper chip at an upper hierarchical position in the chip system according to the stacking level of the chip system, and a lower chip relative to the upper chip; the renaming of the chip is a renaming with a hierarchical position identifier added, and the renaming of the submodule is a renaming with a hierarchical position identifier added to the chip; the design exchange format file comprises: a design exchange format file of the upper chip, a design exchange format file of each first submodule in the upper chip, and a design exchange format file of a connection structure; a design exchange format file of the lower chip and a design exchange format file of each second submodule in the lower chip; The renaming of each chip and each chip's submodule based on the chip, updating the name of each chip and each chip's submodule in the design exchange format file, comprises: Based on the renaming of each chip and each chip's submodule, in the design exchange format file of the upper chip, the name of the chip and its submodule is added with the upper layer's hierarchical position identifier, and in the name of the first submodule of the exchange design format file of the first submodule, the upper layer's hierarchical position identifier is added; And / or, based on the renaming of each chip and the sub-modules of each chip, the lower-level hierarchical position identifier is added to the name of the chip and its sub-modules in the design exchange format file of the lower-level chip, and the lower-level hierarchical position identifier is added to the name of the second sub-module in the exchange design format file of the second sub-module.

6. The chip system simulation method according to claim 4, characterized in that: The second simulation input file is a library file, and the library file includes: a library exchange format file, a timing library file and a current model file; wherein the library exchange format file contains device characteristics, which are used to describe the various standard unit modules and integrated circuit design modules that constitute the chip system; the timing library file contains device characteristics and process conditions, which are used to describe the timing and power consumption information of the various standard unit modules and integrated circuit design modules in the chip system; the current model file contains device characteristics, which are used to describe the flip current conditions of the standard unit modules and the analog integrated circuit design modules under different output states; The renaming of each chip and the submodule of each chip based on the physical connection relationship and the renaming of the connection structure, updating the second simulation input file containing device characteristics and process conditions, and obtaining the updated second simulation input file, includes: Based on the renaming of each chip and the submodule of each chip, for the library exchange format file of the submodule that is used to constitute the chip and is instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the submodule to obtain an updated library exchange format file with the hierarchical position identifier; Based on the renaming of each chip and the submodule of each chip, for the timing library file of the submodule that is used to constitute the chip and is instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the submodule to obtain an updated timing library file with the hierarchical position identifier; Furthermore, based on the renaming of each chip and the sub-module of each chip, for the current model file of the sub-module that is used to constitute the chip and is instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the sub-module to obtain an updated current model file with the hierarchical position identifier.

7. The chip system simulation method according to claim 6, characterized in that: The third simulation input file is a process file, and the process file includes: a layout and wiring process library exchange format file, and the layout and wiring process library exchange format file contains process parameters, which are used to describe the process layer and standard unit module of the chip system and the layout information of the integrated circuit design module; The renaming of each chip and the submodule of each chip based on the physical connection relationship and the renaming of the connection structure, updating the third simulation input file containing the process parameters to obtain the updated third simulation input file, includes: Based on the renaming of each chip, submodule and connection structure, the name of each chip, submodule and connection structure in the layout and wiring process library exchange format file is updated to obtain an updated layout and wiring process library exchange format file; The method further comprises: The updated layout and wiring process library exchange format file includes the layout and wiring process library exchange format file of the upper chip, the layout and wiring process library exchange format file of the lower chip, and the layout and wiring process library exchange format file of the connection structure connecting the upper chip and the lower chip.

8. The chip system simulation method according to claim 7, characterized in that: The process file also includes: a voltage drop electromigration process file, the voltage drop electromigration process file includes process parameters, a set of process parameters and rules for describing and controlling electromigration and voltage drop problems; The renaming of each chip and the submodule of each chip based on the physical connection relationship and the renaming of the connection structure, updating the third simulation input file containing the process parameters to obtain the updated third simulation input file, includes: Based on the renaming of each chip, submodule and connection structure, the name of each chip, submodule and connection structure in the voltage drop electromigration process file is updated to obtain an updated voltage drop electromigration process file; The method further comprises: The updated voltage drop electromigration process file includes the voltage drop electromigration process file of the upper chip, the voltage drop electromigration process file of the lower chip, and the voltage drop electromigration process file of the connection structure connecting the upper chip and the lower chip.

9. The chip system simulation method according to claim 8, characterized in that: The acquiring the connection data of the chip system based on the updated first simulation input file, the updated second simulation input file, and the updated third simulation input file comprises: Determine the update file status of the design exchange format file, instantiate each exchange design format file based on the update file status, and extract data of the instantiated design exchange format file to obtain first connection data; Extracting data of an updated library exchange format file, an updated timing library file, and an updated current model file to obtain second connection data; and extracting data of the merged layout and routing process library exchange format file to obtain third connection data, and extracting data of the merged voltage drop electromigration process file to obtain fourth connection data; The connection data of the chip system is obtained based on the first connection data, the second connection data, the third connection data and the fourth connection data.

10. The chip system simulation method according to claim 9, characterized in that: The determining of the update file status of the design exchange format file, instantiating each exchange design format file based on the update file status, and extracting data of the instantiated design exchange format file to obtain the first connection data includes: When it is determined that the updated file situation is that the design exchange format file of the upper chip, the design exchange format file of the lower chip, and the design exchange format file of the connection structure are all updated, instantiate the updated design exchange format file of the lower chip; instantiate the updated design exchange format file of the upper chip and the design exchange format file of the connection structure; Extracting data of the instantiated design exchange format file to obtain first connection data; When it is determined that the update file situation is that the design exchange format file of the upper chip and the design exchange format file of the connection structure are both updated, but the design exchange format file of the lower chip is not updated, instantiate the design exchange format file of the lower chip that has not been updated; instantiate the updated design exchange format file of the upper chip and the design exchange format file of the connection structure; Extracting data of the instantiated design exchange format file to obtain first connection data; When it is determined that the updated file situation is that the design exchange format file of the lower chip and the design exchange format file of the connection structure are updated, but the design exchange format file of the upper chip is not updated, instantiate the updated design exchange format file of the lower chip; instantiate the unupdated design exchange format file of the upper chip and the updated design exchange format file of the connection structure; The data of the instantiated design exchange format file is extracted to obtain the first connection data.

11. The chip system simulation method according to claim 10, characterized in that: When it is determined that the update file situation is that the design exchange format file of the upper chip and the design exchange format file of the connection structure are both updated, but the design exchange format file of the lower chip is not updated, the instantiation processing of the design exchange format file of the lower chip that is not updated includes: Instantiating the updated design exchange format file of the upper layer chip and the updated design exchange format file of the connection structure in the design exchange format file of the lower layer chip that has not been updated; In the design exchange format file of the lower layer chip that has not been updated, the power ground network definition that has power connection with the updated upper layer chip is logically redefined; Complete the instantiation process of the design exchange format file of the underlying chip that has not been updated.

12. The chip system simulation method according to claim 11, characterized in that: The instantiation processing of the updated design exchange format file of the upper chip includes: In the updated design exchange format file of the upper chip, the hierarchical position identifier of the upper layer is added to the naming of the instantiated standard cell module, and the hierarchical position identifier of the upper layer is added to the name of the instantiated integrated circuit design module; The standard cell module and the integrated circuit design module are the first submodules constituting the upper chip.

13. The chip system simulation method according to any one of claims 2 to 12, characterized in that: The extracting of power supply network simulation nodes of the chip system from the physical connection data includes: Based on the renaming of the chips and the submodules of each chip and the connection structure in the updated simulation input file, internal data describing the physical connection relationship of each chip and connection structure data describing the physical connection relationship between chips are determined in the physical connection data; Abstractly generate internal simulation nodes of each chip according to the internal data, and abstractly generate simulation nodes of connection structures for connecting chips according to the connection structure data; Based on the generated internal simulation nodes of each chip and the simulation nodes of the connection structure, a power network simulation node of the chip system is formed.

14. The chip system simulation method according to claim 13, characterized in that: The abstraction and generation of a simulation node for connecting a connection structure between chips according to the connection structure data includes: Based on the data of the metal layer describing the connection structure and the data of the relative position relationship of the connection holes connecting the metal layers in the connection structure data, a connection structure simulation node is abstractly generated.

15. The chip system simulation method according to claim 13, characterized in that: The step of constructing the power supply network structure of the chip system based on the extracted power supply network simulation nodes includes: Adding the internal simulation nodes of the chip and the simulation nodes of the connection structure to the corresponding connection positions in the resistance, inductance and capacitance model of the chip system to construct a power network structure of the chip system; The RL model is used to describe and simulate the circuit connection between the internal simulation nodes of the chip and the simulation nodes of the connection structure.

16. The chip system simulation method according to any one of claims 1 to 12, characterized in that: The connection data of the chip system is connection data of a chip system designed with back side power supply.

17. A simulation device for a chip system, characterized in that: include: A data acquisition module, used to acquire connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system; A power network structure construction module, used to extract power network simulation nodes of the chip system from the physical connection data, and to construct a power network structure of the chip system based on the extracted power network simulation nodes; A simulation module is used to perform voltage drop electromigration simulation on the chip system based on the power network structure.

18. An electronic device, characterized in that: It comprises a memory and a processor, the memory stores a program, and the processor calls the program stored in the memory to execute the simulation method of the chip system as described in any one of claims 1-16.

19. A storage medium, characterized in that: The storage medium stores a program, and when the program is executed, the simulation method of the chip system according to any one of claims 1 to 16 is implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the simulation method of the chip system as described in any one of claims 1 to 16 is implemented.

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