Buffer circuit and memory

Abstract

The invention relates to a buffer circuit and a memory. The buffer circuits are applied to the memory, each of the CA0 buffer circuit, the CA1 buffer circuit, the CA2 buffer circuit, the CA3 buffer circuit and the CA4 buffer circuit comprises a first command address input end connected with a command address pin, and different CA buffer circuits are connected with different command address pins; the first circuit output end is used for outputting a digital signal; the positive input end of the first comparator is connected with the first command address input end, the reverse input end receives a reference signal, the enable end receives a power-down enable signal, and the output end is connected with the output end of the first circuit; after the memory enters the power-down mode, the first comparator is turned off based on the level of the power-down enable signal; and the first voltage output circuit is used for outputting high-level voltage or low-level voltage to the output end of the first circuit after the memory enters the power-down mode. After entering the power-down mode and closing the CA buffer circuits, the power-down mode can be effectively quitted.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a buffer circuit and a memory. Background Art

[0002] The fifth generation double data rate memory (DDR5) specification (SPEC) stipulates that in power-down mode, all command address (CA) buffer circuits need to be turned off to reduce power consumption. At the same time, when the CA buffer circuit is turned off, the memory still needs to be able to correctly receive the power-down exit (PDE) command to exit the power-down mode.

[0003] However, after the CA buffer circuit is turned off, the next time the PDE command is sent, it will not be recognized. Therefore, a special setting is required to recognize the PDE command in power-down mode. Summary of the invention

[0004] Based on this, an embodiment of the present application provides a buffer circuit and a memory that can identify a PDE command in a power-off mode.

[0005] A buffer circuit, applied to a memory, includes a CA0 buffer circuit, a CA1 buffer circuit, a CA2 buffer circuit, a CA3 buffer circuit, and a CA4 buffer circuit, wherein the CA0 buffer circuit, the CA1 buffer circuit, the CA2 buffer circuit, the CA3 buffer circuit, and the CA4 buffer circuit each include:

[0006] A first command address input terminal is connected to a command address pin, and different CA buffer circuits are connected to different command address pins;

[0007] A first circuit output terminal, used for outputting a digital signal;

[0008] a first comparator, wherein a positive input terminal is connected to the first command address input terminal, a reverse input terminal receives a reference signal, an enable terminal receives a power-down enable signal, and an output terminal is connected to the first circuit output terminal; after the memory enters the power-down mode, the first comparator is turned off based on the level of the power-down enable signal;

[0009] The first voltage output circuit is used to output a high level voltage or a low level voltage to the first circuit output terminal after the memory enters the power-down mode.

[0010] In one embodiment, the output voltage circuit includes:

[0011] A first pull-up circuit, connected to the first circuit output end, and configured to output the high level voltage to the first circuit output end;

[0012] The first pull-down circuit is connected to the output end of the first circuit and is used to output the low-level voltage to the output end of the first circuit.

[0013] In one embodiment, the first pull-up circuit comprises:

[0014] A first switch unit has one end connected to the output end of the first circuit and the other end connected to the high level voltage.

[0015] In one embodiment, the first switch unit includes:

[0016] A first P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage;

[0017] The second P-type transistor has a gate connected to the command address inversion signal, a source connected to the drain of the first P-type transistor, and a drain connected to the output end of the first circuit.

[0018] In one embodiment, the first pull-up circuit comprises:

[0019] A second switch unit has one end connected to the output end of the first circuit and the other end connected to the low level voltage.

[0020] In one embodiment, the second switch unit includes:

[0021] A first N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage;

[0022] The second N-type transistor has a gate connected to a power-off enable reverse signal, a source connected to the drain of the first N-type transistor, and a drain connected to the output end of the first circuit. The power-off enable reverse signal has a level opposite to that of the power-off enable signal.

[0023] In one embodiment, the command address buffer circuit further includes a CA12 buffer circuit and a CA13 buffer circuit.

[0024] The CA12 buffer circuit comprises:

[0025] The second command address input terminal is connected to the CA12 pin;

[0026] The second circuit output terminal is used to output a digital signal;

[0027] A second comparator, wherein the positive input terminal is connected to the second command address input terminal, the reverse input terminal is used to input a reference signal, the output terminal is connected to the second circuit output terminal, and the enable terminal is connected to a second enable signal, wherein the level of the second enable signal is high when exiting the power-down mode and in the non-mirror mode, and is low in other cases;

[0028] a second voltage output circuit, configured to output the high level voltage or the low level voltage to the second circuit output terminal after the memory enters a power-down mode;

[0029] The CA13 buffer circuit comprises:

[0030] The third command address input terminal is connected to the CA13 pin;

[0031] The third circuit output terminal is used to output a digital signal;

[0032] A third comparator, wherein the positive input terminal is connected to the third command address input terminal, the reverse input terminal is used to input a reference signal, the output terminal is connected to the third circuit output terminal, and the enable terminal is connected to a third enable signal, the level of the third enable signal is high when exiting the power-down mode and in the mirror mode, and is low in other cases;

[0033] The third voltage output circuit is used to output the high level voltage or the low level voltage to the output terminal of the third circuit after the memory enters the power-down mode.

[0034] In one embodiment, the CA12 buffer circuit further includes a NOR gate, two output ends of the NOR gate are respectively connected to the power-off enable reverse signal and the mirror enable signal, and the output end is used to output the second enable signal to the enable end of the second comparator.

[0035] In one embodiment, the CA13 buffer circuit further includes an AND gate, two output ends of the AND gate are respectively connected to a power-off enable signal and a mirror enable signal, and the output end is used for the enable end of the third comparator to output the third enable signal.

[0036] In one embodiment, the second voltage output circuit includes a second pull-up circuit and a second pull-down circuit.

[0037] The second pull-up circuit comprises:

[0038] A third P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage;

[0039] a fourth P-type transistor, having a gate connected to the command address inversion signal, a source connected to the drain of the third P-type transistor, and a drain connected to the output end of the second circuit;

[0040] The second pull-down circuit comprises:

[0041] A third N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage;

[0042] a fourth N-type transistor, having a gate connected to a power-off enable reverse signal, a source connected to a drain of the third N-type transistor, and a drain connected to an output end of the second circuit, wherein the power-off enable reverse signal is a reverse signal of the power-off enable signal;

[0043] A fifth N-type transistor has a gate connected to the mirror enable signal, a source connected to the low level voltage, and a drain connected to the output end of the second circuit.

[0044] In one embodiment, the third voltage output circuit includes a third pull-up circuit and a third pull-down circuit.

[0045] The third pull-up circuit comprises:

[0046] a fifth P-type transistor, whose gate is connected to the power-down enable signal and whose source is connected to the high-level voltage; a sixth P-type transistor, whose gate is connected to the command address inversion signal and whose source is connected to the drain of the fifth P-type transistor and whose drain is connected to the output terminal of the third circuit;

[0047] The third pull-down circuit comprises:

[0048] A sixth N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage;

[0049] a seventh N-type transistor, wherein the gate is connected to the power-off enable reverse signal, the source is connected to the drain of the sixth N-type transistor, the drain is connected to the output end of the third circuit, and the power-off enable reverse signal has a level opposite to that of the power-off enable signal;

[0050] An eighth N-type transistor, having a gate connected to a mirror enable reverse signal, a source connected to the low level voltage, and a drain connected to the output end of the third circuit, wherein the mirror enable reverse signal has a level opposite to that of the mirror enable signal.

[0051] In one embodiment, the command address buffer circuit further includes a CA5 to CA11 buffer circuit, and the CA5 to CA11 buffer circuit has the same circuit structure as the CA0 to CA4 buffer circuit.

[0052] A memory, comprising:

[0053] A buffer circuit as described in any one of the above items;

[0054] A command address buffer control circuit, connected to the buffer circuit, and configured to output the power-down enable signal to the buffer circuit;

[0055] The decoder circuit is connected to the command address buffer control circuit and is used to send a power-down mode exit command to the command address buffer control circuit.

[0056] In one embodiment, the memory further comprises:

[0057] The address mirror circuit is connected to the buffer circuit and is used to send a mirror enable signal to the buffer circuit.

[0058] In one embodiment, the memory further comprises:

[0059] A command address inversion pin is connected to the buffer circuit and is used to send a command address inversion signal to the buffer circuit.

[0060] The above-mentioned buffer circuit and memory are provided with a first voltage output circuit in the CA0 to CA4 buffer circuits. Therefore, after entering the power-down mode and turning off all CA buffer circuits, the CA0 to CA4 buffer circuits can still output a high-level voltage or a low-level voltage to the first circuit output terminal through the first voltage output circuit, so that the first circuit output terminal can output a digital signal even when the first comparator is turned off. At this time, after applying low-level data to the CS_N pin, the digital signal data output by the first voltage output circuit of the CA0 to CA4 buffer circuits is combined with the data on the CS_N pin to form a command to exit the power-down mode that complies with the SPEC truth table of the memory (such as DDR5), thereby exiting the power-down mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 A module block diagram of a memory according to an embodiment;

[0063] Figure 2 A module block diagram of a memory according to another embodiment;

[0064] Figure 3 The circuit structure adopted by the CA0 to CA4 buffer circuits of one embodiment;

[0065] Figure 4 A circuit structure of a CA12 buffer circuit according to an embodiment;

[0066] Figure 5 Circuit structure of CA13 buffer circuit of one embodiment

[0067] Figure 6 A circuit structure of a NOR gate in a CA12 buffer circuit according to an embodiment;

[0068] Figure 7 A circuit structure of an AND gate in a CA13 buffer circuit according to an embodiment.

[0069] Description of reference numerals:

[0070] 100-buffer circuit, 111-first command address input terminal, 112-first circuit output terminal, 113-first comparator, 114-first voltage output circuit, 1141-first pull-up circuit, 1142-first pull-down circuit, 121-second command address input terminal, 122-second circuit output terminal, 123-second comparator, 124-second voltage output circuit, 1241-second pull-up circuit, 1242-second pull-down circuit, 125-NOR gate, 131-third command address input terminal, 132-third circuit output terminal, 133-third comparator, 134-third voltage output circuit, 1341-third pull-up circuit, 1342-third pull-down circuit, 135-AND gate, 200-command address buffer control circuit, 300-decoder circuit, 400-address mirror circuit, 500-command address inversion pin. DETAILED DESCRIPTION

[0071] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0073] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0074] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0075] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0076] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0077] In one embodiment, a memory is provided. The memory may include, but is not limited to, a fifth generation double data rate memory (DDR5).

[0078] See also Figure 1 , the memory includes a buffer circuit 100, a command address buffer control circuit 200, and a decoder circuit 300. Meanwhile, the memory may include a plurality of command address (CA) pins.

[0079] In the buffer circuit 100 , a CA buffer circuit may be correspondingly provided for each CA pin.

[0080] As an example, in DDR5, the memory is provided with 14 CA pins (CA0 to CA13 pins). Accordingly, in the buffer circuit 100, 14 CA buffer circuits (CA0 to CA13 buffer circuits) are provided accordingly.

[0081] At the same time, DDR5 also has a chip select signal (CS_N) pin. Different CA pins can output different data through their corresponding CA buffer circuits. According to the SPEC truth table of DDR5, the data output by the CA buffer circuit corresponding to each CA pin is combined with the data on the CS_N pin to form a certain command. Different data combinations can form different commands.

[0082] For example, as shown in the SPEC truth table in Table 1 below, when the data on the CS_N pin corresponds to a low level L, and the data output by the CA buffer circuit corresponding to the CA0 to CA4 pins (i.e., the CA0 to CA4 buffer circuit) corresponds to a high level H, it represents a command to "exit power-down mode". At the same time, it can be understood that at this time, the data output by the CA buffer circuit corresponding to the CA5 to CA13 pins (i.e., the CA5 to CA13 buffer circuit) corresponds to a level V, which means that the data output by the CA buffer circuit corresponding to the CA5 to CA13 pins can correspond to a high level H or a low level L.

[0083] Table 1

[0084]

[0085] The command address buffer control circuit 200 is connected to the buffer circuit 100 , and can generate and output a power-down enable signal En to the buffer circuit 100 .

[0086] As an example, the command address buffer control circuit 200 may also generate and output a power-down enable reverse signal Enb to the buffer circuit 100. The power-down enable reverse signal Enb is opposite in level to the power-down enable signal En. When the level of the power-down enable signal En is high, the level of the power-down enable reverse signal Enb is low. When the level of the power-down enable signal En is low, the level of the power-down enable reverse signal Enb is high.

[0087] The decoder circuit 300 is connected to the command address buffer control circuit 200 and is used to send a power-down mode exit command to the command address buffer control circuit 200 .

[0088] When the command address buffer control circuit 200 receives the command to exit the power-down mode decoded by the decoder circuit 300, it can generate a high-level power-down enable signal En and a low-level power-down enable reverse signal Enb;

[0089] At the same time, as an example, the decoder circuit 300 may also send a power-down mode entry command to the command address buffer control circuit 200 .

[0090] When the command address buffer control circuit 200 receives the command for entering the power-down mode decoded by the decoder circuit 300 , it can generate a low-level power-down enable signal En and a high-level power-down enable inverse signal.

[0091] In one embodiment, see Figure 2 The memory may also include an address mirror circuit 400. The address mirror circuit 400 is connected to the buffer circuit 100 and is used to send a mirror enable signal Mir to the buffer circuit 100. When the level of the mirror enable signal Mir is high, it indicates that the mirror mode is entered. When the level of the mirror enable signal Mir is low, it indicates that the non-mirror mode is entered.

[0092] As an example, the address mirror circuit 400 may also send a mirror enable inverted signal Mirb to the buffer circuit 100. The mirror enable inverted signal Mirb has a level opposite to that of the mirror enable signal Mir.

[0093] The memory may further include a mirror (MIR) pin. An input terminal of the address mirror circuit 400 may be connected to the mirror (MIR) pin.

[0094] When the MIR pin is connected to the power supply voltage VDDQ, it indicates that the mirror mode is to be entered. At this time, the address mirror circuit 400 can generate and send a high-level mirror enable signal Mir to the buffer circuit 100, and can generate and send a low-level mirror enable reverse signal Mirb to the buffer circuit 100.

[0095] At the same time, the memory can control the mirror exchange of the even-numbered CA buffer circuit with the next odd-numbered CA buffer circuit. For example, the CA2 buffer circuit can be mirror exchanged with the CA3 buffer circuit (not the CA1 buffer circuit). The CA4 buffer circuit can be mirror exchanged with the CA5 buffer circuit (not the CA3 buffer circuit).

[0096] When the MIR pin is connected to the power supply voltage VSS, it indicates that the non-mirror mode is to be entered instead of the mirror mode. At this time, the address mirror circuit 400 can generate and send a low-level mirror enable signal Mir to the buffer circuit 100, and can generate and send a high-level mirror enable reverse signal Mirb to the buffer circuit 100. At this time, the CA buffer circuits are not exchanged for mirroring.

[0097] It should also be noted that the CA13 pin is specified in the DDR5 SPEC and is only used as the R17 address bit when the capacity is 64Gb, or in a three-dimensional stacking process. When the capacity and process determine that CA13 is not needed, the CA13 buffer circuit can be normally closed, thereby saving circuit power consumption. At the same time, when entering the mirror mode, since the CA12 buffer circuit needs to be mirrored and exchanged with the CA13 buffer circuit, the CA12 buffer circuit can be normally closed at this time.

[0098] In one embodiment, see Figure 2 The memory further includes a command address inversion (CAI) pin 500. The command address inversion pin 500 is connected to the buffer circuit 100 and is used to send a command address inversion signal Cai to the buffer circuit 100.

[0099] When the CAI pin is connected to the power supply voltage VDDQ, the command address inversion signal Cai is sent to the buffer circuit 100 as a high-level signal, indicating that the command address inversion mode is to be entered. At the same time, the signals outputted by all CA buffer circuits in the SPEC truth table when entering the command address inversion mode are inverted. For example, when the command address inversion mode is not entered, in the SPEC truth table, the data on the CS_N pin corresponds to a low level L, and the data outputted by the CA buffer circuit corresponding to the CA0 to CA4 pins (i.e., the CA0 to CA4 buffer circuit) corresponds to a high level H, which represents the command of "exiting the power-down mode". When entering the command address inversion mode, in the SPEC truth table, the data on the CS_N pin corresponds to a low level L, and the data outputted by the CA buffer circuit corresponding to the CA0 to CA4 pins (i.e., the CA0 to CA4 buffer circuit) corresponds to a low level L, which represents the command of "exiting the power-down mode".

[0100] When the CAI pin is connected to the power supply voltage VSS, the command address inversion signal Cai sent to the buffer circuit 100 is a low level signal, indicating that the command address inversion mode is not entered.

[0101] In one embodiment, a buffer circuit applied to a memory is provided.

[0102] The buffer circuit 100 includes a CA0 buffer circuit, a CA1 buffer circuit, a CA2 buffer circuit, a CA3 buffer circuit, and a CA4 buffer circuit.

[0103] See also Figure 3 The CA0 buffer circuit, the CA1 buffer circuit, the CA2 buffer circuit, the CA3 buffer circuit and the CA4 buffer circuit all include a first command address input terminal 111, a first circuit output terminal 112, a first comparator 113 and a first voltage output circuit 114.

[0104] At the same time, as an example, the command address buffer circuit also includes CA5 to CA11 buffer circuits, and the CA5 to CA11 buffer circuits have the same circuit structure as the CA0 to CA4 buffer circuits. Of course, in the CA5 to CA11 buffer circuits, part (such as the CA5 buffer circuit) may have the same circuit structure as the CA0 to CA4 buffer circuits, and the other part (such as the CA6 to CA11 buffer circuit) may have a different circuit structure from the CA0 to CA4 buffer circuits. Alternatively, the CA5 to CA11 buffer circuits may also have different circuit structures from the CA0 to CA4 buffer circuits. This is not limited here.

[0105] The first command address input terminal 111 is connected to the CA pin. Different CA buffer circuits are connected to different CA pins.

[0106] For example, the first command address input terminal 111 of the CA0 buffer circuit is connected to the CA0 pin. The first command address input terminal 111 of the CA1 buffer circuit is connected to the CA1 pin. The first command address input terminal 111 of the CA2 buffer circuit is connected to the CA2 pin. The first command address input terminal 111 of the CA3 buffer circuit is connected to the CA3 pin.

[0107] The first circuit output terminal 112 is used to output a digital signal. The level of the digital signal output by the first circuit output terminal 112 can represent the data output by the CA buffer circuit.

[0108] The positive input terminal of the first comparator 113 is connected to the first command address input terminal 111, thereby receiving the voltage on the CA pin. At the same time, the negative input terminal of the first comparator 113 receives the reference signal. At this time, the output terminal of the first comparator 113 can output a digital signal according to the comparison between the analog voltage on the CA pin and the analog voltage of the reference signal.

[0109] At the same time, the output terminal of the first comparator 113 is connected to the first circuit output terminal 112, so that the first circuit output terminal 112 can output a digital signal.

[0110] The enable terminal of the first comparator 113 can be connected to the command address buffer control circuit 200, so as to receive the power-down enable signal En. After receiving the power-down enable signal En, the enable terminal of the first comparator 113 can be turned off and on according to the level of the power-down enable signal En.

[0111] For example, when the enable terminal of the first comparator 113 receives a high-level power-down enable signal En, the first comparator 113 may be turned on, and when the enable terminal of the first comparator 113 receives a low-level power-down enable signal En, the first comparator 113 may be turned off.

[0112] After the memory enters the power-down mode, the command address buffer control circuit 200 may generate a low-level power-down enable signal En, so that the first comparator 113 is turned off based on the level of the power-down enable signal.

[0113] After the memory exits the power-down mode, the command address buffer control circuit 200 may generate a high-level power-down enable signal En, so that the first comparator 113 is turned on based on the level of the power-down enable signal.

[0114] The first voltage output circuit 114 is used to output a high level voltage or a low level voltage to the first circuit output terminal after the memory enters the power-down mode.

[0115] As described above, when the memory enters the power-down mode, the first comparator 113 is turned off, thereby turning off the CA buffer circuit. At this time, the output end of the first comparator 113 cannot output a digital signal according to the comparison result between the voltage on the CA pin received by the positive input end of the first comparator 113 and the voltage of the reference signal. Therefore, the output end of the first comparator 113 cannot output a digital signal to the first circuit output end 112.

[0116] At this time, the first voltage output circuit 114 outputs a high level voltage or a low level voltage to the first circuit output terminal 112 , so that the first circuit output terminal 112 can output a digital signal even when the first comparator 113 is turned off.

[0117] Therefore, after applying low-level data to the CS_N pin, the digital signal data output by the first voltage output circuit 114 of the CA0 to CA4 buffer circuits is combined with the data on the CS_N pin to form a command to exit the power-down mode that complies with the SPEC truth table of the memory (such as DDR5) to be sent to the decoder circuit 300, so that the decoder circuit 300 can decode the command to exit the power-down mode and send the command to exit the power-down mode to the command address buffer control circuit 200. After receiving the command to exit the power-down mode decoded by the decoder circuit 300, the command address buffer control circuit 200 can generate a high-level power-down enable signal En, so that the first comparator 113 is turned on.

[0118] As an example, when the command address inversion mode is not enabled and the mirror mode is not enabled, if the power-down mode has been entered, the comparators in all CA buffer circuits are turned off. At this time, in the CA0 to CA4 buffer circuits, a high level voltage (high level voltage) can be output to the first circuit output terminal 112 through the first voltage output circuit 114, so that the digital signal output by the first circuit output terminal 112 is a high level signal.

[0119] At this time, after low-level data is applied to the CS_N pin, the digital signal data output by the first voltage output circuit 114 of the CA0 to CA4 buffer circuit is combined with the data on the CS_N pin to form a command to exit the power-down mode that complies with the SPEC truth table of the memory (such as DDR5).

[0120] As another example, when the command address inversion mode is enabled and the mirror mode is not enabled, if the power-down mode has been entered, the comparators in all CA buffer circuits are turned off. At this time, in the CA0 to CA4 buffer circuits, a low-level voltage can be output to the first circuit output terminal 112 through the first voltage output circuit 114, so that the digital signal output by the first circuit output terminal 112 is a low-level signal.

[0121] At this time, after low-level data is applied to the CS_N pin, the digital signal data output by the first voltage output circuit 114 of the CA0 to CA4 buffer circuit is combined with the data on the CS_N pin to form a command to exit the power-down mode in accordance with the SPEC truth table in the command address inversion mode.

[0122] In one embodiment, see Figure 3 The output voltage circuit 114 includes a first pull-up circuit 1141 and a first pull-down circuit 1142 .

[0123] The first pull-up circuit 1141 is connected to the first circuit output terminal 112 , and is configured to output a high level voltage to the first circuit output terminal 112 .

[0124] The first pull-down circuit 1142 is connected to the first circuit output terminal 112 and is used to output a low level voltage to the first circuit output terminal 112 .

[0125] At this time, a high level voltage and a low level voltage are output to the first circuit output terminal 112 through the first pull-up circuit 1141 and the first pull-down circuit 1142 respectively, so as to facilitate circuit control.

[0126] Of course, in other embodiments, the first circuit output terminal 112 may be connected to the same signal output terminal of the output voltage circuit 114 through the circuit design of the output voltage circuit 114. The signal output terminal may output a high level voltage when a high level voltage needs to be output, and may output a low level voltage when a low level voltage needs to be output.

[0127] In one embodiment, see Figure 3 The first pull-up circuit 1141 includes a first switch unit. One end of the first switch unit is connected to the first circuit output terminal 112, and the other end is connected to the high level voltage VDDQ.

[0128] The first switch unit may control whether the first pull-up circuit 1141 outputs a high level voltage.

[0129] As an example, the first switch unit may include a first P-type transistor T P1 The second P-type transistor T P2 .

[0130] The second P-type transistor T P2 The source of the first P-type transistor T P1 of the drain.

[0131] At the same time, the first P-type transistor T P1 The gate of the first P-type transistor T is connected to the power-down enable signal En, P1 The source of the second P-type transistor T is connected to the high level voltage VDDQ. P2The gate of the second P-type transistor T is connected to the command address inversion signal Cai. P2 The drain of is connected to the first circuit output terminal 112.

[0132] When entering the power-down mode, the power-down enable signal En is at a low level. P1 Conductivity.

[0133] Meanwhile, if in the non-command address inversion mode, the command address inversion signal Cai is at a low level. P2 Therefore, at this time, the first P-type transistor T P1 The high level voltage VDDQ connected to the source of the first circuit will be transmitted to the first circuit output terminal 112, so that the first circuit output terminal 112 can output a high level signal.

[0134] At this time, the high level signal outputted by the first circuit output terminal 112 of the CA0 to CA4 buffer circuits may be combined with the low level data on the CS_N pin to form a command for exiting the power-down mode in accordance with the SPEC truth table.

[0135] If in the command address inversion mode, the command address inversion signal Cai is at a high level. P2 Therefore, at this time, the first P-type transistor T P1 The high level voltage VDDQ connected to the source of will not be transmitted to the first circuit output terminal 112. The first circuit output terminal 112 can receive the low level signal provided by the first pull-down circuit 1142.

[0136] At this time, the low level signal outputted by the first circuit output terminal 112 of the CA0 to CA4 buffer circuits may be combined with the low level data on the CS_N pin to form a command to exit the power-down mode in accordance with the SPEC truth table in the command address inversion mode.

[0137] When the power-down mode is exited, the power-down enable signal En is at a high level. P1 Therefore, regardless of whether it is in the command address inversion mode, the first P-type transistor T P1 The high level voltage VDDQ connected to the source of the first circuit will not be transmitted to the first circuit output terminal 112. At the same time, the first pull-down circuit 1142 can be set not to output a low level signal to the first circuit output terminal 112 based on the power-down enable signal En being at a high level. At the same time, after exiting the power-down mode, the first comparator 113 is turned on, so that the first circuit output terminal 112 can receive the voltage signal output by the first comparator 113 according to the CA pin.

[0138] In one embodiment, see Figure 3The first pull-down circuit 1142 includes a second switch unit. One end of the second switch unit is connected to the first circuit output terminal 112, and the other end is connected to the low level voltage VSS. The low level voltage VSS is, for example, a ground voltage.

[0139] The second switch unit can control whether the low level voltage of the first pull-down circuit 1142 is output.

[0140] As an example, the second switch unit may include a first N-type transistor T N1 The second N-type transistor T N2 .

[0141] The second N-type transistor T N2 The source of the first N-type transistor T N1 of the drain.

[0142] At the same time, the first N-type transistor T N1 The gate of the first N-type transistor T is connected to the command address inversion signal Cai. N1 The source of the second N-type transistor T is connected to the low level voltage VSS. N2 The gate of the second N-type transistor T is connected to the power-down enable reverse signal Enb, N2 The drain of is connected to the first circuit output terminal 112.

[0143] When entering the power-down mode, the power-down enable reverse signal Enb is at a high level. N2 Conductivity.

[0144] At the same time, if in the command address inversion mode, the command address inversion signal Cai is at a high level. N1 Therefore, at this time, the first N-type transistor T N1 The low level voltage VSS connected to the source of the first circuit will be transmitted to the first circuit output terminal 112, so that the first circuit output terminal 112 can output a low level signal.

[0145] At this time, the low level signal outputted by the first circuit output terminal 112 of the CA0 to CA4 buffer circuits may be combined with the low level data on the CS_N pin to form a command to exit the power-down mode in accordance with the SPEC truth table in the command address inversion mode.

[0146] If in the non-command address inversion mode, the command address inversion signal Cai is at a low level. N1 Therefore, at this time, the first N-type transistor T N1 The low level voltage VSS connected to the source of the first pull-up circuit 1141 will not be transmitted to the first circuit output terminal 112. The first circuit output terminal 112 can receive the high level signal provided by the first pull-up circuit 1141.

[0147] At this time, the high level signal outputted by the first circuit output terminal 112 of the CA0 to CA4 buffer circuits may be combined with the low level data on the CS_N pin to form a command for exiting the power-down mode in accordance with the SPEC truth table.

[0148] When the power-down mode is exited, the power-down enable reverse signal Enb is at a low level. N2 Therefore, regardless of whether it is in the command address inversion mode, the first N-type transistor T N1 The low level voltage VSS connected to the source of the first circuit output terminal 112 will not be transmitted to the first circuit output terminal 112. At the same time, the first pull-up circuit 1141 can be set to not output a high level signal to the first circuit output terminal 112 based on the power-down enable reverse signal Enb being at a high level. At the same time, after exiting the power-down mode, the first comparator 113 is turned on, so that the first circuit output terminal 112 can receive the voltage signal output by the first comparator 113 according to the CA pin.

[0149] In one embodiment, the command address buffer circuit further includes a CA12 buffer circuit and a CA13 buffer circuit.

[0150] See also Figure 4 The CA12 buffer circuit includes a second command address input terminal 121, a second circuit output terminal 122, a second comparator 123 and a second voltage output circuit 124.

[0151] The second command address input terminal 121 is connected to the CA12 pin. The second circuit output terminal 122 is used to output a digital signal. The level of the digital signal output by the second circuit output terminal 122 can represent the data output by the CA12 buffer circuit.

[0152] The positive input terminal of the second comparator 123 is connected to the second command address input terminal 121, thereby receiving the voltage on the CA12 pin. The negative input terminal of the second comparator 123 is used to input a reference signal. At this time, the output terminal of the second comparator 123 can output a digital signal according to the comparison between the analog voltage on the CA12 pin and the analog voltage of the reference signal.

[0153] At the same time, the output terminal of the second comparator 123 is connected to the second circuit output terminal 122, so that the second circuit output terminal 122 can output a digital signal.

[0154] The enable terminal of the second comparator 123 is connected to the second enable signal. The level of the second enable signal is high when exiting the power-down mode and in the non-mirror mode, and is low in other cases. When the level of the second enable signal is high, the second comparator 123 is turned on. When the level of the second enable signal is low, the second comparator 123 is turned off. Therefore, at this time, the second comparator 123 will only be turned on when exiting the power-down mode and in the non-mirror mode. Otherwise, when entering any mode of the power-down mode and the mirror mode, the second comparator 123 will be turned off.

[0155] The second voltage output circuit 124 is used to output a high level voltage or a low level voltage to the second circuit output terminal 122 after the memory enters the power-down mode.

[0156] See also Figure 5 The CA13 buffer circuit includes a third command address input terminal 131, a third circuit output terminal 132, a third comparator 133 and a third voltage output circuit 134.

[0157] The third command address input terminal 131 is connected to the CA13 pin. The third circuit output terminal 132 is used to output a digital signal. The level of the digital signal output by the third circuit output terminal 132 can represent the data output by the CA13 buffer circuit.

[0158] The positive input terminal of the third comparator 133 is connected to the third command address input terminal 131, thereby receiving the voltage on the CA13 pin. The negative input terminal of the third comparator 133 is used to input a reference signal. At this time, the output terminal of the third comparator 133 can output a digital signal according to the comparison between the analog voltage on the CA13 pin and the analog voltage of the reference signal.

[0159] At the same time, the output terminal of the third comparator 133 is connected to the third circuit output terminal 132 , so that the third circuit output terminal 132 can output a digital signal.

[0160] The enable terminal of the third comparator 133 is connected to the third enable signal. The level of the third enable signal is high when exiting the power-down mode and in the mirror mode, and is low in other cases. When the level of the second enable signal is high, the third comparator 133 is turned on. When the level of the second enable signal is low, the third comparator 133 is turned off. Therefore, at this time, the third comparator 133 will only be turned on when exiting the power-down mode and in the mirror mode. Otherwise, when entering any mode of the power-down mode and the non-mirror mode, the second comparator 123 will be turned off.

[0161] The third voltage output circuit 134 is used to output a high level voltage or a low level voltage to the third circuit output terminal 132 after the memory enters the power-down mode.

[0162] In this embodiment, by connecting the second enable signal to the enable terminal of the second comparator 123 and connecting the third enable signal to the enable terminal of the third comparator 133, both the CA12 buffer circuit and the CA13 buffer circuit can be turned off after entering the power-down mode, thereby saving power consumption.

[0163] At the same time, after exiting the power-down mode, if in the non-mirror mode, the CA12 buffer circuit is turned on and the CA13 buffer circuit is turned off; if in the mirror mode, the CA13 buffer circuit is turned on and the CA12 buffer circuit is turned off, so that the CA13 buffer circuit and the CA12 buffer circuit can be effectively mirror-swapped. At the same time, when the capacity and process determine that the CA13 pin is not needed, the CA13 buffer circuit can be normally closed in the non-mirror mode, and the CA12 buffer circuit that is mirror-swapped with the CA13 buffer circuit can be normally closed in the mirror mode, thereby further saving power consumption.

[0164] At the same time, similar to the first voltage output circuit 114 provided in the CA0 to CA4 buffer circuits, the second voltage output circuit 124 is provided in the CA12 buffer circuit, and the third voltage output circuit 134 is provided in the CA13 buffer circuit. At this time, in the non-mirror mode, the second circuit output terminal 122 can output a digital signal even when the second comparator 123 is turned off due to entering the power-down mode. And in the mirror mode, the third circuit output terminal 132 can output a digital signal even when the third comparator 133 is turned off due to entering the power-down mode.

[0165] In one embodiment, see Figure 6 The CA12 buffer circuit further includes a NOR gate 125. Two output terminals of the NOR gate 125 are respectively connected to the power-off enable reverse signal Enb and the mirror enable signal Mir, and the output terminal is used to output the second enable signal to the enable terminal of the second comparator 123.

[0166] At this time, the level of the power-down enable reverse signal Enb is high when entering the power-down mode and low when exiting the power-down mode. The level of the mirror enable signal Mir is high when entering the mirror mode and low when entering the non-mirror mode.

[0167] Therefore, at this time, the setting of the NOR gate 125 can effectively achieve that the level of the second enable signal is high when exiting the power-down mode and in the non-mirror mode, and is low in other cases.

[0168] In one embodiment, see Figure 7The CA13 buffer circuit further includes an AND gate 135, two output ends of the AND gate 135 are respectively connected to the power-off enable signal En and the mirror enable signal Mir, and the output end is used for the enable end of the third comparator 133 to output the third enable signal.

[0169] At this time, the level of the power-down enable signal En is low when entering the power-down mode, and is high when exiting the power-down mode. The level of the mirror enable signal Mir is high when entering the mirror mode, and is low when entering the non-mirror mode.

[0170] Therefore, at this time, the setting of the AND gate 135 can effectively achieve that the level of the third enable signal is high when exiting the power-down mode and in the mirror mode, and is low in other cases.

[0171] In one embodiment, see Figure 4 The second voltage output circuit 124 includes a second pull-up circuit 1241 and a second pull-down circuit 1242 .

[0172] The second pull-up circuit 1241 includes a third P-type transistor T P3 The fourth P-type transistor T P4 .

[0173] The third P-type transistor T P3 The gate of the third P-type transistor T is connected to the power-down enable signal En. P3 The source of the fourth P-type transistor T is connected to the high level voltage VDDQ. P4 The gate of the fourth P-type transistor T is connected to the command address inversion signal Cai. P4 The source of the fourth P-type transistor T is connected to the drain of the third P-type transistor. P4 The drain is connected to the second circuit output terminal 122.

[0174] The working principle of the second pull-up circuit 1241 is similar to that of the first pull-up circuit 1141 , and will not be described in detail here.

[0175] The second pull-down circuit 1242 includes a third N-type transistor T N3 , the fourth N-type transistor T N4 and a fifth N-type transistor T N5 .

[0176] The third N-type transistor T N3 The gate of the third N-type transistor T is connected to the command address inversion signal Cai. N3 The source of the fourth N-type transistor T is connected to the low level voltage VSS. N4 The gate of the fourth N-type transistor T is connected to the power-down enable reverse signal Enb, N4 The source of the third N-type transistor T N3The drain of the fourth N-type transistor T N4 The drain is connected to the second circuit output terminal 122.

[0177] The third N-type transistor T of the second pull-down circuit 1242 N3 The working principle is similar to that of the first N-type transistor T of the first pull-down circuit 1241. N The working principle of the fourth N-type transistor T of the second pull-down circuit 1242 is similar. N4 The working principle is similar to that of the second N-type transistor T of the first pull-down circuit 1241. N2 The working principle is similar and will not be described here.

[0178] The fifth N-type transistor T N5 The gate of the fifth N-type transistor T is connected to the mirror enable signal Mir. N5 The source of the fifth N-type transistor T is connected to the low level voltage VSS. N5 The drain is connected to the second circuit output terminal 122.

[0179] The level of the mirror enable signal Mir is high when entering the mirror mode, and is low when entering the non-mirror mode. The low level voltage VSS may be a ground voltage.

[0180] Therefore, when entering the mirror mode, the fifth N-type transistor T N5 The second circuit output terminal 122 may be grounded, thereby effectively reducing the power consumption of the CA12 buffer circuit.

[0181] In one embodiment, see Figure 5 The third voltage output circuit 134 includes a third pull-up circuit 1341 and a third pull-down circuit 1342 .

[0182] The third pull-up circuit 1341 includes a fifth P-type transistor T P5 and a sixth P-type transistor T P6 .

[0183] The fifth P-type transistor T P5 The gate of the fifth P-type transistor T is connected to the power-down enable signal En. P5 The source is connected to the high level voltage VDDQ.

[0184] The sixth P-type transistor T P6 The gate of the sixth P-type transistor T is connected to the command address inversion signal Cai. P6 The source of the fifth P-type transistor T P5 The drain of the sixth P-type transistor T P6 The drain is connected to the third circuit output terminal 134.

[0185] The working principle of the third pull-up circuit 1341 is similar to that of the first pull-up circuit 1141 , which will not be described in detail here.

[0186] The third pull-down circuit 1342 includes a sixth N-type transistor T N6 , the seventh N-type transistor T N7 and an eighth N-type transistor T N8 .

[0187] The sixth N-type transistor T N6 The gate of the sixth N-type transistor T is connected to the command address inversion signal Cai. N6 The source of the seventh N-type transistor T is connected to the low level voltage VSS. N7 The gate of the seventh N-type transistor T is connected to the power-down enable reverse signal Enb, N7 The source of the sixth N-type transistor T N6 The drain of the seventh N-type transistor T N7 The drain is connected to the third circuit output terminal 134.

[0188] The sixth N-type transistor T of the third pull-down circuit 1342 N6 The working principle is similar to that of the first N-type transistor T of the first pull-down circuit 1241. N The seventh N-type transistor T of the second pull-down circuit 1242 is similar to the working principle. N7 The working principle is similar to that of the second N-type transistor T of the first pull-down circuit 1241. N2 The working principle is similar and will not be described here.

[0189] The eighth N-type transistor T N8 The gate of the eighth N-type transistor T is connected to the mirror enable reverse signal Mirb. N8 The source of the eighth N-type transistor T is connected to the low level voltage VSS. N8 The drain is connected to the third circuit output terminal 134.

[0190] The level of the mirror enable reverse signal Mirb is low when entering the mirror mode, and is high when entering the non-mirror mode. The low level voltage VSS may be a ground voltage.

[0191] Therefore, when entering the non-mirror mode, the eighth N-type transistor T N8 The third circuit output terminal 134 may be grounded, thereby effectively reducing the power consumption of the CA13 buffer circuit.

[0192] In the description of this specification, the description with reference to the terms "one embodiment", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0193] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0194] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A buffer circuit, applied to a memory, characterized in that: It includes a CA0 buffer circuit, a CA1 buffer circuit, a CA2 buffer circuit, a CA3 buffer circuit and a CA4 buffer circuit, wherein the CA0 buffer circuit, the CA1 buffer circuit, the CA2 buffer circuit, the CA3 buffer circuit and the CA4 buffer circuit all include: A first command address input terminal is connected to a command address pin, and different CA buffer circuits are connected to different command address pins; A first circuit output terminal, used for outputting a digital signal; a first comparator, wherein a positive input terminal is connected to the first command address input terminal, a reverse input terminal receives a reference signal, an enable terminal receives a power-down enable signal, and an output terminal is connected to the first circuit output terminal; after the memory enters the power-down mode, the first comparator is turned off based on the level of the power-down enable signal; The first voltage output circuit is used to output a high level voltage or a low level voltage to the first circuit output terminal after the memory enters the power-down mode.

2. The buffer circuit according to claim 1, characterized in that: The output voltage circuit comprises: A first pull-up circuit, connected to the first circuit output end, and configured to output the high level voltage to the first circuit output end; The first pull-down circuit is connected to the output end of the first circuit and is used to output the low-level voltage to the output end of the first circuit.

3. The buffer circuit according to claim 2, characterized in that: The first pull-up circuit comprises: A first switch unit has one end connected to the output end of the first circuit and the other end connected to the high level voltage.

4. The buffer circuit according to claim 3, characterized in that: The first switch unit comprises: A first P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage; The second P-type transistor has a gate connected to the command address inversion signal, a source connected to the drain of the first P-type transistor, and a drain connected to the output end of the first circuit.

5. The buffer circuit according to claim 2, characterized in that: The first pull-up circuit comprises: A second switch unit has one end connected to the output end of the first circuit and the other end connected to the low level voltage.

6. The buffer circuit according to claim 5, characterized in that: The second switch unit comprises: A first N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage; The second N-type transistor has a gate connected to a power-off enable reverse signal, a source connected to the drain of the first N-type transistor, and a drain connected to the output end of the first circuit. The power-off enable reverse signal has a level opposite to that of the power-off enable signal.

7. The buffer circuit according to any one of claims 1 to 6, characterized in that: The command address buffer circuit also includes a CA12 buffer circuit and a CA13 buffer circuit. The CA12 buffer circuit comprises: The second command address input terminal is connected to the CA12 pin; The second circuit output terminal is used to output a digital signal; A second comparator, wherein the positive input terminal is connected to the second command address input terminal, the reverse input terminal is used to input a reference signal, the output terminal is connected to the second circuit output terminal, and the enable terminal is connected to a second enable signal, wherein the level of the second enable signal is high when exiting the power-down mode and in the non-mirror mode, and is low in other cases; a second voltage output circuit, configured to output the high level voltage or the low level voltage to the second circuit output terminal after the memory enters a power-down mode; The CA13 buffer circuit comprises: The third command address input terminal is connected to the CA13 pin; The third circuit output terminal is used to output a digital signal; A third comparator, wherein the positive input terminal is connected to the third command address input terminal, the reverse input terminal is used to input a reference signal, the output terminal is connected to the third circuit output terminal, and the enable terminal is connected to a third enable signal, the level of the third enable signal is high when exiting the power-down mode and in the mirror mode, and is low in other cases; The third voltage output circuit is used to output the high level voltage or the low level voltage to the output terminal of the third circuit after the memory enters the power-down mode.

8. The buffer circuit according to claim 7, characterized in that: The CA12 buffer circuit also includes a NOR gate, two output ends of which are respectively connected to the power-off enable reverse signal and the mirror enable signal, and the output end is used to output the second enable signal to the enable end of the second comparator.

9. The buffer circuit according to claim 7, characterized in that: The CA13 buffer circuit also includes an AND gate, two output ends of the AND gate are respectively connected to a power-off enable signal and a mirror enable signal, and the output end is used for the enable end of the third comparator to output the third enable signal.

10. The buffer circuit according to claim 7, characterized in that: The second voltage output circuit includes a second pull-up circuit and a second pull-down circuit. The second pull-up circuit comprises: A third P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage; a fourth P-type transistor, having a gate connected to the command address inversion signal, a source connected to the drain of the third P-type transistor, and a drain connected to the output end of the second circuit; The second pull-down circuit comprises: A third N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage; a fourth N-type transistor, having a gate connected to a power-off enable reverse signal, a source connected to a drain of the third N-type transistor, and a drain connected to an output end of the second circuit, wherein the power-off enable reverse signal is a reverse signal of the power-off enable signal; A fifth N-type transistor has a gate connected to the mirror enable signal, a source connected to the low level voltage, and a drain connected to the output end of the second circuit.

11. The buffer circuit according to claim 7, characterized in that: The third voltage output circuit includes a third pull-up circuit and a third pull-down circuit. The third pull-up circuit comprises: a fifth P-type transistor, a gate of which is connected to the power-down enable signal, and a source of which is connected to the high-level voltage; a sixth P-type transistor, whose gate is connected to the command address inversion signal, whose source is connected to the drain of the fifth P-type transistor, and whose drain is connected to the output end of the third circuit; The third pull-down circuit comprises: A sixth N-type transistor, a gate of which is connected to the command address inversion signal, and a source of which is connected to the low level voltage; a seventh N-type transistor, wherein the gate is connected to the power-off enable reverse signal, the source is connected to the drain of the sixth N-type transistor, the drain is connected to the output end of the third circuit, and the power-off enable reverse signal has a level opposite to that of the power-off enable signal; An eighth N-type transistor, having a gate connected to a mirror enable reverse signal, a source connected to the low level voltage, and a drain connected to the output end of the third circuit, wherein the mirror enable reverse signal has a level opposite to that of the mirror enable signal.

12. The buffer circuit according to claim 1, wherein: The command address buffer circuit further includes a CA5 to CA11 buffer circuit, and the CA5 to CA11 buffer circuit has the same circuit structure as the CA0 to CA4 buffer circuit.

13. A memory, characterized in that: include: The buffer circuit according to any one of claims 1 to 12; A command address buffer control circuit, connected to the buffer circuit, and configured to output the power-down enable signal to the buffer circuit; The decoder circuit is connected to the command address buffer control circuit and is used to send a power-down mode exit command to the command address buffer control circuit.

14. The memory according to claim 13, characterized in that: The memory also includes: The address mirror circuit is connected to the buffer circuit and is used to send a mirror enable signal to the buffer circuit.

15. The memory according to claim 13, characterized in that: The memory also includes: A command address inversion pin is connected to the buffer circuit and is used to send a command address inversion signal to the buffer circuit.

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