A dynamically reconfigurable memristor array and its preparation method

Abstract

The application relates to a dynamically reconfigurable memristor array and a preparation method thereof, and belongs to the technical fields of semiconductor memristor, integrated circuit and control circuit. The application provides a dynamically reconfigurable memristor array, which can realize the reconfiguration of different array structures dynamically by only switching the peripheral circuit mode through the combination of a memristor chip and a peripheral circuit, including adjusting the number of rows or columns of the memristor array, changing the relative position of a single array point in the memristor array, and changing other electrical devices such as diodes, transistors or selectors in series in the array point. The application realizes the memristor array with different structures by firstly preparing independent memristor devices on a single substrate, then packaging the memristor devices and connecting them into the dynamically reconfigurable peripheral circuit. The application can more flexibly realize the requirements of the memristor array under the same number of memristors, so as to better adapt to the requirements of various neural morphological calculations in artificial neural networks or other memory-computing integrated systems.

Description

Technical Field

[0001] The present invention belongs to semiconductor memristor technology and integration and control circuit technology, and more specifically, relates to a dynamically reconfigurable memristor array and a preparation method thereof. Background Art

[0002] With the rapid development of the Internet of Things, big data, and cloud computing, the wave of information and intelligentization is sweeping the globe. Research and application in artificial neural networks, integrated storage and computing, and artificial intelligence are also deepening. Due to their unique electrical properties, memristors are crucial electrical components for fully hardware-based artificial intelligence neural network systems. In fully hardware-based artificial neural network systems, memristor arrays are responsible for scaling and mapping artificial synaptic weights and performing a large number of fundamental neuromorphic computations, such as vector matrix multiplication (VMM). Therefore, different artificial neural network architectures and different neural computing functions typically require different memristor arrays to implement different structures. Traditional static memristor arrays, on the other hand, often fabricate and connect all memristor devices on the same substrate. Therefore, once the static memristor array is fabricated, the array structure cannot be changed. If a different memristor array structure is required within the same system, or if the existing memristor device is found to not meet the current requirements during testing, the existing memristor array will become incompatible, necessitating the fabrication of new devices and the planning of a new array structure. Summary of the Invention

[0003] The present invention aims to provide a dynamically reconfigurable memristor array. The memristor array comprises independent memristor devices and peripheral circuits, with any one of the memristor devices selectively connected to the peripheral circuits. By selecting the peripheral circuit connection mode, the structure of the memristor array can be dynamically changed. The memristor array of the present invention can be reconfigured to accommodate different neuromorphic computing requirements without requiring the production of new memristor devices. This solves the technical problem in prior art where the structure of static memristor arrays cannot be changed after fabrication.

[0004] According to a first aspect of the present invention, a dynamically reconfigurable memristor array is provided, wherein the memristor array includes independent memristor devices and peripheral circuits, wherein any one of the memristor devices comprises, from top to bottom, a top electrode, a resistive layer, and a bottom electrode, wherein the top electrode and the bottom electrode of any one of the memristor devices are used to connect to a chip carrier, wherein the pins of the chip carrier are selectively connected to the peripheral circuit via a multi-way switch, and the chip carrier can dynamically change the structure of the memristor array by switching between different connection modes with the peripheral circuit.

[0005] Preferably, the structure of the array of memristors is the number of rows of the array, the number of columns of the array, the relative position of the array points, or whether there is a series electrical element on the array points of the array.

[0006] Preferably, when the array of memristors includes 4 memristor devices, the array of memristors is a 4x1 array of memristors or a 2x2 array of memristors.

[0007] Preferably, when the array of memristors includes 9 memristor devices, the array of memristors is a 9x1 array of memristors or a 3x3 array of memristors.

[0008] Preferably, when the array of memristors includes 12 memristor devices, the array of memristors is a 3x4 array of memristors or a 2x6 array of memristors.

[0009] Preferably, the electrical element is a transistor, a selector, or a diode.

[0010] According to another aspect of the present application, there is provided a method for preparing any one of the dynamically reconfigurable arrays of memristors, comprising the following steps:

[0011] (1) preparing a plurality of memristor devices independently on a substrate and packaging them onto a chip carrier, the top electrode and the bottom electrode of each of the memristor devices being connected to the chip carrier, respectively;

[0012] (2) selectively connecting the pins of the chip carrier in step (1) to a peripheral circuit through a multiplexer; connecting the plurality of memristor devices to build arrays of memristors of different structures according to different connection modes of the peripheral circuit and the chip carrier.

[0013] Preferably, in step (1), the memristor devices have a Crossbar architecture.

[0014] Preferably, in step (2), the peripheral circuit is a printed circuit board.

[0015] Preferably, in step (2), the connection mode of the chip carrier and the peripheral circuit is gold ball bonding, chip mounting, or conductive silver paste connection.

[0016] In summary, compared with the prior art, the above technical solutions conceived by the present application can at least achieve the following beneficial effects:

[0017] (1) The present invention proposes a dynamically reconfigurable memristor array, consisting of memristor devices and peripheral circuits. This allows for the realization of different memristor array structures with a fixed number of memristors simply by switching the peripheral circuit mode, without re-fabricating new memristor devices. Furthermore, array point replacement can be more conveniently achieved when a small number of memristor devices are damaged. This effectively adapts to various neuromorphic computing requirements and different artificial neural network models, improving the memristor array's compatibility with the non-ideal characteristics of memristors. This is of great significance for the implementation and related testing of full-hardware artificial neural networks.

[0018] (2) The present invention provides a dynamically reconfigurable memristor array. Compared to traditional static memristor arrays, this array has dynamic reconfigurability. After preparation, the array structure can be changed by switching the peripheral circuit connection mode.

[0019] (3) The memristor array provided by the present invention can maximize the functionality of different memristor array structures, even with a limited number of memristor devices. It can also utilize different VMM operations under different artificial neural network models, thus determining the direction of future large-scale memristor array integration structural design. This allows the array to have the flexibility to adapt to different computational requirements and has a positive impact on the design stage of more complex artificial neural network arrays.

[0020] (4) In traditional memristor arrays, if a single device fails, the entire array will lose its function. However, the memristor array provided by the present invention can be easily connected to other healthy, undamaged devices by coordinating with peripheral circuits, even if a small number of devices fail, thereby improving the service life and compatibility of the entire array.

[0021] (5) The memristor array provided by the present invention can test and screen the prepared memristor devices, and then select appropriate devices to connect to the peripheral circuit. This can, to a certain extent, accommodate the non-ideal characteristics of the devices and improve the accuracy of neuromorphic computing.

[0022] (6) The memristor array provided by the present invention allows for the connection of electronic components with different functions at each array point. This enables the memristor array to have more diverse functions, such as leakage current suppression, threshold excitation, and scaling mapping, thus further enriching the array's control capabilities.

[0023] (7) The memristor array implementation method provided by the present invention is applicable to memristor devices made of various materials and has strong universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of a traditional fixed memristor array.

[0025] Figure 2 Schematic diagram of the dynamically reconfigurable memristor array of the present invention.

[0026] Figure 3 Schematic diagram of the structure of the memristor chip in Example 1.

[0027] Figure 4 1 is an equivalent circuit diagram after the peripheral circuit and the memristor chip are connected in Example 1.

[0028] Figure 5 4×1 memristor array equivalent circuit diagram in Example 1.

[0029] Figure 6 2×2 memristor array equivalent circuit diagram in Example 1.

[0030] Figure 7 1 is an equivalent circuit diagram of a 2×2 memristor array in which the relative positions of array points are changed in Example 1.

[0031] Figure 8 This is an equivalent circuit diagram of a 2×2 1S1R memristor array having a selection function by controlling a multi-way switch in Example 1.

[0032] Figure 9 This is the equivalent circuit diagram of the 9×1 memristor array in Example 2.

[0033] Figure 10 This is the equivalent circuit diagram of the 3×3 memristor array in Example 2.

[0034] Figure 11 This is an equivalent circuit diagram of a 3×3 memristor array in Example 2 in which the relative positions of array points are changed.

[0035] Figure 12 This is an equivalent circuit diagram of a 3×3 1D1R memristor array with a rectification effect achieved by adding diodes at array points in Example 2.

[0036] Figure 13 3 is a circuit diagram of the peripheral circuit in Example 3.

[0037] Figure 14 This is a schematic diagram of 3×4, 4×3, 2×6 and 6×2 memristor arrays implemented by inserting 12 devices as a group in Example 3. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0039] The traditional memristor array is integrated on a substrate. Therefore, after the preparation is completed, the memristor array structure cannot be changed through subsequent operations. The schematic diagram of the traditional static 2×2 memristor array is as follows Figure 1 shown.

[0040] The memristor array of the present invention is composed of two parts: independent memristor devices and dynamically reconfigurable peripheral circuits. By controlling the peripheral circuits, the structure of the original memristor array, the relative positions of array points, and other external electrical devices connected to the array points can be adjusted directly without rebuilding a new array. This helps to use the same memristor device in the same array module to test and apply the performance of different array structures.

[0041] The present invention can switch the connection mode of the peripheral circuit through switches or other control systems, so that each independent device can be connected into an array with different structures. Figure 2 As shown in Figure 1, a dynamically reconfigurable memristor array is implemented as follows:

[0042] (1) preparing memristor devices on a single substrate, performing electrical testing, and packaging memristor devices with good electrical performance and similar electrical behavior onto a chip carrier;

[0043] (2) designing and preparing a dynamically reconfigurable peripheral circuit, and connecting the chip carrier pins in (1) to the peripheral circuit;

[0044] (3) Selecting different connection modes of the peripheral circuits and connecting the memristor devices in different connection modes to realize memristor arrays with different structures.

[0045] The specific method for preparing the memristor in step (1) of the present invention is to use photolithography technology for patterning, and then use magnetron sputtering, pulsed laser deposition, electrochemical anodization and other methods to prepare the bottom electrode, resistive layer and top electrode of the memristor, and finally obtain a memristor device that is independent of each other and can be connected to a chip carrier.

[0046] Preferably, the structure of the memristor prepared in step (1) is a classic Crossbar structure, or other structures in which TE and BE can be connected to a chip carrier respectively.

[0047] The peripheral circuit in step (2) of the present invention has multiple modes for connecting to the memristor device, providing an interface for connecting a single array point to other electrical components, thus having dynamic reconfigurability. At the same time, the peripheral circuit can be conveniently connected to the chip carrier, and the connection mode can be switched by the control system.

[0048] Preferably, the peripheral circuit designed in step (2) is prepared into a PCB, and an interface is provided to allow the pins of the chip carrier to be directly inserted, while the transition between different connection modes of the peripheral circuit is achieved by switching switches.

[0049] Preferably, the connection method between the memristor device and the chip carrier in step (2) may include: gold wire ball bonding, chip mounting, conductive silver glue connection or other commonly used connection methods in the semiconductor field.

[0050] Preferably, the reconfigurability of the peripheral circuit in step (2) means that the peripheral circuit has different modes of circuit connection, can switch modes through switches or other control systems, provides an interface for connecting to a memristor chip carrier, and can optionally provide interfaces for other electrical devices connected to array points, such as transistors, selectors, diodes, etc.

[0051] Preferably, the different memristor array structures in step (3) represent at least one difference among the following three characteristics: the number of rows and columns of the array, the relative positions of the array points, and the electrical elements connected in series at each array point.

[0052] The following are specific embodiments

[0053] Example 1

[0054] This embodiment provides a method for implementing a dynamically reconfigurable array based on four oxide memristors, and by controlling the multiplexer switches of the peripheral circuits on a single-layer PCB, four different memristor array structures are implemented. The specific steps are as follows:

[0055] (1) Cleaning the silicon wafer substrate: Place the silicon wafer in acetone, ethanol, and deionized water in sequence, and ultrasonically clean it for 15 minutes each. After three cycles, blow dry it with a nitrogen gun and set aside.

[0056] (2) Preparation of memristor chip: After obtaining the bottom electrode pattern using photolithography technology on the substrate, the sample is placed on the tray of the magnetron sputtering chamber, the target material for depositing the bottom electrode is installed on the target source of the chamber, and the parameters are set. The corresponding material layer is obtained by sputtering and then debonding to obtain the bottom electrode. The same method is used to prepare the oxide resistive layer and the top electrode respectively, and 32 complete independent memristor devices are obtained, and finally a memristor chip is prepared. The structure of the memristor chip is as follows Figure 3 shown.

[0057] (3) Screening available memristor devices: The prepared memristor chip is placed in a semiconductor characteristic analysis system, and an electrical signal is applied through the connection of the probe of the probe station with the top and bottom electrodes of the device, so as to test the electrical performance. After the electrical test of 32 single devices on the memristor chip, 4 devices with stable and consistent resistance change behavior, similar pulse response performance are selected for standby;

[0058] (4) Welding and packaging of memristor chip and chip carrier: The memristor chip is packaged on the chip carrier using the gold wire bonding method. After initializing the wire bonding machine, the memristor array is bonded with the chip carrier using AB glue and placed on a tray, then the tray is placed in the input magazine and semi-automatically enters the welding workbench. Then clamp the tray, preheat the bottom of the chip, and set the welding parameters. After the gold wire is ignited and the ball is burned, the welding program is entered, the cross line of the interface is aligned with the metal surface to be welded, the bottom electrode and the top electrode of the device selected in step (3) are welded to the chip carrier. After the welding is completed, the memristor chip carrier is taken out.

[0059] (5) Preparation of peripheral circuit: The peripheral circuit is designed using Altium Designer software, and on the single-layer circuit diagram, each node is connected with a multi-way switch to control different connection modes of the peripheral circuit and provide an interface with the chip carrier. Figure 4 is the equivalent circuit diagram of the peripheral circuit connected with the memristor in Example 1. After the peripheral circuit is designed, a single-layer PCB is prepared according to the drawing.

[0060] (6) Array implementation: After the packaged memristor chip is inserted into the pin designed by the peripheral circuit, different arrays are realized by controlling the connection of the multi-way switch, which can realize a 4x1 memristor array, a 2x2 memristor array, a 2x2 memristor array with changed relative positions of array points, and a 2x2 one Selector one Resistor (1S1R) memristor array with selective function.

[0061] Figure 5 is the equivalent circuit diagram of the 4x1 memristor array in Example 1; Figure 6 is the equivalent circuit diagram of the 2x2 memristor array in Example 1; Figure 7 is the equivalent circuit diagram of the 2x2 memristor array with changed relative positions of array points in Example 1; Figure 8 is the equivalent circuit diagram of the 2x2 1S1R memristor array with selective function in Example 1 by controlling the multi-way switch.

[0062] Example 2

[0063] This embodiment provides a method for implementing a dynamically reconfigurable array based on nine oxide memristors, and by selecting the connections of peripheral circuits on different multi-layer PCBs, four different memristor array structures are implemented. The specific steps are as follows:

[0064] (1) Cleaning the silicon wafer substrate: Same as step (1) in Example 1

[0065] (2) Preparation of memristor chip: same as step (2) in Example 1

[0066] (3) Screening of good quality memristor devices: The same as step (3) in Example 1, but 9 devices with stable resistance switching behavior, good consistency and similar pulse response performance need to be selected for use.

[0067] (4) Welding and packaging of the memristor chip and the chip carrier: same as step (4) in Example 1

[0068] (5) Prepare peripheral circuits: Use Altium Designer software to design a multilayer peripheral circuit with four connection modes and an interface to the chip carrier. Prepare a multilayer PCB according to the drawings, with each layer of the PCB circuit representing a connection mode.

[0069] (6) Array implementation: After inserting the packaged memristor chip into the interface designed for the peripheral circuit, by selecting the peripheral circuits on different layers of the PCB, a 9×1 memristor array, a 3×3 memristor array, a 3×3 memristor array with a changed relative position of the array points, and a 3×3 one diode one resistor (1D1R) memristor array with a rectification effect achieved by connecting diodes in series with the array points can be realized.

[0070] Figure 9 is the equivalent circuit diagram of the 9×1 memristor array in Example 1; Figure 10 is the equivalent circuit diagram of the 3×3 memristor array in Example 1; Figure 11 is an equivalent circuit diagram of a 3×3 memristor array in Example 1 in which the relative positions of array points are changed; Figure 12 This is an equivalent circuit diagram of a 3×3 1D1R memristor array with a rectification effect achieved by adding diodes at array points in Example 1.

[0071] Example 3

[0072] The embodiment provides an implementation method of a dynamic reconfigurable memristor array with flexible selection of the number of memristor devices and array structure. The structure of the memristor array is determined by packaging single memristor devices and inserting the same into interfaces provided by a peripheral circuit, so that the number of rows and columns of the memristor array is not more than 10. The embodiment uses 12 packaged memristor devices to realize 3*4, 4*3, 2*6 and 6*2 memristor arrays. The specific steps are as follows:

[0073] (1) Preparing a single memristor device: according to the structure and material of the memristor, a batch of memristor devices are prepared on each clean substrate.

[0074] (2) Packaging the single memristor device: the memristor device is packaged, and the top electrode and the bottom electrode are connected to the DIP pin, respectively.

[0075] (3) Preparing a peripheral circuit array: a cross peripheral circuit array with ten rows and ten columns is designed, and an interface for connecting the packaged memristor device and an external electrical element is provided at the intersection of each row and each column of the peripheral circuit. Figure 13 is a circuit schematic diagram of the peripheral circuit in embodiment 3. The peripheral circuit is prepared on a PCB according to the design diagram.

[0076] (4) Realizing the memristor array: the packaged plurality of memristor single devices are inserted into the interfaces of the peripheral circuit, and an array with a certain structure is formed. According to the number of memristor devices and the position of the inserted memristor devices, any memristor array with the number of rows and columns less than or equal to 10 can be formed. Figure 14 is a schematic diagram of 3*4, 4*3, 2*6 and 6*2 arrays realized by inserting 12 devices in embodiment 3. The black dots represent a unit formed by a series connection of a memristor and a gating device (transistor, diode, selector, etc.), and the input and output of the corresponding array are selected, that is, different array structures are selected.

[0077] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A dynamically reconfigurable memristor array, characterized in that: The memristor array includes independent memristor devices and peripheral circuits. Any memristor device consists of a top electrode, a resistive layer, and a bottom electrode from top to bottom. The top electrode and bottom electrode of any memristor device are used to connect to a chip carrier. The pins of the chip carrier are selectively connected to the peripheral circuit through a multi-way switch. The chip carrier can dynamically change the structure of the memristor array by switching different connection modes with the peripheral circuit.

2. The dynamically reconfigurable memristor array according to claim 1, wherein: The structure of the memristor array includes the number of rows of the array, the number of columns of the array, the relative positions of array points, or whether electrical elements are connected in series at the array points of the array.

3. The dynamically reconfigurable memristor array according to claim 1, wherein: When the memristor array includes four memristor devices, the memristor array is a 4×1 memristor array or a 2×2 memristor array.

4. The dynamically reconfigurable memristor array according to claim 1, wherein: When the memristor array includes 9 memristor devices, the memristor array is a 9×1 memristor array or a 3×3 memristor array.

5. The dynamically reconfigurable memristor array according to claim 1, wherein: When the memristor array includes 12 memristor devices, the memristor array is a 3×4 memristor array or a 2×6 memristor array.

6. The dynamically reconfigurable memristor array according to claim 2, wherein: The electrical element is a transistor, a selector or a diode.

7. The method for preparing a dynamically reconfigurable memristor array according to any one of claims 1 to 6, wherein: The following steps are involved: (1) preparing a plurality of independent memristor devices on a substrate and packaging them on a chip carrier, wherein the top electrode and the bottom electrode of each memristor device are respectively connected to the chip carrier; (2) selectively connecting the pins of the chip carrier in step (1) to the peripheral circuit through a multi-way switch; and connecting a plurality of memristor devices according to different connection modes between the peripheral circuit and the chip carrier to construct memristor arrays with different structures.

8. The preparation method according to claim 7, wherein In step (1), the memristor device has a Crossbar architecture.

9. The preparation method according to claim 7, wherein In step (2), the peripheral circuit is a printed circuit board.

10. The preparation method according to claim 7, wherein In step (2), the chip carrier and the peripheral circuit are connected by gold wire ball welding, chip mounting or conductive silver glue.

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