Method for forming metal gate
By introducing a heavy ion implantation process before the metal gate is formed, a heavy ion doped layer with high wear resistance is formed, which solves the problem of high non-uniformity of the metal gate and improves the uniformity of the device's electrical performance.
Patent Information
- Application Number
- CN202310810906.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-04
- Publication Date
- 2025-01-10
AI Technical Summary
Existing technologies often result in butterfly-shaped defects during the formation of metal gates, leading to high non-uniformity of the metal gates and affecting the uniformity of device electrical performance.
Before forming the metal gate, a heavy ion implantation process is introduced to form a heavy ion doped layer, which changes the material properties of the dielectric layer, making it more wear-resistant and with a lower grinding rate, thereby avoiding the generation of butterfly defects and ensuring the uniformity of the metal gate height.
Heavy ion implantation improves the high uniformity of the metal gate, enhances the uniformity of the device's electrical performance, and avoids the generation of butterfly defects.
Smart Images
Figure CN119297079A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for forming a metal gate. Background Art
[0002] In recent years, CMOS devices are being miniaturized to smaller sizes in accordance with Moore's Law. Therefore, when preparing CMOS devices, maintaining and improving the uniformity of local device electrical properties has become a huge challenge for process engineers. Among them, it is required to maintain uniformity in the height of the metal gate to reduce the height difference between the gates, so as to improve the uniformity of local device electrical properties.
[0003] However, in the prior art, the formation of metal gates is often accompanied by the formation of dishing defects, which refer to defects with high sides and a concave middle that appear on the surface of the gate metal layer during the grinding process of the gate metal layer. The butterfly defect not only affects the surface flatness of the gate metal layer itself, but also leads to the non-uniformity of the height of the formed metal gate, thereby affecting the uniformity of the device electrical performance. Summary of the invention
[0004] The object of the present invention is to provide a method for forming a metal gate to avoid the generation of butterfly defects and thus improve the uniformity of electrical properties of local devices.
[0005] In order to solve the above technical problems, the present invention provides a method for forming a metal gate, which comprises: providing a substrate, forming a plurality of polysilicon pseudo gates on the substrate, and having a spacing space between two adjacent polysilicon pseudo gates; forming a dielectric layer, the dielectric layer filling the spacing space, and the upper surface of the dielectric layer is flush with the upper surface of the polysilicon pseudo gate; performing heavy ion implantation on a portion of the dielectric layer away from the substrate to form a heavy ion doped layer doped with heavy ions; removing the polysilicon pseudo gate to form a gate trench between two adjacent heavy ion doped layers; and forming a metal gate, the metal gate filling the gate trench.
[0006] Preferably, in the method for forming the metal gate, after forming the plurality of polysilicon dummy gates on the substrate, the method for forming the metal gate further comprises: forming a sidewall structure on the sidewalls of the plurality of polysilicon dummy gates.
[0007] Preferably, in the method for forming the metal gate, before forming the dielectric layer, the method for forming the metal gate also includes: forming a contact etch stop layer, wherein the contact etch stop layer covers the surface of the sidewall structure, the upper surface of the polysilicon pseudo gate, and the upper surface of the substrate on both sides of the sidewall structure.
[0008] Preferably, in the method for forming the metal gate, the method for forming the dielectric layer and making the upper surface of the dielectric layer flush with the upper surface of the polysilicon dummy gate includes: grinding the dielectric layer and stopping at the contact etch stop layer; and, simultaneously grinding the contact etch stop layer and the dielectric layer until the contact etch stop layer located on the upper surface of the polysilicon dummy gate is removed and stops at the upper surface of the polysilicon dummy gate.
[0009] Preferably, in the method for forming the metal gate, the method of performing heavy ion implantation on the portion of the dielectric layer away from the substrate comprises: performing heavy ion implantation on the portion of the dielectric layer away from the substrate by adopting a full ion implantation method.
[0010] Preferably, in the method for forming the metal gate, the heavy ions in the heavy ion implantation include silicon ions or germanium ions.
[0011] Preferably, in the method for forming the metal gate, the method for forming the metal gate includes: forming a gate metal layer, the gate metal layer filling the gate trench; and simultaneously grinding the gate metal layer and the heavy ion doping layer until the heavy ion doping layer is completely ground away, and finally the remaining gate metal layer serves as the metal gate.
[0012] Preferably, in the method for forming the metal gate, the method for forming the gate metal layer includes: filling the gate metal material in the gate groove and extending it to cover the upper surface of the heavy ion doped layer; grinding and removing the gate metal material on the upper surface of the heavy ion doped layer so that the upper surface of the remaining gate metal material is flush with the upper surface of the heavy ion doped layer to form the gate metal layer.
[0013] Preferably, in the method for forming the metal gate, the method for removing the polysilicon dummy gate is dry etching.
[0014] Preferably, in the method for forming the metal gate, grinding the dielectric layer, grinding the gate metal layer and grinding the heavy ion doped layer all adopt a chemical mechanical polishing method.
[0015] In summary, the present invention provides a method for forming a metal gate, the method comprising: providing a substrate, forming a plurality of polysilicon pseudo gates on the substrate, and having a spacing space between two adjacent polysilicon pseudo gates; forming a dielectric layer, the dielectric layer filling the spacing space, and the upper surface of the dielectric layer being flush with the upper surface of the polysilicon pseudo gate; performing heavy ion implantation on the portion of the dielectric layer away from the substrate, and forming a heavy ion doped layer doped with heavy ions; removing the polysilicon pseudo gate, so that a gate groove is formed between two adjacent heavy ion doped layers; and forming a metal gate, the metal gate filling the gate groove. Before forming the metal gate, a heavy ion implantation process is introduced to form a heavy ion doped layer, so as to change the material properties of the dielectric layer. Compared with the dielectric layer, the heavy ion doped layer has higher wear resistance and lower grinding rate, and is not easy to produce butterfly defects during the grinding process, thereby avoiding large height differences in the formation of the metal gate and improving the uniformity of the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a schematic diagram of butterfly defect;
[0017] Figures 2 to 7 It is a schematic diagram of the device structure corresponding to the steps of forming a metal gate in the prior art;
[0018] Figure 8 is a flow chart of forming a metal gate according to an embodiment of the present invention;
[0019] Fig. 9 is a schematic diagram of step S1 of forming a metal gate according to an embodiment of the present invention;
[0020] Fig.10 is a schematic diagram of step S2 of forming a metal gate according to an embodiment of the present invention;
[0021] Fig.11 is a schematic diagram of step S3 of forming a metal gate according to an embodiment of the present invention;
[0022] Fig.12 is a schematic diagram of step S4 of forming a metal gate according to an embodiment of the present invention;
[0023] Fig.13 is a schematic diagram of step S5 of forming a metal gate according to an embodiment of the present invention;
[0024] Fig.14 is a schematic diagram of forming a contact etch stop layer according to an embodiment of the present invention;
[0025] The reference numerals are as follows:
[0026] 20 - substrate; 21 - polysilicon pseudo gate; 22 - contact etching stop layer; 23 - spacing space; 24 - dielectric layer; 25 - heavy ion doping layer; 26 - gate trench; 27 - metal gate. DETAILED DESCRIPTION
[0027] As mentioned in the above background technology, the formation of metal gates in the prior art is often accompanied by the generation of butterfly defects. Figure 1 Due to the existence of the butterfly defect 17, when the metal gate 16 is formed, a metal layer will be formed at the position of the butterfly defect 17, causing a short circuit in the subsequent semiconductor device, thereby reducing the electrical performance of the semiconductor device; in addition, the butterfly defect 17 will also affect the formation height of the metal gate 16, thereby causing the height of the metal gate 16 to be non-uniform.
[0028] In view of the above problems, the applicant carefully studied the preparation process of forming a metal gate in the prior art, see Figures 2 to 7 The specific method includes the following steps: (1) forming a polysilicon pseudo gate 11 on a substrate 10, and depositing a contact etch stop layer 12 on the surface of the polysilicon pseudo gate 11 and the substrate 10; (2) depositing a dielectric layer 13 on the contact etch stop layer 12; (3) grinding the dielectric layer 13 until the polysilicon is exposed; (4) removing the polysilicon pseudo gate 11 to form a gate trench 14; (5) depositing a gate metal layer 15 on the dielectric layer 13, and filling the gate trench 14 with the gate metal layer 15; (6) grinding the gate metal layer 15 to form a metal gate 16.
[0029] After research and analysis by the applicant, the reasons for the formation of the metal gate 16 and the appearance of the butterfly defect 17 in the prior art include the low wear resistance of the dielectric layer 13 and the high grinding rate. During the grinding process, a butterfly defect 17 with a middle depression and high sides is easily formed. When the dielectric layer 13 and the gate metal layer 15 are simultaneously ground to form the metal gate 16, the formation height of the metal gate 16 is affected, and the height uniformity of the metal gate 16 is poor.
[0030] To this end, an embodiment of the present invention provides a method for forming a metal gate, see Figure 8 , the method for forming the metal gate comprises the following steps:
[0031] S1, providing a substrate, forming a plurality of polysilicon dummy gates on the substrate, and having a spacing space between two adjacent polysilicon dummy gates;
[0032] S2, forming a dielectric layer, wherein the dielectric layer fills the spacing space, and an upper surface of the dielectric layer is flush with an upper surface of the polysilicon pseudo gate;
[0033] S3, performing heavy ion implantation on a portion of the dielectric layer away from the substrate to form a heavy ion doped layer doped with heavy ions;
[0034] S4, removing the polysilicon dummy gate, so that a gate trench is formed between two adjacent heavy ion doped layers;
[0035] S5, forming a metal gate, wherein the metal gate fills the gate trench.
[0036] The method provided in an embodiment of the present invention introduces a heavy ion implantation process to form a heavy ion doping layer before forming the metal gate, thereby changing the material properties of the portion of the dielectric layer away from the substrate. The heavy ion doping layer has higher wear resistance than the dielectric layer and a relatively low grinding rate, and is less likely to produce butterfly defects that would occur in the prior art, thereby avoiding large differences in the height of the formed metal gate and improving the uniformity of the device's electrical performance.
[0037] The following combination Figures 9 to 14 The method for forming a metal gate proposed in the present invention is further described in detail with specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used.
[0038] First, execute step S1, such as Fig. 9 As shown, a substrate 20 is provided, and a plurality of polysilicon dummy gates 21 are formed on the substrate 20, and a spacing space 23 is provided between two adjacent polysilicon dummy gates 21. The material of the substrate 20 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or may be silicon on insulator (SOI) or germanium on insulator (GOI); or may be other materials, such as III-V compounds such as gallium arsenide, and those skilled in the art may select the type of the substrate 20 according to the semiconductor device formed on the substrate 20, and therefore, the type of the substrate 20 shall not limit the protection scope of the present invention.
[0039] Optionally, in the present embodiment, the method for forming the polysilicon pseudo gate 21 is as follows: a gate dielectric layer, a pseudo gate material layer covering the gate dielectric layer, and a mask layer covering the pseudo gate material layer are formed on the surface of the substrate 20, a patterned photoresist is formed on the mask layer, and the mask layer, the pseudo gate material layer, and the gate dielectric layer are etched using the patterned photoresist as a mask to form the polysilicon pseudo gate 21.
[0040] In some embodiments, in order to improve the electrical performance of the device, optionally, a contact etching stop layer 22 with high stress is formed on the surface of the substrate, such as Fig.14 As shown, the method for forming the contact etching stop layer 22 includes the following steps:
[0041] forming a sidewall structure on the sidewalls of the plurality of polysilicon dummy gates 21; and,
[0042] A contact etching stop layer 22 is formed, and the contact etching stop layer 22 covers the surface of the spacer structure, the upper surface of the polysilicon dummy gate 21 and the upper surface of the substrate 20 on both sides of the spacer structure.
[0043] Optionally, the contact etch stop layer 22 is formed by plasma chemical vapor deposition; in other optional implementations, high-density plasma chemical vapor deposition or molecular layer deposition may be used to form the contact etch stop layer 22. In addition, optionally, the contact etch stop layer 22 may be a high-stress silicon nitride layer or a silicon oxynitride layer, which is not specifically limited in this embodiment.
[0044] Then, execute step S2, such as Fig.10 As shown, the dielectric layer 24 is formed, the dielectric layer 24 fills the spacing space 23, and the upper surface of the dielectric layer 24 is flush with the upper surface of the polysilicon pseudo gate 21. In this embodiment, the material of the dielectric layer 24 can be silicon oxide, silicon nitride or low-K dielectric material.
[0045] In step S2, the method of making the upper surface of the dielectric layer 24 flush with the upper surface of the polysilicon dummy gate 21 includes:
[0046] Grinding the dielectric layer 24, stopping at the contact etching stop layer 22; and,
[0047] The contact etching stop layer 22 and the dielectric layer 24 are ground simultaneously until the contact etching stop layer 22 located on the upper surface of the polysilicon dummy gate 21 is removed and the etching stops at the upper surface of the polysilicon dummy gate 21 .
[0048] Next, execute step S3, such as Fig.11 As shown, heavy ion implantation is performed on a portion of the dielectric layer 24 away from the substrate 20 to form a heavy ion doped layer 25 doped with heavy ions.
[0049] Among them, heavy ions refer to ions formed when atoms with atomic numbers greater than 2 lose electrons, such as silicon ions. It can be understood that the heavy ions used in the heavy ion implantation of the portion of the dielectric layer 24 away from the substrate 20 in this embodiment include silicon ions, which is only a specific example of the implementation of this embodiment and does not constitute a limitation. In other embodiments of the present invention, the heavy ions can also be germanium ions, which can be flexibly set according to actual needs.
[0050] Preferably, when executing step S3, a method of full ion implantation is used to perform heavy ion implantation on the portion of the dielectric layer 24 away from the substrate 20. By injecting heavy ions into the portion of the dielectric layer 24 away from the substrate 20, the material properties of the original dielectric layer 24 are changed to form the heavy ion doped layer 25. Since the heavy ion doped layer 25 has good wear resistance and a low grinding rate, it is not easy to produce a butterfly-shaped depression with a middle depression and two convex sides during the grinding process.
[0051] Generally, ion implantation is divided into full ion implantation and regional ion implantation; regional ion implantation requires a photolithography process before ion implantation, and then ion implantation is performed in a specific area; while the full ion implantation adopted in this embodiment does not require a photolithography process, and directly implants ions into the dielectric layer 24 away from the substrate 20, and the ion implantation area of the full ion implantation matches the cross-sectional area of the dielectric layer 24. That is, in this embodiment, the dielectric layer 24 has excellent wear resistance everywhere after the heavy ions are implanted.
[0052] Furthermore, when executing step S3, considering that the heavily ion doped layer 25 should have a certain thickness to at least ensure that it and the gate metal layer are ground to form a metal gate 27 in the subsequent process, preferably, the implantation depth of the full ion implantation is 5 nanometers to 500 nanometers.
[0053] In addition, when performing the comprehensive ion implantation, the environment is not limited to low temperature, normal temperature or high temperature environment.
[0054] Next, execute step S4, such as Fig.12 As shown, the polysilicon dummy gate 21 is removed, so that a gate trench 26 is formed between two adjacent heavy ion doped layers 25. When etching to form the gate trench 26, the heavy ion doped layer 25 also has a low etching rate, so the butterfly defect can be effectively avoided.
[0055] Preferably, the method for removing the polysilicon dummy gate 21 is dry etching. The etching rates of the polysilicon dummy gate 21 and the heavy ion doped layer 25 are similar in dry etching, which can reduce the loss of the heavy ion doped layer 25, and further, when the gate metal layer is subsequently flattened to form the metal gate 27, the uniformity of the height of the metal gate 27 can be better controlled.
[0056] Finally, execute step S5, such as Fig.13 As shown, the metal gate 27 is formed, and the metal gate 27 fills the gate trench 26 .
[0057] In step S5, the method for forming the metal gate 27 includes the following steps:
[0058] forming a gate metal layer, wherein the gate metal layer fills the gate trench 26; and,
[0059] The gate metal layer and the heavy ion doping layer 25 are ground at the same time until the heavy ion doping layer 25 is completely ground away, and finally the remaining gate metal layer serves as the metal gate 27 .
[0060] In some embodiments, when the gate metal layer and the heavy ion doped layer 25 are ground simultaneously to form the metal gate 27, the heavy ion doped layer 25 is not completely ground away, and the remaining small portion of the heavy ion doped layer 25 does not affect the formation of the metal gate 27 in the subsequent process; in some other preferred embodiments, when the gate metal layer and the heavy ion doped layer 25 are ground simultaneously to form the metal gate 27, the heavy ion doped layer 25 is completely removed.
[0061] Since the grinding of the gate metal layer and the grinding of the heavy ion doped layer 25 are performed simultaneously, the height and flatness of the upper surface of the heavy ion doped layer 25 will inevitably affect the height of the metal gate 27 formed by grinding the gate metal layer, and further affect the uniformity of the height of the metal gate 27. In this embodiment, the grinding rate of the heavy ion doped layer 25 is low, and the butterfly defect with a concave middle and high sides is not likely to occur during the grinding process. Therefore, the uniformity of the height of the metal gate 27 can be ensured, thereby improving the uniformity of the electrical performance of the device.
[0062] Furthermore, in step S5, the method for forming the gate metal layer includes the following steps:
[0063] Filling the gate trench 26 with a gate metal material and extending the gate trench 26 to cover the upper surface of the heavy ion doped layer 25; and,
[0064] The gate metal material on the upper surface of the heavy ion doped layer 25 is removed by grinding, so that the upper surface of the remaining gate metal material is flush with the upper surface of the heavy ion doped layer 25 , so as to form the gate metal layer.
[0065] Optionally, in this embodiment, grinding the dielectric layer 24 , grinding the gate metal layer and grinding the heavy ion doped layer 25 all adopt a chemical mechanical polishing method.
[0066] In summary, an embodiment of the present invention provides a method for forming a metal gate, the method comprising: providing a substrate, forming a plurality of polysilicon pseudo gates on the substrate, and having a spacing space between two adjacent polysilicon pseudo gates; forming a dielectric layer, the dielectric layer filling the spacing space, and the upper surface of the dielectric layer being flush with the upper surface of the polysilicon pseudo gate; performing heavy ion implantation on the portion of the dielectric layer away from the substrate, and forming a heavy ion doped layer doped with heavy ions; removing the polysilicon pseudo gate, so that a gate trench is formed between two adjacent heavy ion doped layers; and forming a metal gate, the metal gate filling the gate trench. Before forming the metal gate, a heavy ion implantation process is introduced to form a heavy ion doped layer, changing the material properties of part of the dielectric layer, the heavy ion doped layer has higher wear resistance than the dielectric layer, and when grinding the gate metal layer and the heavy ion doped layer at the same time, the grinding rate of the heavy ion doped layer is relatively low, and it is not easy to produce butterfly defects that would be produced in the prior art, thereby avoiding the formation of large height differences of the metal gate and improving the uniformity of the electrical performance of the device.
[0067] In addition, it should be recognized that although the present invention application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
Claims
1. A method for forming a metal gate, characterized in that: The method for forming the metal gate comprises: Providing a substrate, forming a plurality of polysilicon dummy gates on the substrate, and having a spacing space between two adjacent polysilicon dummy gates; forming a dielectric layer, wherein the dielectric layer fills the spacing space, and an upper surface of the dielectric layer is flush with an upper surface of the polysilicon pseudo gate; Performing heavy ion implantation on a portion of the dielectric layer away from the substrate to form a heavy ion doped layer doped with heavy ions; removing the polysilicon dummy gate so that a gate trench is formed between two adjacent heavy ion doped layers; and, A metal gate is formed, wherein the metal gate fills the gate trench.
2. The method for forming a metal gate according to claim 1, wherein: After forming a plurality of the polysilicon dummy gates on the substrate, the method for forming the metal gate further includes: forming a sidewall structure on the sidewalls of the plurality of the polysilicon dummy gates.
3. The method for forming a metal gate according to claim 2, wherein: Before forming the dielectric layer, the method for forming the metal gate further includes: forming a contact etch stop layer, wherein the contact etch stop layer covers the surface of the sidewall structure, the upper surface of the polysilicon pseudo gate, and the upper surface of the substrate on both sides of the sidewall structure.
4. The method for forming a metal gate according to claim 3, wherein: The method of forming the dielectric layer and making the upper surface of the dielectric layer flush with the upper surface of the polysilicon dummy gate includes: grinding the dielectric layer and stopping at the contact etching stop layer; and, The contact etching stop layer and the dielectric layer are ground simultaneously until the contact etching stop layer located on the upper surface of the polysilicon dummy gate is removed and the etching stops at the upper surface of the polysilicon dummy gate.
5. The method for forming a metal gate according to claim 1, wherein: The method of performing heavy ion implantation on the portion of the dielectric layer away from the substrate comprises: performing heavy ion implantation on the portion of the dielectric layer away from the substrate by adopting a full ion implantation method.
6. The method for forming a metal gate according to claim 1, wherein: The heavy ions in the heavy ion implantation include silicon ions or germanium ions.
7. The method for forming a metal gate according to claim 1, wherein: The method of forming the metal gate includes: forming a gate metal layer, wherein the gate metal layer fills the gate trench; and The gate metal layer and the heavy ion doped layer are ground simultaneously until the heavy ion doped layer is completely ground away, and finally the remaining gate metal layer serves as the metal gate.
8. The method for forming a metal gate according to claim 7, wherein: The method of forming the gate metal layer comprises: Filling the gate metal material in the gate trench and extending it to cover the upper surface of the heavy ion doped layer; The gate metal material on the upper surface of the heavy ion doped layer is removed by grinding, so that the upper surface of the remaining gate metal material is flush with the upper surface of the heavy ion doped layer, so as to form the gate metal layer.
9. The method for forming a metal gate according to claim 1, wherein: The method for removing the polysilicon dummy gate is dry etching.
10. The method for forming a metal gate according to claim 1, wherein: The grinding of the dielectric layer, the grinding of the gate metal layer and the grinding of the heavy ion doped layer are all carried out by chemical mechanical grinding.