Coupling type three-level inverter direct current side capacitance current ripple suppression method and system

Abstract

The invention belongs to the field of power electronic power conversion, and provides a coupling type three-level inverter direct current side capacitance current ripple suppression method and system, and the method comprises the steps: determining a coupling type three-level inverter space vector diagram region division method according to a virtual voltage vector duty ratio distribution factor value range; according to the amplitude, the phase angle and the three-phase output current of the reference voltage vector, the sector and the area where the reference voltage vector is located are judged; according to the sector and the area where the reference voltage vector is located, selecting a virtual voltage vector and two basic voltage vectors which are closest to each other, and respectively calculating duty ratios of the virtual voltage vector and the two basic voltage vectors; designing a controller based on a dead-beat control method according to a sector and an area where a reference voltage vector is located, a direct-current side capacitor voltage deviation given value and a direct-current side capacitor voltage deviation actual value, and updating a small vector duty ratio distribution factor to realize independent control of capacitor voltage; and designing a switch sequence based on the updated small vector duty ratio and the sector and the area where the reference voltage vector is located.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic power conversion, and in particular relates to a method and system for suppressing ripple of capacitor current on the DC side of a coupled three-level inverter. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Three-level inverters are widely used in renewable energy generation, motor drive and energy storage systems due to their simple structure, good output current waveform quality and high efficiency. T-type three-level inverter is a commonly used circuit topology, but it contains a large number of power switch tubes. The coupled three-level inverter contains only ten power switch tubes, which further reduces the number of power switch tubes while maintaining multi-level output characteristics, and has broad application prospects.

[0004] Electrolytic capacitors are components that are prone to failure, and their stability directly determines the quality of the inverter's output waveform. The DC side capacitor current ripple is defined as the RMS value of the neutral current. When the DC side capacitor current ripple is high, the service life of the capacitor will be shortened, or even directly damage the inverter. Larger capacitors will extend the inverter's service life, but increase the system size and cost.

[0005] The inventors found that the existing DC side capacitor current ripple suppression method is mainly aimed at T-type or hybrid active neutral point clamped (Hybrid Active Neutral-Point-Clamped, HANPC) three-level inverter topology. When the coupled three-level inverter operates under the condition where the DC side capacitor voltage is unequal, the harmonic content of its output current will increase. In addition, the output state of this topology is limited and the neutral vector cannot be generated. Therefore, the existing control method cannot be directly applied. Therefore, the DC side capacitor current ripple suppression method suitable for the coupled three-level inverter under unbalanced conditions needs to be studied urgently. Summary of the invention

[0006] In order to solve the above problems, the present invention proposes a method and system for suppressing the ripple of the DC side capacitor current of a coupled three-level inverter. The present invention can effectively suppress the DC side capacitor current ripple of the coupled three-level inverter while maintaining good output current waveform quality, and is suitable for working conditions of balanced and unbalanced DC side capacitor voltage.

[0007] According to some embodiments, a first solution of the present invention provides a method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter, which adopts the following technical solution:

[0008] A method for suppressing capacitor current ripple on a DC side of a coupled three-level inverter, comprising:

[0009] According to the value range of the virtual voltage vector duty cycle allocation factor, a method for dividing the space vector diagram of the coupled three-level inverter is determined;

[0010] According to the amplitude, phase angle and three-phase output current of the reference voltage vector, the sector and region where the reference voltage vector is located are determined;

[0011] According to the sector and region where the reference voltage vector is located, a virtual voltage vector and two basic voltage vectors that are closest to each other are selected to calculate their duty cycles respectively;

[0012] According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, a controller is designed based on the deadbeat control method to update the small vector duty cycle allocation factor to achieve independent control of the capacitor voltage.

[0013] Based on the updated small vector duty cycle and the sector and region where the reference voltage vector is located, a switching sequence is designed, and the switching sequence is converted into a PWM drive signal of the power switch tube to control the operation of the coupled three-level inverter.

[0014] According to some embodiments, a second solution of the present invention provides a coupled three-level inverter DC side capacitor current ripple suppression system, which adopts the following technical solution:

[0015] A coupled three-level inverter DC side capacitor current ripple suppression system, comprising:

[0016] A sector division module is configured to determine a region division method of a space vector diagram of a coupled three-level inverter according to a value range of a virtual voltage vector duty cycle allocation factor;

[0017] A sector determination module is configured to determine the sector and region where the reference voltage vector is located according to the amplitude, phase angle and three-phase output current of the reference voltage vector;

[0018] The basic voltage vector selection module is configured to select a virtual voltage vector and two basic voltage vectors that are closest to the reference voltage vector according to the sector and area where the reference voltage vector is located, and calculate their duty ratios respectively;

[0019] The capacitor voltage independent control module is configured to design a controller based on a deadbeat control method according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation, and the actual value of the DC side capacitor voltage deviation, update the small vector duty cycle allocation factor, and realize the capacitor voltage independent control;

[0020] The drive signal generation module is configured to design a switch sequence based on the updated small vector duty cycle and the sector and region where the reference voltage vector is located, convert the switch sequence into a PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

[0021] According to some embodiments, a third aspect of the present invention provides a computer-readable storage medium.

[0022] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter as described in the first aspect above.

[0023] According to some embodiments, a fourth aspect of the present invention provides a computer device.

[0024] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter as described in the first aspect above are implemented.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] Compared with the traditional space vector modulation method, the present invention significantly reduces the ripple of the DC side capacitor current, and can extend the service life of the DC side capacitor. Under the balanced and unbalanced working conditions of the DC side capacitor voltage, the method of the present invention reduces the total harmonic distortion rate of the three-phase output current of the coupled three-level inverter, and improves the efficiency and stability of the system. The present invention corrects the duty cycle of the P-type small vector and the N-type small vector according to different sectors, regions, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage, and realizes independent control of the capacitor voltage. Compared with the traditional space vector method, the present invention only uses three voltage vectors to synthesize the reference voltage vector, and there is no need to use an indirect method to calculate the voltage vector duty cycle, which reduces the calculation burden. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0028] Figure 1 It is the circuit topology diagram of the coupled three-level inverter;

[0029] Figure 2 It is the space vector diagram of the coupled three-level inverter when the DC side unbalance factor is greater than 0;

[0030] Figure 3It is the space vector diagram of the coupled three-level inverter when the DC side unbalance factor is less than 0;

[0031] Figure 4 is the value range of the virtual vector duty cycle allocation factor β when the system adopts the traditional space vector modulation method;

[0032] FIG5 is a region division method according to Embodiment 1 of the present invention;

[0033] Figure 6 Schematic diagram of the switching sequence when the system adopts the traditional space vector modulation method and the reference voltage is located in the sector 1 and the outer area;

[0034] Figure 7 This is a schematic diagram of a switching sequence when the system adopts the control method of the first embodiment of the present invention and the reference voltage is located in sector 1 and area A1;

[0035] Figure 8 This is a schematic diagram of a method for suppressing ripple of a DC-side capacitor current according to a first embodiment of the present invention;

[0036] FIG9( a ) is a simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is 0.2, and the modulation index is 0.8;

[0037] FIG9( b ) is a simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is -0.2, and the modulation index is 0.8;

[0038] FIG9(c) is a simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is 0, and the modulation index is 0.8;

[0039] FIG10( a ) is a simulation waveform diagram when the system adopts the control method of the first embodiment of the present invention, the DC side unbalance factor is 0.2, and the modulation index is 0.8;

[0040] FIG10( b ) is a simulation waveform diagram when the system adopts the control method of the first embodiment of the present invention, the DC side unbalance factor is -0.2, and the modulation index is 0.8;

[0041] FIG10( c ) is a simulation waveform diagram when the system adopts the control method of the first embodiment of the present invention, the DC side unbalance factor is 0, and the modulation index is 0.8;

[0042] FIG11( a ) is a simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is 0.2, and the modulation index is 0.4;

[0043] FIG11( b ) is a simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is -0.2, and the modulation index is 0.4;

[0044] FIG11( c ) is a simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is 0, and the modulation index is 0.4;

[0045] FIG12( a ) is a simulation waveform diagram when the system adopts the control method of the first embodiment of the present invention, the DC side unbalance factor is 0.2, and the modulation index is 0.4;

[0046] FIG12( b ) is a simulation waveform diagram when the system adopts the control method of the first embodiment of the present invention, the DC side unbalance factor is -0.2, and the modulation index is 0.4;

[0047] FIG12( c ) is a simulation waveform diagram when the system adopts the control method of the first embodiment of the present invention, the DC side unbalance factor is 0, and the modulation index is 0.4;

[0048] FIG13( a ) is a simulation waveform diagram of a system using the control method of Embodiment 1 of the present invention, with the modulation index set to 0.8 and a given value of the DC side capacitor voltage deviation undergoing a unit step;

[0049] FIG13( b ) is a simulation waveform diagram when the system adopts the control method of the first embodiment of the present invention, the modulation index is set to 0.4, and the DC side capacitor voltage deviation given value undergoes a unit step. DETAILED DESCRIPTION

[0050] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0051] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0052] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0053] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0054] Embodiment 1

[0055] This embodiment provides a method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter. In this embodiment, the method includes the following steps:

[0056] According to the value range of the virtual voltage vector duty cycle allocation factor, a method for dividing the space vector diagram of the coupled three-level inverter is determined;

[0057] According to the amplitude, phase angle and three-phase output current of the reference voltage vector, the sector and region where the reference voltage vector is located are determined;

[0058] According to the sector and region where the reference voltage vector is located, a virtual voltage vector and two basic voltage vectors that are closest to each other are selected to calculate their duty cycles respectively;

[0059] According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, a controller is designed based on the deadbeat control method to update the small vector duty cycle allocation factor to achieve independent control of the capacitor voltage.

[0060] Based on the updated small vector duty cycle and the sector and region where the reference voltage vector is located, a switching sequence is designed, and the switching sequence is converted into a PWM drive signal of the power switch tube to control the operation of the coupled three-level inverter.

[0061] Figure 1 The system topology of the coupled three-level inverter includes two sets of photovoltaic arrays, two DC-side electrolytic capacitors, a coupled three-level inverter and a three-phase load. The two sets of photovoltaic arrays are connected to an electrolytic capacitor respectively, and the control strategy is further designed to realize the independent maximum power point tracking (MPPT) function of the photovoltaic array, thereby improving the system efficiency.

[0062] The power switch tube refers to an insulated-gate bipolar transistor (IGBT); the power switch tube may also be implemented by transistors in other forms, which may be selected according to the actual needs of technicians in this field.

[0063] The switching states of the coupled three-level inverter include three types: P, O and N. Select the DC side neutral point O (see Figure 1 ) as a reference, when the switch state is P, the bridge arm output voltage is +VP; when the switch state is O, the bridge arm output voltage is 0; when the switch state is N, the bridge arm output voltage is –VN.

[0064] For the convenience of analysis, the DC side unbalance factor μ is defined as:

[0065]

[0066] Among them, V P and V N are the voltages across the upper and lower capacitors, Vdiff is the difference between the two capacitor voltages on the DC side (i.e. V diff =V P -V N ), V dc It is the sum of the voltages of the two capacitors on the DC side.

[0067] Based on formula (1), the expressions of the upper and lower capacitor voltages on the DC side are:

[0068]

[0069] Figure 2 and Figure 3 They are the space vector diagrams of the coupled three-level inverter when the unbalance factor on the DC side is greater than or less than 0, respectively. The entire space vector diagram is divided into 6 sectors (i.e., the first sector to the sixth sector, which can also be expressed as sector 1 to sector 6). It can be seen that under the condition of unbalanced midpoint voltage on the DC side, the positions of the large vector and the zero vector remain unchanged, that is, the same as when the midpoint voltage is balanced; the position of the small vector is offset, and the small vector no longer maintains the redundant characteristics, which makes the implementation process of the space vector modulation method extremely complicated.

[0070] All basic voltage vectors are related to the neutral current (i np ) is shown in Table 1. It is not difficult to find that only the small vector affects the neutral current. In addition, the neutral current amplitude generated by each pair of P-type small vector and N-type small vector is equal and the direction is opposite.

[0071] Without loss of generality, the specific implementation process is described in detail by taking sector 1 as an example.

[0072] According to the value range of the virtual voltage vector duty cycle allocation factor, the region division method of the coupled three-level inverter space vector diagram is determined, which is specifically:

[0073] According to two pairs of small vectors in the first sector of the space vector diagram of the coupled three-level inverter, a first virtual voltage vector and a second virtual voltage vector are synthesized respectively;

[0074] According to the two virtual voltage vectors and the two large vectors, the duty ratios of the two virtual voltage vectors are determined based on an indirect method;

[0075] Calculating a virtual voltage vector duty cycle allocation factor according to the duty cycles of the two virtual voltage vectors;

[0076] Considering the value range of the large vector, the duty cycle allocation factor of the small vector, and when the DC side unbalance factor is equal to zero, the value range of the duty cycle allocation factors of the two virtual voltage vectors is determined;

[0077] Determine two straight lines passing through the first sector based on the maximum value and the minimum value of the virtual voltage vector duty cycle allocation factor, which respectively represent the connection line of a virtual voltage vector and a large vector;

[0078] The two straight lines are used as the region division conditions to divide the first sector of the space vector diagram of the coupled three-level inverter into regions. Specifically, as follows:

[0079] The small vectors in sector 1 include the first pair of small vectors [POO] (V S1p ) and [ONN](V S1n ), the second pair of small vectors [PPO] (V S2p ) and [OON](V S2n ), their amplitudes are no longer equal, and it is difficult to synthesize the reference voltage vector. Therefore, each pair of small vectors synthesizes a virtual voltage vector, and its expressions are:

[0080]

[0081] Among them, V v1 and V v2 represents two virtual vectors, a first virtual voltage vector and a second virtual voltage vector respectively, and α is a small vector duty cycle allocation factor.

[0082] To this end, all the basic voltage vectors in sector 1 are expressed as:

[0083]

[0084] Among them, V L1 、V L2 and V Z They represent large vector [PNN], large vector [PPN] and zero vector [OOO] respectively.

[0085] Table 1 Neutral current (i np ) and the basic voltage vector

[0086]

[0087]

[0088] 1. Calculation of virtual vector duty cycle allocation factor

[0089] When the reference voltage vector (Vref) is located in the outer area of ​​fan 1, two virtual voltage vectors and two large vectors are used to synthesize the reference voltage, and its volt-second balance equation is:

[0090]

[0091] Among them, d L1 d L2d v1 and d v2 Respectively represent V L1 、V L2 、V v1 and V v2 duty cycle.

[0092] Simplified, the sum of the duty cycles of the virtual vectors (d v12 )for:

[0093]

[0094] Among them, m is the modulation index, and its expression is:

[0095]

[0096] Assume that the virtual voltage vector duty cycle allocation factor is β, the duty cycle of each virtual voltage vector (d v1 and d v2 ) can be expressed as:

[0097]

[0098] Therefore, the duty cycle of the two large vectors is:

[0099]

[0100] Considering d L1 and d L2 Should be greater than 0, and 0≤β≤1, the maximum value of β is β max and the minimum value β min They are:

[0101]

[0102] 2. Analysis of virtual voltage vector duty cycle allocation factors

[0103] When the small vector duty cycle allocation factor α and the DC side unbalance factor μ are equal to 0, β under different modulation indices max and β min like Figure 4 As shown. It is not difficult to find that β max and β min It can be 0 or 1 within a certain range. In addition, as the modulation index increases, the maximum and minimum values ​​of β can be 0 or 1 within a larger range.

[0104] When β max When is equal to 1, formula (11) can be expressed as:

[0105]

[0106] Similarly, when βmin When is equal to 0, formula (12) can be expressed as:

[0107]

[0108] It can be seen that equations (13) and (14) represent two straight lines passing through sector 1. At this time, the two straight lines pass through a small vector and a large vector respectively, and their space vector diagrams are shown in Figure 5. Taking the above two straight lines as the area division conditions, only three voltage vectors are synthesized into a reference voltage vector, which reduces the calculation burden.

[0109] When the reference voltage vector is located in sector 1, the small vectors [POO], [ONN], [PPO] and [OON] determine the neutral current, that is, the output current i a and i c Directly determines the DC side capacitor current ripple. Therefore, the DC side capacitor current ripple can be suppressed by discarding the virtual voltage vector with a large neutral current amplitude. Specifically, when |i a |≤|i c |, β should be equal to 1; when |i a |>|i c |, β should be 0. When the reference voltage vector is located in sectors other than sector 1, the value of the virtual voltage vector duty cycle allocation factor can be obtained by using the above principle, which will not be repeated here.

[0110] when|i a |≤|i c |When Figure 6 and Figure 7 The neutral point current and output voltage waveforms of the conventional method and the method of the present invention are shown in FIG. Since the small vectors [POO] and [ONN] with high neutral line current amplitude are discarded, the method of the present invention can effectively reduce the DC side capacitor current ripple.

[0111] 3. Independent control of capacitor voltage

[0112] As mentioned above, in a large-capacity centralized photovoltaic power generation system, by connecting a group of photovoltaic arrays at both ends of each DC side capacitor, the voltages at both ends of the two capacitors C1 and C2 of the DC side capacitor are controlled respectively to realize independent MPPT function and improve system efficiency. To this end, a controller is designed based on the deadbeat control method to accurately adjust the neutral current, obtain the duty cycle allocation factors of the P-type small vector and the N-type small vector, to update the duty cycle of each basic voltage vector, and realize independent control of capacitor voltage.

[0113] According to Kirchhoff's Current Law (KCL), the mathematical model of neutral current can be expressed as:

[0114]

[0115] Among them, C dc is the DC side capacitance, and C dc =C1=C2.

[0116] Assume a sampling period of T s , the discrete model of the neutral current can be expressed as:

[0117]

[0118] Among them, V diff (k) and V diff (k+1) represents the capacitor voltage difference between the kth and k+1th sampling periods, i np (k) is the neutral line current value of the kth sampling period.

[0119] Let V diff (k+1) is the given value of capacitor voltage deviation The reference value of the neutral current is It can be expressed as:

[0120]

[0121] Specifically, when the reference voltage vector is located in sector 1 (region A1 and region B1), that is, in the first region of the first sector, the relationship between the neutral current and the duty cycle is:

[0122] i np =i a d S1n +i b d S1p +i c d S1p (18);

[0123] Among them, d S1p and d S1n Respectively represent the duty cycle of the first pair of small vectors [POO] and [ONN], i a 、i b and i c are the three-phase output currents of the inverter respectively.

[0124] To achieve independent control of capacitor voltage, d S1p and d S1n The duty cycle is corrected to:

[0125]

[0126] Among them, y np is an intermediate variable, and y np The relationship with the small vector duty cycle allocation factor α is:

[0127]

[0128] Combining equations (17), (18) and (19), we can get y np The optimal value of is:

[0129]

[0130] When the reference voltage vector is located in other sectors and regions, y np The optimal value of can be solved according to the above method. When the reference voltage vector is located in sector 1, area A2 and B2, y np The optimal value of is:

[0131]

[0132] When the reference voltage vector is located in sector 2, area A1 and B1, y np The optimal value of is:

[0133]

[0134] When the reference voltage vector is located in sector 2, area A2 and B2, y np The optimal value of is:

[0135]

[0136] When the reference voltage vector is located in sector 3, area A1 and B1, y np The optimal value of is:

[0137]

[0138] When the reference voltage vector is located in sector 3, area A2 and B2, y np The optimal value of is:

[0139]

[0140] When the reference voltage vector is located in sector 4, area A1 and B1, y np The optimal value of is:

[0141]

[0142] When the reference voltage vector is located in sector 4, area A2 and B2, y np The optimal value of is:

[0143]

[0144] When the reference voltage vector is located in sector 5, area A1 and B1, y np The optimal value of is:

[0145]

[0146] When the reference voltage vector is located in sector 5, area A2 and B2, y np The optimal value of is:

[0147]

[0148] When the reference voltage vector is located in sector 6, area A1 and B1, y np The optimal value of is:

[0149]

[0150] When the reference voltage vector is located in sector 6, area A2 and B2, y np The optimal value of is:

[0151]

[0152] 4. Switch sequence design

[0153] Considering the low output harmonic content, small dead time impact and small number of power switch operations of the coupled three-level inverter, the switching sequence is designed.

[0154] When the reference voltage vector is located in area A1 within sector 1, the five-stage switching sequence is designed as follows: [PNN]-[POO]-[PPN]-[ONN]-[PNN];

[0155] When the reference voltage vector is located in region A2 within sector 1, the five-stage switching sequence is designed as follows: [PNN]-[PPO]-[PPN]-[OON]-[PNN];

[0156] When the reference voltage vector is located in region B1 within sector 1, the five-stage switching sequence is designed as follows: [PPN]-[POO]-[OOO]-[ONN]-[PPN];

[0157] When the reference voltage vector is located in region B2 within sector 1, the five-stage switching sequence is designed as follows: [PPN]-[POO]-[OOO]-[ONN]-[PPN];

[0158] When the reference voltage vector is located in region A1 within sector 2, the five-stage switching sequence is designed as follows: [PPN]-[PPO]-[NPN]-[OON]-[PPN];

[0159] When the reference voltage vector is located in region A2 within sector 2, the five-stage switching sequence is designed as follows: [PPN]-[OPO]-[NPN]-[NON]-[PPN];

[0160] When the reference voltage vector is located in region B1 within sector 2, the five-stage switching sequence is designed as follows: [NPN]-[PPO]-[OOO]-[OON]-[NPN];

[0161] When the reference voltage vector is located in region B2 within sector 2, the five-stage switching sequence is designed as follows: [PPN]-[OPO]-[OOO]-[NON]-[PPN];

[0162] When the reference voltage vector is located in region A1 within sector 3, the five-stage switching sequence is designed as follows: [NPN]-[OPO]-[NPP]-[NON]-[NPN];

[0163] When the reference voltage vector is located in region A2 within sector 3, the five-stage switching sequence is designed as follows: [NPN]-[OPP]-[NPP]-[NOO]-[NPN];

[0164] When the reference voltage vector is located in region B1 within sector 3, the five-stage switching sequence is designed as follows: [NPP]-[OPO]-[OOO]-[NON]-[NPP];

[0165] When the reference voltage vector is located in region B2 within sector 3, the five-stage switching sequence is designed as follows: [NPN]-[OPP]-[OOO]-[NOO]-[NPN];

[0166] When the reference voltage vector is located in region A1 within sector 4, the five-stage switching sequence is designed as follows: [NPP]-[OPP]-[NNP]-[NOO]-[NPP];

[0167] When the reference voltage vector is located in region A2 within sector 4, the five-stage switching sequence is designed as follows: [NPP]-[OOP]-[NNP]-[NNO]-[NPP];

[0168] When the reference voltage vector is located in region B1 within sector 4, the five-stage switching sequence is designed as follows: [NNP]-[OPP]-[OOO]-[NOO]-[NNP];

[0169] When the reference voltage vector is located in region B2 within sector 4, the five-stage switching sequence is designed as follows: [NPP]-[OOP]-[OOO]-[NNO]-[NPP];

[0170] When the reference voltage vector is located in region A1 within sector 5, the five-stage switching sequence is designed as follows: [NNP]-[OOP]-[PNP]-[NNO]-[NNP];

[0171] When the reference voltage vector is located in region A2 within sector 5, the five-stage switching sequence is designed as follows: [NNP]-[POP]-[PNP]-[ONO]-[NNP];

[0172] When the reference voltage vector is located in region B1 within sector 5, the five-stage switching sequence is designed as follows: [PNP]-[OOP]-[OOO]-[NNO]-[PNP];

[0173] When the reference voltage vector is located in region B2 within sector 5, the five-stage switching sequence is designed as follows: [NNP]-[POP]-[OOO]-[ONO]-[NNP];

[0174] When the reference voltage vector is located in region A1 within sector 6, the five-stage switching sequence is designed as follows: [PNP]-[POP]-[PNN]-[ONO]-[PNP];

[0175] When the reference voltage vector is located in region A2 within sector 6, the five-stage switching sequence is designed as follows: [PNP]-[POO]-[PNN]-[ONN]-[PNP];

[0176] When the reference voltage vector is located in region B1 within sector 6, the five-stage switching sequence is designed as follows: [PNN]-[POP]-[OOO]-[ONO]-[PNN];

[0177] When the reference voltage vector is located in region B2 within sector 6, the five-stage switching sequence is designed as follows: [PNP]-[POO]-[OOO]-[ONN]-[PNP].

[0178] The switching sequence is converted into a driving signal of the power switch tube, thereby controlling the operation of the coupled three-level inverter system.

[0179] Figure 8 This is a schematic diagram of a method for suppressing DC side capacitor current ripple according to Embodiment 1 of the present invention.

[0180] Figure 9 shows the simulation waveform when the system adopts the traditional space vector modulation method and the modulation index is 0.8, including the DC side capacitor voltage (V P and V N ), line voltage (V ab )、A phase output voltage (i a )、Neutral current (i np). The unbalance coefficient of Figure 9(a) is set to 0.2, the unbalance coefficient of Figure 9(b) is set to –0.2, and the unbalance coefficient of Figure 9(c) is set to 0. At this time, the DC side input voltage is 100V. It can be seen that the DC side current ripple of the system is very high, and the effective values ​​of the DC side capacitor current ripple are as high as 2.621A, 2.622A, and 2.621A respectively.

[0181] Figure 10 is a simulation waveform diagram when the system adopts the control method of embodiment 1 of the present invention and the modulation index is 0.8. Among them, the unbalance coefficient of Figure 10 (a) is set to 0.2, the unbalance coefficient of Figure 10 (b) is set to -0.2, and the unbalance coefficient of Figure 10 (c) is set to 0. At this time, the system line voltage is a five-level waveform, and the output current is a sinusoidal waveform. The effective value of the DC side capacitor current ripple of the system is reduced to 1.715A, 1.709A and 1.711A respectively. It can be seen that the DC side capacitor current ripple of the system is 65.43%, 65.18% and 65.28% of the traditional space vector modulation method, respectively, and maintains good output current quality, with obvious advantages.

[0182] Figure 11 shows the simulation waveform when the system adopts the traditional space vector modulation method and the modulation index is 0.4. Among them, the unbalance coefficient of Figure 11 (a) is set to 0.2, the unbalance coefficient of Figure 11 (b) is set to –0.2, and the unbalance coefficient of Figure 11 (c) is set to 0. It can be seen that the line voltage (V ab ) is reduced to a three-level waveform, the quality of the system's output current is reduced, and its output current total harmonic distortion (THD i ) are 1.82%, 1.82% and 1.76% respectively. The DC side capacitor current ripple of the system is very high, and its DC side capacitor current ripple is as high as 1.718A, 1.718A and 1.718A respectively.

[0183] FIG12 is a simulation of a system using the control method of Embodiment 1 of the present invention and a modulation index of 0.4. The unbalance coefficient of FIG12(a) is set to 0.2, the unbalance coefficient of FIG12(b) is set to –0.2, and the unbalance coefficient of FIG12(c) is set to 0. At this time, the line voltage is a five-level waveform and the output current is a sinusoidal waveform. The DC side capacitor current ripple of the system is reduced by 54.83%, 55.30% and 55.15% respectively compared with the traditional space vector modulation method, which has obvious advantages.

[0184] FIG13 is a simulation waveform diagram of the system using the control method of the first embodiment of the present invention when the capacitor voltage deviation given value undergoes a step change. It can be seen that the control method of the first embodiment of the present invention can independently control the two capacitor voltages on the DC side. In addition, the control method of the first embodiment of the present invention achieves DC side capacitor current ripple suppression under dynamic conditions while maintaining good output current waveform quality.

[0185] Embodiment 2

[0186] This embodiment provides a coupled three-level inverter DC side capacitor current ripple suppression system, including:

[0187] A sector division module is configured to determine a region division method of a space vector diagram of a coupled three-level inverter according to a value range of a virtual voltage vector duty cycle allocation factor;

[0188] A sector determination module is configured to determine the sector and region where the reference voltage vector is located according to the amplitude, phase angle and three-phase output current of the reference voltage vector;

[0189] The basic voltage vector selection module is configured to select a virtual voltage vector and two basic voltage vectors that are closest to the reference voltage vector according to the sector and area where the reference voltage vector is located, and calculate their duty ratios respectively;

[0190] The capacitor voltage independent control module is configured to design a controller based on a deadbeat control method according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation, and the actual value of the DC side capacitor voltage deviation, update the small vector duty cycle allocation factor, and realize the capacitor voltage independent control;

[0191] The drive signal generation module is configured to design a switch sequence based on the updated small vector duty cycle and the sector and region where the reference voltage vector is located, convert the switch sequence into a PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

[0192] The examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the contents disclosed in the above embodiment 1. It should be noted that the above modules as part of the system can be executed in a computer system such as a set of computer executable instructions.

[0193] The description of each embodiment in the above embodiments has different emphases. For parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0194] The proposed system can be implemented in other ways. For example, the system embodiment described above is only illustrative, and the division of the modules is only a logical function division. In actual implementation, there may be other division methods, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed.

[0195] Embodiment 3

[0196] This embodiment provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the steps of the method for suppressing the ripple of the capacitor current on the DC side of the coupled three-level inverter as described in the first embodiment above are implemented.

[0197] Embodiment 4

[0198] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps in the method for suppressing the ripple of the capacitor current on the DC side of the coupled three-level inverter as described in the first embodiment are implemented.

[0199] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0200] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0201] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0202] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0203] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0204] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A method for suppressing capacitor current ripple on the DC side of a coupled three-level inverter, characterized in that: include: According to the value range of the virtual voltage vector duty cycle allocation factor, a method for dividing the space vector diagram of the coupled three-level inverter is determined; According to the amplitude, phase angle and three-phase output current of the reference voltage vector, the sector and region where the reference voltage vector is located are determined; According to the sector and region where the reference voltage vector is located, a virtual voltage vector and two basic voltage vectors that are closest to each other are selected to calculate their duty cycles respectively; According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, a controller is designed based on the deadbeat control method to update the small vector duty cycle allocation factor to achieve independent control of the capacitor voltage. Based on the updated small vector duty cycle and the sector and region where the reference voltage vector is located, a switching sequence is designed, and the switching sequence is converted into a PWM drive signal of the power switch tube to control the operation of the coupled three-level inverter.

2. The method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter according to claim 1, characterized in that: The method for determining the area division of the space vector diagram of the coupled three-level inverter according to the value range of the virtual voltage vector duty cycle allocation factor is specifically as follows: synthesizing a first virtual voltage vector and a second virtual voltage vector respectively according to two pairs of small vectors in a first sector of a space vector diagram of a coupled three-level inverter; According to the two virtual voltage vectors and the two large vectors, the duty ratios of the two virtual voltage vectors are determined based on an indirect method; Calculating a virtual voltage vector duty cycle allocation factor according to the duty cycles of the two virtual voltage vectors; Considering the value range of the large vector, the duty cycle allocation factor of the small vector, and when the DC side unbalance factor is equal to zero, the value range of the duty cycle allocation factors of the two virtual voltage vectors is determined; Determine two straight lines passing through the first sector based on the maximum value and the minimum value of the virtual voltage vector duty cycle allocation factor, which respectively represent the connection line of a virtual voltage vector and a large vector; The two straight lines are used as area division conditions to divide the first sector of the space vector diagram of the coupled three-level inverter into regions.

3. The method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter according to claim 2, characterized in that: The two straight lines passing through the first sector are determined based on the maximum value and the minimum value of the virtual voltage vector duty cycle allocation factor, specifically: When the maximum value of the virtual voltage vector duty cycle allocation factor is 1, it is obtained: When the minimum value of the virtual voltage vector duty cycle allocation factor is 0, it is obtained: Among them, μ is the DC side unbalance factor, α is the small vector duty cycle allocation factor, V ref is the reference voltage vector, V dc It is the sum of the voltages of the two capacitors on the DC side.

4. The method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter according to claim 1, characterized in that: The method of selecting the nearest virtual voltage vector and two basic voltage vectors to calculate their duty cycles respectively is as follows: According to two pairs of small vectors in the first sector of the space vector diagram of the coupled three-level inverter, a first virtual voltage vector and a second virtual voltage vector are synthesized respectively; Based on the two virtual voltage vectors and the two large vectors, the duty ratios of the two virtual voltage vectors and the duty ratios of the two large vectors are determined based on an indirect method; The virtual voltage vector with a large neutral current value is discarded, and another virtual voltage vector and two basic voltage vectors are selected to calculate their duty cycles respectively.

5. The method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter according to claim 1, characterized in that: According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, a controller is designed based on a deadbeat control method, and a small vector duty cycle allocation factor is updated to realize independent control of the capacitor voltage, specifically: Determine a discrete model of the neutral current according to a given value of the DC side capacitor voltage deviation and an actual value of the DC side capacitor voltage deviation; According to the discrete model of neutral current, a controller is designed based on the deadbeat control method to adjust the midpoint voltage. Determine the relationship between the neutral current and the duty cycle allocation factor of the small vector in the first sector based on the sector and the region where the reference voltage vector is located; The duty cycle of the small vector is updated based on the neutral current to achieve independent control of the capacitor voltage.

6. The method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter according to claim 1, characterized in that: The switching sequence is designed based on the updated small vector duty cycle and the sector and region where the reference voltage vector is located, specifically: Determine an expression for an optimal value of an intermediate variable in the first sector based on a relationship between a neutral current and a duty cycle of a selected small vector in the first sector and a reference value of the neutral current; Determining the optimal value of the intermediate variable when the reference voltage vector is located in other sectors and regions based on the expression of the optimal value of the intermediate variable in the first sector; According to the magnitude of the neutral current, determine the small vector duty cycle allocation factor; Different switching sequences are designed based on the optimal values ​​of the intermediate variables when the reference voltage is located in different sectors and regions.

7. The method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter according to claim 1, characterized in that: The design switch sequence is specifically: When the reference voltage vector is located in area A1 within sector 1, the five-stage switching sequence is designed as follows: [PNN]-[POO]-[PPN]-[ONN]-[PNN]; When the reference voltage vector is located in region A2 within sector 1, the five-stage switching sequence is designed as follows: [PNN]-[PPO]-[PPN]-[OON]-[PNN]; When the reference voltage vector is located in region B1 within sector 1, the five-stage switching sequence is designed as follows: [PPN]-[POO]-[OOO]-[ONN]-[PPN]; When the reference voltage vector is located in region B2 within sector 1, the five-stage switching sequence is designed as follows: [PPN]-[POO]-[OOO]-[ONN]-[PPN]; When the reference voltage vector is located in region A1 within sector 2, the five-stage switching sequence is designed as follows: [PPN]-[PPO]-[NPN]-[OON]-[PPN]; When the reference voltage vector is located in region A2 within sector 2, the five-stage switching sequence is designed as follows: [PPN]-[OPO]-[NPN]-[NON]-[PPN]; When the reference voltage vector is located in region B1 within sector 2, the five-stage switching sequence is designed as follows: [NPN]-[PPO]-[OOO]-[OON]-[NPN]; When the reference voltage vector is located in region B2 within sector 2, the five-stage switching sequence is designed as follows: [PPN]-[OPO]-[OOO]-[NON]-[PPN]; When the reference voltage vector is located in region A1 within sector 3, the five-stage switching sequence is designed as follows: [NPN]-[OPO]-[NPP]-[NON]-[NPN]; When the reference voltage vector is located in region A2 within sector 3, the five-stage switching sequence is designed as follows: [NPN]-[OPP]-[NPP]-[NOO]-[NPN]; When the reference voltage vector is located in region B1 within sector 3, the five-stage switching sequence is designed as follows: [NPP]-[OPO]-[OOO]-[NON]-[NPP]; When the reference voltage vector is located in region B2 within sector 3, the five-stage switching sequence is designed as follows: [NPN]-[OPP]-[OOO]-[NOO]-[NPN]; When the reference voltage vector is located in region A1 within sector 4, the five-stage switching sequence is designed as follows: [NPP]-[OPP]-[NNP]-[NOO]-[NPP]; When the reference voltage vector is located in region A2 within sector 4, the five-stage switching sequence is designed as follows: [NPP]-[OOP]-[NNP]-[NNO]-[NPP]; When the reference voltage vector is located in region B1 within sector 4, the five-stage switching sequence is designed as follows: [NNP]-[OPP]-[OOO]-[NOO]-[NNP]; When the reference voltage vector is located in region B2 within sector 4, the five-stage switching sequence is designed as follows: [NPP]-[OOP]-[OOO]-[NNO]-[NPP]; When the reference voltage vector is located in region A1 within sector 5, the five-stage switching sequence is designed as follows: [NNP]-[OOP]-[PNP]-[NNO]-[NNP]; When the reference voltage vector is located in region A2 within sector 5, the five-stage switching sequence is designed as follows: [NNP]-[POP]-[PNP]-[ONO]-[NNP]; When the reference voltage vector is located in region B1 within sector 5, the five-stage switching sequence is designed as follows: [PNP]-[OOP]-[OOO]-[NNO]-[PNP]; When the reference voltage vector is located in region B2 within sector 5, the five-stage switching sequence is designed as follows: [NNP]-[POP]-[OOO]-[ONO]-[NNP]; When the reference voltage vector is located in region A1 within sector 6, the five-stage switching sequence is designed as follows: [PNP]-[POP]-[PNN]-[ONO]-[PNP]; When the reference voltage vector is located in region A2 within sector 6, the five-stage switching sequence is designed as follows: [PNP]-[POO]-[PNN]-[ONN]-[PNP]; When the reference voltage vector is located in region B1 within sector 6, the five-stage switching sequence is designed as follows: [PNN]-[POP]-[OOO]-[ONO]-[PNN]; When the reference voltage vector is located in region B2 within sector 6, the five-stage switching sequence is designed as follows: [PNP]-[POO]-[OOO]-[ONN]-[PNP].

8. A coupled three-level inverter DC side capacitor current ripple suppression system, characterized in that: include: A sector division module is configured to determine a region division method of a space vector diagram of a coupled three-level inverter according to a value range of a virtual voltage vector duty cycle allocation factor; A sector determination module is configured to determine the sector and region where the reference voltage vector is located according to the amplitude, phase angle and three-phase output current of the reference voltage vector; The basic voltage vector selection module is configured to select a virtual voltage vector and two basic voltage vectors that are closest to the reference voltage vector according to the sector and area where the reference voltage vector is located, and calculate their duty ratios respectively; The capacitor voltage independent control module is configured to design a controller based on a deadbeat control method according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation, and the actual value of the DC side capacitor voltage deviation, update the small vector duty cycle allocation factor, and realize the capacitor voltage independent control; The drive signal generation module is configured to design a switch sequence based on the updated small vector duty cycle and the sector and region where the reference voltage vector is located, convert the switch sequence into a PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method for suppressing the ripple of the capacitor current on the DC side of a coupled three-level inverter as described in any one of claims 1 to 7 are implemented.

10. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the method for suppressing the ripple of the capacitor current on the DC side of the coupled three-level inverter according to any one of claims 1 to 7 are implemented.

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