Sigma delta AD high-precision temperature sensor circuit

Abstract

A sigma delta AD high-precision temperature sensor circuit relates to the technical field of temperature sensors, the whole sampling period is divided into a plurality of parts through a segmented sampling technology, VBE1 and VBE10 are alternately sampled, sigma delta AD performs integral quantization on the VBE1 and the VBE10, an amplifier is used for realizing charge transfer, namely integral operation, on sampling voltage, and the sampling voltage is used for realizing charge transfer, namely integral operation, on the sampling voltage. The comparator compares an output signal of the amplifier with common-mode voltage VCM and converts the output signal and the common-mode voltage VCM into a digital signal, then the two VBEs are subtracted through the counter in a digital domain, the counter counts the positive number of the positive pulse generated by the VBE10 and counts the negative number of the positive pulse generated by the VBE1, and finally the output result of the counter is converted and calculated to obtain a temperature value. According to the method, the delta VBE operation can be realized in the digital domain, and the problem that the temperature conversion precision is influenced due to the error of the delta VBE made in the analog domain is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of temperature sensors, and in particular to a ΣΔAD high-precision temperature sensor circuit. Background Art

[0002] ΣΔAD is an important module commonly used in temperature sensor circuits. The temperature sensor mainly uses the characteristic that the emitter voltage difference of transistors with different current densities is proportional to the temperature. The ΣΔAD module integrates and quantifies different ΔVBE, and then converts it into temperature through a counter. The main application place is to detect ambient temperature. In the past, temperature sensors sampled different VBEs, made a difference in the analog domain through sampling capacitors, and then quantified ΔVBE. However, when making ΔVBE in the analog domain, no matter what circuit is used to implement it, there will be a certain error in this ΔVBE, which affects the temperature conversion accuracy. Summary of the invention

[0003] The purpose of the present invention is to provide a ΣΔAD high-precision temperature sensor capable of realizing ΔVBE operation in the digital domain, so as to solve the problem that the ΔVBE calculated in the analog domain has errors, thereby affecting the temperature conversion accuracy.

[0004] In order to achieve the above objectives, the technical solution adopted by the present invention is: a ΣΔAD high-precision temperature sensor circuit, whose circuit structure is:

[0005] The reference voltage VREF is connected to the first end of the first switch, the second end of the first switch is connected to the first end of the second switch, the second end of the second switch is connected to the negative input end of the amplifier, and the common mode voltage VCM is connected to the positive input end of the amplifier;

[0006] The second end of the first switch is grounded through the third switch and also grounded through the first capacitor;

[0007] The second end of the second switch is grounded via the fourth switch and the fifth switch in sequence, and the connection point between the fourth switch and the fifth switch is grounded via the second capacitor;

[0008] The second end of the second switch is also connected to the input signal end VIN through the sixth switch and the seventh switch in sequence, and the connection point between the sixth switch and the seventh switch is grounded through the third capacitor;

[0009] The output end of the amplifier is connected to the negative input end of the amplifier through the fourth capacitor and the ninth switch in sequence, and is also connected to the negative input end of the amplifier through the fifth capacitor and the eighth switch in sequence;

[0010] The output of the amplifier is connected to the negative input of the comparator, and the common mode voltage VCM is connected to the positive input of the comparator;

[0011] The output terminal of the comparator is connected to the data input terminal D of the D flip-flop;

[0012] The enable signal EN and the oscillator clock signal OSC are respectively connected to the two input terminals of the first OR gate, the output terminal of the first OR gate and the second control signal CR2 of the state machine are respectively connected to the two input terminals of the third AND gate, the output terminal of the third AND gate is connected to the clock signal terminal of the D flip-flop through the second inverter; the output terminal Q of the D flip-flop is connected to an input terminal of the fourth AND gate; the output terminal of the first OR gate is also connected to the other input terminal of the fourth AND gate through the fifth inverter; the output terminal of the fourth AND gate is connected to the input terminal of the counter; the counter is composed of other digital circuits, and due to the use of the existing technology, the specific circuit structure of the counter is not described in detail in the content of the present invention;

[0013] The output terminal of the fifth inverter is also connected to one input terminal of the fifth AND gate through the seventh inverter, and the enable signal EN is also connected to the other input terminal of the fifth AND gate through the sixth inverter;

[0014] The output end of the fifth AND gate is connected to an input end of the eighth AND gate through the fourth inverter, the output end of the fifth AND gate is also connected to an input end of the ninth AND gate, the output end of the eighth AND gate is connected to another input end of the ninth AND gate, and the output end of the ninth AND gate is connected to another input end of the eighth AND gate;

[0015] The output terminal signal of the eighth AND gate is used as the control signal of the fifth switch and the seventh switch, and the output terminal signal of the ninth AND gate is used as the control signal of the second switch, the fourth switch and the sixth switch;

[0016] The output terminal Q of the D flip-flop is connected to one input terminal of the sixth AND gate through the third inverter, the output terminal Q of the D flip-flop is also connected to one input terminal of the seventh AND gate, and the output terminal of the eighth AND gate is connected to the other input terminals of the sixth AND gate and the seventh AND gate;

[0017] The output terminal signal of the sixth AND gate is used as the control signal of the first switch, and the output terminal signal of the seventh AND gate is used as the control signal of the third switch;

[0018] The first control signal CR1 of the state machine is connected to one input terminal of the first AND gate and is also connected to one input terminal of the second AND gate through the first inverter; the output terminal of the first AND gate is connected to another input terminal of the second AND gate, and the output terminal of the second AND gate is connected to another input terminal of the first AND gate;

[0019] The output terminal signal of the first AND gate is used as the control signal of the ninth switch, and the output terminal signal of the second AND gate is used as the control signal of the eighth switch;

[0020] The input signal terminal VIN is connected to the transistor VBE signal, and the transistor VBE voltage includes alternately appearing VBE1 and VBE10, wherein VBE1 is the voltage generated when one times the bias current flows through the BE junction of the transistor, and VBE10 is the voltage when ten times the bias current flows through the BE junction of the transistor.

[0021] The circuit of the present invention can realize a new type of VBE sampling technology, that is, a digital circuit controls VBE sampling, and through the segmented sampling technology, the entire sampling period is divided into multiple parts, and VBE1 and VBE10 are sampled alternately. ΣΔAD integrates and quantizes VBE1 and VBE10 respectively, wherein the amplifier is used to realize charge transfer of the sampled voltage, that is, to perform integration operation, and the comparator compares the output signal of the amplifier with the common mode voltage VCM and converts it into a digital signal.

[0022] Then, the counter is used in the digital domain to realize the difference between the two VBEs. The counter counts the positive pulses generated by VBE10, and each positive pulse count increases by 1. The counter counts the negative pulses generated by VBE1, and each positive pulse count decreases by 1. Finally, the counter output result is converted and calculated to obtain the temperature value.

[0023] The reason for using alternate sampling is that the working cycle of ΣΔAD is particularly long. If the alternate sampling working mode is not used, the temperatures of the two VBEs will be different, affecting the conversion accuracy.

[0024] Furthermore, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch and the ninth switch are all switch tubes made of NMOS tubes, and when the control signal is at a high level, the corresponding switch is turned on.

[0025] Furthermore, within one sampling period, the control signal of the ninth switch appears at a high level 10 times, and correspondingly, the control signal of the eighth switch appears at a low level 10 times, that is, the entire sampling period is divided into 10 parts.

[0026] Furthermore, the input voltage of the input signal terminal VIN is 5*VBE-4K*VREF, where K is a fixed proportional coefficient given by the input voltage generating circuit. This input voltage generating circuit is implemented using an additional analog circuit in the prior art, and will not be described in detail in the present invention.

[0027] Furthermore, the control signal of the ninth switch and the control signal of the eighth switch also alternately control the VBE voltage of the transistor. When the control signal of the ninth switch is at a high level, ten times the bias current flows through the BE junction of the transistor. At this time, the input voltage of the input signal terminal VIN is VIN1=5*VBE10-4K*VREF. When the control signal of the eighth switch is at a high level, one times the bias current flows through the BE junction of the transistor. At this time, the input voltage of the input signal terminal VIN is VIN2=5*VBE1-4K*VREF.

[0028] The beneficial effects of the present invention are:

[0029] Through segmented sampling technology, VBE1 and VBE10 are sampled alternately multiple times, and the difference between the two is realized in the digital domain. This avoids the disadvantage that the ΣΔAD conversion time is too long, resulting in different temperatures for the two VBEs. At the same time, it also solves the problem that the ΔVBE made in the analog domain is not accurate enough, affecting the conversion accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the circuit structure of an embodiment of the present invention;

[0031] Figure 2 is a waveform diagram of each switch control signal according to an embodiment of the present invention;

[0032] Figure 3 This is an enlarged view of a local waveform when the S9 control signal is high and the S8 control signal is low in an embodiment of the present invention;

[0033] Figure 4 This is an enlarged view of a local waveform when the S9 control signal is low and the S8 control signal is high in an embodiment of the present invention;

[0034] Figure 5 Schematic diagram of sampling phase and charge transfer phase of VIN1 according to an embodiment of the present invention;

[0035] Figure 6 Schematic diagram of the sampling phase and charge transfer phase of VIN2 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] Figure 1 A specific embodiment of the present invention is a ΣΔAD high-precision temperature sensor circuit, whose circuit structure is:

[0038] The reference voltage VREF is connected to the first end of the first switch S1, the second end of the first switch S1 is connected to the first end of the second switch S2, the second end of the second switch S2 is connected to the negative input end of the amplifier AMP, and the common mode voltage VCM is connected to the positive input end of the amplifier AMP;

[0039] A second end of the first switch S1 is grounded through a third switch S3 and is also grounded through a first capacitor C1;

[0040] The second end of the second switch S2 is grounded via the fourth switch S4 and the fifth switch S5 in sequence, and the connection point between the fourth switch S4 and the fifth switch S5 is grounded via the second capacitor C2;

[0041] The second end of the second switch S2 is also connected to the input signal end VIN through the sixth switch S6 and the seventh switch S7 in sequence, and the connection point between the sixth switch S6 and the seventh switch S7 is grounded through the third capacitor C3;

[0042] The output end of the amplifier AMP is connected to the negative input end of the amplifier AMP through the fourth capacitor C4 and the ninth switch S9 in sequence, and is also connected to the negative input end of the amplifier AMP through the fifth capacitor C5 and the eighth switch S8 in sequence;

[0043] The output terminal of the amplifier AMP is connected to the negative input terminal of the comparator COMP, and the common mode voltage VCM is connected to the positive input terminal of the comparator COMP;

[0044] The output terminal of the comparator COMP is connected to the data input terminal D of the D flip-flop DFF;

[0045] The enable signal EN and the oscillator clock signal OSC are respectively connected to two input terminals of the first OR gate OR1, the output terminal of the first OR gate OR1 and the second control signal CR2 of the state machine are respectively connected to two input terminals of the third AND gate AND3, the output terminal of the third AND gate AND3 is connected to the clock signal terminal of the D flip-flop DFF through the second inverter INV2; the output terminal Q of the D flip-flop DFF is connected to one input terminal of the fourth AND gate AND4; the output terminal of the first OR gate OR1 is also connected to the other input terminal of the fourth AND gate AND4 through the fifth inverter INV5; the output terminal of the fourth AND gate AND4 is connected to the input terminal of the counter;

[0046] The output end of the fifth inverter INV5 is also connected to one input end of the fifth AND gate AND5 through the seventh inverter INV7, and the enable signal EN is also connected to the other input end of the fifth AND gate AND5 through the sixth inverter INV6;

[0047] The output end of the fifth AND gate AND5 is connected to one input end of the eighth AND gate AND8 through the fourth inverter INV4, the output end of the fifth AND gate AND5 is also connected to one input end of the ninth AND gate AND9, the output end of the eighth AND gate AND8 is connected to the other input end of the ninth AND gate AND9, and the output end of the ninth AND gate AND9 is connected to the other input end of the eighth AND gate AND8;

[0048] The output terminal signal of the eighth AND gate AND8 is used as the control signal of the fifth switch S5 and the seventh switch S7, and the output terminal signal of the ninth AND gate AND9 is used as the control signal of the second switch S2, the fourth switch S4 and the sixth switch S6;

[0049] The output terminal Q of the D flip-flop DFF is connected to one input terminal of the sixth AND gate AND6 through the third inverter INV3, the output terminal Q of the D flip-flop DFF is also connected to one input terminal of the seventh AND gate AND7, and the output terminal of the eighth AND gate AND8 is connected to the other input terminals of the sixth AND gate AND6 and the seventh AND gate AND7;

[0050] The output terminal signal of the sixth AND gate AND6 is used as the control signal of the first switch S1, and the output terminal signal of the seventh AND gate AND7 is used as the control signal of the third switch S3;

[0051] The first control signal CR1 of the state machine is connected to one input terminal of the first AND gate AND1 and is also connected to one input terminal of the second AND gate AND2 through the first inverter INV1; the output terminal of the first AND gate AND1 is connected to the other input terminal of the second AND gate AND2, and the output terminal of the second AND gate AND2 is connected to the other input terminal of the first AND gate AND1;

[0052] The output terminal signal of the first AND gate AND1 is used as the control signal of the ninth switch S9, and the output terminal signal of the second AND gate AND2 is used as the control signal of the eighth switch S8;

[0053] The input signal terminal VIN is connected to the transistor VBE signal, and the transistor VBE voltage includes alternately appearing VBE1 and VBE10, wherein VBE1 is the voltage generated when one times the bias current flows through the BE junction of the transistor, and VBE10 is the voltage when ten times the bias current flows through the BE junction of the transistor.

[0054] In this embodiment, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8 and the ninth switch S9 are all switch tubes made of NMOS tubes. When the control signal is at a high level, the corresponding switch is turned on.

[0055] By setting a suitable state machine first control signal CR1, within one sampling period, the control signal of the ninth switch S9 appears high 10 times, and correspondingly, the control signal of the eighth switch S8 appears low 10 times, that is, the entire sampling period is divided into 10 parts.

[0056] The input voltage of the input signal terminal VIN is 5*VBE-4K*VREF, where K is a fixed proportional coefficient given by the input voltage generating circuit.

[0057] In this embodiment, the control signal of the ninth switch S9 and the control signal of the eighth switch S8 also alternately control the VBE voltage of the transistor. When the control signal of the ninth switch S9 is at a high level, ten times the bias current flows through the BE junction of the transistor. At this time, the input voltage of the input signal terminal VIN is VIN1=5*VBE10-4K*VREF. When the control signal of the eighth switch S8 is at a high level, one times the bias current flows through the BE junction of the transistor. At this time, the input voltage of the input signal terminal VIN is VIN2=5*VBE1-4K*VREF.

[0058] Figure 2 The figure shows the signal waveform that controls the gate terminal of each NMOS switch tube in the circuit. It can be seen from the figure that the switch signals that control the two integral capacitors, namely the fourth capacitor C4 and the fifth capacitor C5 to access the circuit are the control signal of S9 and the control signal of S8 respectively. It can be said that C4 and C5 are alternately connected to the circuit 10 times. And the control signal of S9 and the control signal of S8 also alternately control the voltage of the transistor VBE. When the S9 control signal is high, C4 is connected to the circuit, and at the same time, ten times the bias current flows through the BE junction of the transistor, that is, VBE10 is connected to the circuit, that is, VIN1=5*VBE10-4K*VREF, and the integration result is stored in C4. When the S8 control signal is high, C5 is connected to the circuit, and at the same time, one times the bias current flows through the BE junction of the transistor, that is, VBE1 is connected to the circuit, that is, VIN2=5*VBE1-4K*VREF, and the integration result is stored in C5. VIN1 and VIN2 are connected to the circuit 10 times respectively, and 240 charge transfers occur each time; that is, during the entire conversion process, VIN1 and VIN2 undergo 2400 charge transfers respectively.

[0059] Figure 3 The figure shows an enlarged view of a local waveform when the S9 control signal is high and the S8 control signal is low. The waveforms of the control signals S1 to S7 in the figure can be obtained by setting a suitable state machine second control signal CR2, enable signal EN, and oscillator clock signal OSC.

[0060] according to Figure 3 The phase relationship of VIN1 can be simplified to Figure 5 The sampling process and integration process shown in Figure 2. There are two sampling phases in the conversion process, and the charge transfer phase is the same (that is, the integration process). Figure 5As shown, when VIN1 is in sampling phase 1, the switch tubes S1, S5, S7, S9 are in a closed conduction state, and S2, S3, S4, S6, S8 are in a disconnected state. In the charge transfer phase of VIN1, S2, S4, S6, S9 are in a closed conduction state, and S1, S3, S5, S7, S8 are in a disconnected state. During the charge transfer process, the total amount of charge transferred is: VCM (C1 + C2 + C3) - VREF * C1 - VIN1 * C3. When VIN1 is in sampling phase 2, the switch tubes S3, S5, S7, S9 are in a closed conduction state, and S1, S2, S4, S6, S8 are in a disconnected state. In the charge transfer phase of VIN1, S2, S4, S6, S9 are in a closed conduction state, and S1, S3, S5, S7, S8 are in a disconnected state. In the charge transfer process, the total amount of charge transferred is: VCM (C1 + C2 + C3) - VIN1 * C3. Assuming that VIN1 has M1 times from sampling phase 2 to charge transfer phase during the entire working process, the total number of conversions is 2400 times. The following equation can be obtained by the law of conservation of charge:

[0061] (2400-M1)[VCM(C1+C2+C3)-VREF*C1-VIN1*C3]+M1[VCM(C1+C2+C3)-VI N1*C3]=0

[0062] In this embodiment, C1=6C, C2=5C, C3=10C, C4=C5=20C, from which the following equation can be derived:

[0063] M1=2400*(6VREF+10VIN1-21*VCM) / 6VREF

[0064] Where VIN1 = 5*VBE10-4K*VREF, the value obtained by M1 is the value that the counter needs to count positively, that is, the number of positive pulses generated by VBE10, the counter counts positively (+1).

[0065] Similarly, Figure 4 The figure shows the enlarged view of the local waveform when the S9 control signal is low and the S8 control signal is high. According to the phase relationship of the figure, the entire sampling process of VIN2 can be simplified as follows: Figure 6 The sampling process and integration process shown in Figure 2. There are two sampling phases in the conversion process, and the charge transfer phase is the same (that is, the integration process). Figure 6As shown, when VIN2 is in sampling phase 1, the switch tubes S1, S5, S7, S8 are in a closed conduction state, and S2, S3, S4, S6, S9 are in a disconnected state. In the charge transfer phase of VIN1, S2, S4, S6, S8 are in a closed conduction state, and S1, S3, S5, S7, S9 are in a disconnected state. During the charge transfer process, the total amount of charge transferred is: VCM (C1 + C2 + C3) - VREF * C1 - VIN2 * C3. When VIN2 is in sampling phase 2, the switch tubes S3, S5, S7, S8 are in a closed conduction state, and S1, S2, S4, S6, S9 are in a disconnected state. In the charge transfer phase of VIN2, S2, S4, S6, S8 are in a closed conduction state, and S1, S3, S5, S7, S9 are in a disconnected state. In the process of charge transfer, the total amount of charge transferred is: VCM (C1 + C2 + C3) - VIN2 * C3. Assuming that VIN2 has M2 times from sampling phase 2 to charge transfer phase during the entire working process, the total number of conversions is 2400 times. The following equation can be obtained by the law of conservation of charge:

[0066] (2400-M2)[VCM(C1+C2+C3)-VREF*C1-VIN2*C3]+M2[VCM(C1+C2+C3)-VI N2*C3]=0

[0067] Among them, C1=6C, C2=5C, C3=10C, C4=C5=20C, from this equation we can deduce:

[0068] M2=2400*(6VREF+10VIN2-21*VCM) / 6VREF

[0069] Where VIN2 = 5*VBE1-4K*VREF, the value obtained by M2 is the value that the counter needs to count negative numbers. That is, the number of positive pulses generated by VBE1 mentioned above, the counter counts negative numbers (-1).

[0070] It should be noted that the counter is a 10-bit counter that outputs in the form of two's complement. That is, 1LSB is 0.25°C, so the counter result divided by 4 is the true temperature value. It is also necessary to subtract 273 from the fixed setting of the counter to convert the temperature data from Kelvin to Celsius.

[0071] In this way, the temperature value T = M1-M2 = 24000 (VIN1-VIN2) / 4*6VREF-273

[0072] in:

[0073] VIN1=5*VBE10-4K*VREF

[0074] VIN2 = 5*VBE1-4K*VREF.

[0075] Finally, T=5000(VBE10-VBE1) / VREF-273=5000*ΔVBE / VREF-273. In this embodiment, VREF=1V.

[0076] It can be seen from the working principle and process of the above embodiment that VBE10 and VBE are sampled 10 times through the segmented sampling technology, and the difference between the two is realized in the digital domain, thereby avoiding the disadvantage that the ΣΔAD conversion time is too long, resulting in different temperatures for the two VBEs. At the same time, it also solves the problem that the ΔVBE made in the analog domain is not accurate enough, affecting the conversion accuracy.

Claims

1. A ΣΔAD high-precision temperature sensor circuit, characterized in that: A reference voltage VREF is connected to a first end of a first switch (S1), a second end of the first switch (S1) is connected to a first end of a second switch (S2), a second end of the second switch (S2) is connected to a negative input end of an amplifier (AMP), and a common mode voltage VCM is connected to a positive input end of the amplifier (AMP); The second end of the first switch (S1) is grounded through the third switch (S3) and is also grounded through the first capacitor (C1); The second end of the second switch (S2) is grounded via the fourth switch (S4) and the fifth switch (S5) in sequence, and the connection point between the fourth switch (S4) and the fifth switch (S5) is grounded via the second capacitor (C2); The second end of the second switch (S2) is also connected to the input signal end VIN through the sixth switch (S6) and the seventh switch (S7) in sequence, and the connection point between the sixth switch (S6) and the seventh switch (S7) is grounded through the third capacitor (C3); The output end of the amplifier (AMP) is connected to the negative input end of the amplifier (AMP) through a fourth capacitor (C4) and a ninth switch (S9) in sequence, and is also connected to the negative input end of the amplifier (AMP) through a fifth capacitor (C5) and an eighth switch (S8) in sequence; The output terminal of the amplifier (AMP) is connected to the negative input terminal of the comparator (COMP), and the common mode voltage VCM is connected to the positive input terminal of the comparator (COMP); The output terminal of the comparator (COMP) is connected to the data input terminal D of the D flip-flop (DFF); The enable signal EN and the oscillator clock signal OSC are respectively connected to two input terminals of a first OR gate (OR1); the output terminal of the first OR gate (OR1) and the second control signal CR2 of the state machine are respectively connected to two input terminals of a third AND gate (AND3); the output terminal of the third AND gate (AND3) is connected to the clock signal terminal of a D flip-flop (DFF) through a second inverter (INV2); the output terminal Q of the D flip-flop (DFF) is connected to an input terminal of a fourth AND gate (AND4); the output terminal of the first OR gate (OR1) is also connected to another input terminal of a fourth AND gate (AND4) through a fifth inverter (INV5); the output terminal of the fourth AND gate (AND4) is connected to the input terminal of a counter; The output end of the fifth inverter (INV5) is also connected to an input end of the fifth AND gate (AND5) through the seventh inverter (INV7), and the enable signal EN is also connected to the other input end of the fifth AND gate (AND5) through the sixth inverter (INV6); The output end of the fifth AND gate (AND5) is connected to an input end of the eighth AND gate (AND8) through the fourth inverter (INV4), the output end of the fifth AND gate (AND5) is also connected to an input end of the ninth AND gate (AND9), the output end of the eighth AND gate (AND8) is connected to the other input end of the ninth AND gate (AND9), and the output end of the ninth AND gate (AND9) is connected to the other input end of the eighth AND gate (AND8); The output terminal signal of the eighth AND gate (AND8) is used as the control signal of the fifth switch (S5) and the seventh switch (S7), and the output terminal signal of the ninth AND gate (AND9) is used as the control signal of the second switch (S2), the fourth switch (S4) and the sixth switch (S6); The output terminal Q of the D flip-flop (DFF) is connected to an input terminal of the sixth AND gate (AND6) through the third inverter (INV3), the output terminal Q of the D flip-flop (DFF) is also connected to an input terminal of the seventh AND gate (AND7), and the output terminal of the eighth AND gate (AND8) is connected to the other input terminals of the sixth AND gate (AND6) and the seventh AND gate (AND7); The output terminal signal of the sixth AND gate (AND6) is used as the control signal of the first switch (S1), and the output terminal signal of the seventh AND gate (AND7) is used as the control signal of the third switch (S3); The first control signal CR1 of the state machine is connected to an input terminal of the first AND gate (AND1) and is also connected to an input terminal of the second AND gate (AND2) through the first inverter (INV1); the output terminal of the first AND gate (AND1) is connected to the other input terminal of the second AND gate (AND2), and the output terminal of the second AND gate (AND2) is connected to the other input terminal of the first AND gate (AND1); The output terminal signal of the first AND gate (AND1) is used as the control signal of the ninth switch (S9), and the output terminal signal of the second AND gate (AND2) is used as the control signal of the eighth switch (S8); The input signal terminal VIN is connected to the transistor VBE signal, and the transistor VBE voltage includes alternately appearing VBE1 and VBE10, wherein VBE1 is the voltage generated when one times the bias current flows through the BE junction of the transistor, and VBE10 is the voltage when ten times the bias current flows through the BE junction of the transistor.

2. The ΣΔAD high-precision temperature sensor circuit according to claim 1, characterized in that: The first switch (S1), the second switch (S2), the third switch (S3), the fourth switch (S4), the fifth switch (S5), the sixth switch (S6), the seventh switch (S7), the eighth switch (S8) and the ninth switch (S9) are all switch tubes made of NMOS tubes. When the control signal is at a high level, the corresponding switch is turned on.

3. The ΣΔAD high-precision temperature sensor circuit according to claim 2, characterized in that: In one sampling period, the control signal of the ninth switch (S9) appears at a high level 10 times, and correspondingly, the control signal of the eighth switch (S8) appears at a low level 10 times.

4. The ΣΔAD high-precision temperature sensor circuit according to claim 1, characterized in that: The input voltage of the input signal terminal VIN is 5*VBE-4K*VREF, where K is a fixed proportional coefficient given by the input voltage generating circuit.

5. The ΣΔAD high-precision temperature sensor circuit according to claim 4, characterized in that: The control signal of the ninth switch (S9) and the control signal of the eighth switch (S8) also alternately control the VBE voltage of the transistor. When the control signal of the ninth switch (S9) is at a high level, ten times the bias current flows through the BE junction of the transistor. At this time, the input voltage of the input signal terminal VIN is VIN1=5*VBE10-4K*VREF. When the control signal of the eighth switch (S8) is at a high level, one times the bias current flows through the BE junction of the transistor. At this time, the input voltage of the input signal terminal VIN is VIN2=5*VBE1-4K*VREF.

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