Circuit board structure with embedded fine lines and its manufacturing method

Abstract

This application discloses a circuit board structure with embedded fine lines and a method for manufacturing the same. The circuit board structure includes at least one circuit layer, a latching structure, and at least one insulating layer and one dielectric layer stacked along the thickness direction. The circuit layer includes fine lines, with a portion of the circuit layer embedded in the insulating layer and another portion embedded in the dielectric layer. The side of the circuit layer facing away from the dielectric layer is exposed from the surface of the insulating layer facing away from the dielectric layer. The latching structure is embedded in the dielectric layer and connects to the fine lines. By partially embedding the fine lines in the insulating layer and partially embedding them in the dielectric layer, and embedding the latching structure within the dielectric layer to connect the fine lines, the adhesion of the fine lines can be greatly enhanced.

Description

Technical Field

[0001] This application relates to the field of circuit boards, and more particularly to circuit board structures with embedded fine lines and methods for manufacturing the same. Background Technology

[0002] To meet the requirements of high-density integration, the width of lines on circuit boards is getting smaller and smaller, but thin lines have poor adhesion and there is a risk of lines floating off. Summary of the Invention

[0003] To address the shortcomings of the existing technology, this application provides a method for manufacturing a circuit board structure with embedded fine lines.

[0004] In addition, it is necessary to provide a circuit board structure with embedded fine lines.

[0005] This application provides a circuit board structure with embedded fine lines. The circuit board structure includes at least one circuit layer, a latching structure, and at least one insulating layer and one dielectric layer stacked along the thickness direction. The circuit layer includes fine lines, a portion of the circuit layer is embedded in the insulating layer, and another portion of the circuit layer is embedded in the dielectric layer. The side of the circuit layer facing away from the dielectric layer is exposed by the surface of the insulating layer facing away from the dielectric layer. The latching structure is embedded in the dielectric layer and connects to the fine lines.

[0006] In some embodiments, the width of the end of the thin line facing the dielectric layer is not less than the width of the end of the thin line facing the insulating layer.

[0007] In some embodiments, the width of the end of the latching structure connected to the thin wire is greater than the width of the thin wire.

[0008] In some embodiments, the circuit board structure includes two circuit layers, two latching structures, and two insulating layers. The two insulating layers are respectively disposed on opposite sides of the dielectric layer, the two latching structures are facing each other and correspondingly disposed, and the two circuit layers are correspondingly disposed.

[0009] In some embodiments, each of the circuit layers further includes pads, and the dielectric layer has a conductor that electrically connects two opposite pads.

[0010] In some embodiments, the surface of the circuit layer facing away from the dielectric layer is flush with the surface of the insulating layer facing away from the dielectric layer.

[0011] This application also provides a method for manufacturing a circuit board structure with embedded fine lines, comprising the following steps:

[0012] An insulating substrate is provided, and an insulating layer is stacked on one side of the insulating substrate along the thickness direction;

[0013] Multiple openings are formed through the insulating layer;

[0014] A circuit layer is formed by electroplating within the opening, the circuit layer comprising fine lines;

[0015] A locking structure is formed on the side of the insulating layer opposite to the insulating carrier plate, and the locking structure is connected to the fine line.

[0016] A portion of the insulating layer is removed along the thickness direction, creating a gap between the latching structure and the insulating layer to obtain a circuit board.

[0017] A dielectric layer is laminated to one side of the circuit board, the dielectric layer fills the gap and adheres to the insulating layer, and the locking structure and part of the circuit layer are embedded in the dielectric layer;

[0018] Remove the insulating substrate to obtain a circuit board structure with embedded fine lines.

[0019] In some embodiments, the step of "laminating a dielectric layer on one side of the circuit board" includes:

[0020] A circuit substrate, a dielectric layer, and another circuit substrate are laminated together, with the two fine lines facing each other and correspondingly arranged during lamination; after lamination, an insulating layer is bonded to each of the opposite sides of the dielectric layer.

[0021] In some embodiments, the dielectric layer contains a conductor, and the circuit layer further includes pads spaced apart from the fine lines;

[0022] The step of "laminating one of the circuit substrates, one of the dielectric layers, and another of the circuit substrates" includes:

[0023] During stacking, each end of the conductor corresponds to one of the pads; after lamination, the conductor is electrically connected to the two pads.

[0024] In some implementations, the step of "creating a plurality of openings through the insulating layer" includes:

[0025] The insulating layer is exposed and developed to form a plurality of openings, wherein the width of the opening on the side away from the insulating substrate is not less than the width of the opening on the side facing the insulating substrate.

[0026] Compared to existing technologies, the circuit board structure with embedded fine lines provided in this application greatly enhances the adhesion of the fine lines by embedding part of the fine lines in the insulating layer and part of them in the dielectric layer, and by embedding a locking structure in the dielectric layer to connect the fine lines. Attached Figure Description

[0027] Figure 1 This is a cross-sectional schematic diagram of an insulating carrier plate provided in an embodiment of this application.

[0028] Figure 2 for Figure 1 The diagram shows a cross-section of the insulating carrier plate after the insulating layer has been applied.

[0029] Figure 3 In order to be in Figure 2 The diagram shows a cross-section of the insulation layer after an opening has been created.

[0030] Figure 4 In order to be in Figure 3 The diagram shows a cross-section of the opening after copper plating has been used to form the circuit layer.

[0031] Figure 5 In order to be in Figure 4 The diagram shows a cross-sectional view of the circuit layer after it forms a locking structure away from the surface of the insulating substrate.

[0032] Figure 6 To remove a portion from the side opposite to the insulating carrier plate Figure 5 A schematic cross-sectional view of the circuit board obtained after the insulation layer is shown.

[0033] Figure 7 To be Figure 6 The circuit board, a dielectric layer, and another shown Figure 6 The diagram shows a cross-sectional view of the stacked circuit board substrate.

[0034] Figure 8 To be Figure 7 The diagram shows a cross-sectional view of the circuit board structure obtained by laminating the circuit board substrate, a dielectric layer, and removing the insulating substrate.

[0035] Explanation of main component symbols

[0036] Circuit board structure 100

[0037] Insulating carrier plate 10

[0038] Insulation layer 11

[0039] Opening 112

[0040] Line layer 20

[0041] Copper layer 201

[0042] Fine Line 22

[0043] Pad 24

[0044] Locking structure 30

[0045] gap R

[0046] Circuit board 1

[0047] Dielectric layer 4

[0048] Conductor 42

[0049] Thickness direction A

[0050] Widths W1 and W2

[0051] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0052] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0053] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. When a component is said to be "set on" another component, it can be directly set on the other component or there may be an intervening component.

[0054] Please see Figures 1 to 8 This application provides a method for manufacturing a circuit board structure 100 with embedded fine lines, comprising the following steps:

[0055] Step S1, please refer to Figure 1 An insulating carrier plate 10 is provided.

[0056] The insulating carrier plate 10 serves only as a temporary load-bearing material and may be made of glass or ceramic.

[0057] In some embodiments, the insulating carrier plate 10 may be a peelable insulating carrier plate for easy subsequent removal.

[0058] For step S2, please refer to [link / reference]. Figure 2 An insulating layer 11 is provided on one side of the insulating carrier plate 10.

[0059] Specifically, the insulating substrate 10 has a thickness direction A, and the insulating layer 11 can be formed by printing photosensitive resin on one side of the insulating substrate 10 along the thickness direction A. That is, the insulating layer 11 can be patterned by exposure and development.

[0060] In other embodiments, a photoresist layer may be attached to one side of the insulating carrier plate 10 instead of the insulating layer 11.

[0061] Step S3, please refer to Figure 3 A plurality of openings 112 are formed through the insulating layer 11, and the width of the opening 112 on the side away from the insulating carrier plate 10 is not less than the width of the opening 112 on the side facing the insulating carrier plate 10.

[0062] Specifically, according to a predetermined size, an exposure and development process can be performed on a predetermined area of ​​the insulating layer 11 to form a plurality of openings 112 of a specific size, the openings 112 penetrating the insulating layer 11 along the thickness direction A. The width of the openings 112 formed by exposure and development is uniform along the thickness direction A.

[0063] For step S4, please refer to [link / reference]. Figure 4 A copper plating is performed inside the opening 112 to form a circuit layer 20, the circuit layer 20 including spaced fine lines 22 and pads 24.

[0064] Specifically, the circuit layer 20 is formed within the opening 112 using chemical plating and electroplating processes. A copper layer 201 is also formed on the surface of the insulating layer 11 facing away from the insulating substrate 10.

[0065] Traditional techniques using laser-drilled blind holes followed by electroplating to form fine lines typically result in a wider top and narrower bottom, meaning the end used for connection is narrower. This narrowness leads to reduced adhesion. However, in this application, the fine lines 22 are formed by copper plating within the opening 112 created through exposure and development. The width of the end of the fine line 22 facing away from the insulating substrate 10 is not less than the width of the end facing the insulating substrate 10, effectively improving the adhesion of the fine lines 22. In this embodiment, the width W1 of the fine lines 22 formed within the opening 112 is uniform along the thickness direction A.

[0066] For step S5, please refer to [link / reference]. Figure 5 Corresponding to the fine line 22, a locking structure 30 is formed on the surface of the insulating layer 11 opposite to the insulating carrier plate 10.

[0067] The latching structure 30 can be one or more. When there is one latching structure 30, a single latching structure 30 can simultaneously connect to multiple thin wires 22. When there are multiple latching structures 30, each latching structure 30 is connected to one thin wire 22. The width W2 of the end of the latching structure 30 connected to the thin wire 22 is greater than the width W1 of the thin wire 22. The latching structure 30 can be, but is not limited to, a rectangle, a triangle, or other irregular shapes.

[0068] Specifically, the locking structure 30 can be formed by attaching a photosensitive dry film to the surface of the copper layer 201, followed by exposure, development, electroplating, and other steps, and then removing the copper layer 201 by film removal and rapid etching.

[0069] For step S6, please refer to [link / reference]. Figure 6 A portion of the insulating layer 11 is removed along the thickness direction A, so that a gap R is formed between the insulating layer 11 and the locking structure 30, thereby obtaining the circuit board 1.

[0070] Specifically, a portion of the insulating layer 11 can be removed using a plasma etching process on the side of the insulating layer 11 facing away from the insulating substrate 10. The surface of the circuit layer 20 facing away from the insulating substrate 10 protrudes from the surface of the insulating layer 11 facing away from the insulating substrate 10.

[0071] For step S7, please refer to [link / reference]. Figure 7 and Figure 8 A circuit board 1, a dielectric layer 4, and another circuit board 1 are laminated together, and the insulating carrier 10 is removed to obtain a circuit board structure 100 with embedded fine lines. During lamination, the latching structures 30 of the two circuit boards 1 face each other and are correspondingly arranged towards the dielectric layer 4; after lamination, the dielectric layer 4 fills the gap R and bonds the two insulating layers 11, thereby embedding the latching structure 30 and part of the circuit layer 20 within the dielectric layer 4.

[0072] The dielectric layer 4 is further provided with a conductive body 42. When stacked, the conductive body 42 is provided corresponding to the pad 24. After pressing, the conductive body 42 electrically connects the two pads 24.

[0073] In some embodiments, the dielectric layer 4 may be a prepreg (PP) or other dielectric material layer, and the conductor 42 may be copper paste.

[0074] Please see Figure 8An embodiment of this application also provides a circuit board structure 100 with embedded fine lines. The circuit board structure 100 includes at least one circuit layer 20, a latching structure 30, and an insulating layer 11 and a dielectric layer 4 stacked along the thickness direction A. Part of the circuit layer 20 is embedded in the insulating layer 11, and another part is embedded in the dielectric layer 4. The latching structure 30 is embedded in the dielectric layer 4 and connected to the circuit layer 20.

[0075] The circuit layer 20 includes thin lines 22, and the locking structure 30 is connected to the side of the thin lines 22 facing away from the insulating layer 11. The surface of the circuit layer 20 facing away from the dielectric layer 4 is approximately flush with the surface of the insulating layer 11 facing away from the dielectric layer 4. The width of the end of the thin lines 22 facing the dielectric layer 4 is not less than the width of the end of the thin lines 22 facing away from the dielectric layer 4. Preferably, the width W1 of the thin lines 22 is uniform along the thickness direction A. The width W2 of the locking structure 30 connected to the end of the thin lines 22 is greater than the width W1 of the thin lines 22. The locking structure 30 may be, but is not limited to, rectangular, triangular, or other irregular shapes.

[0076] In some embodiments, the latching structure 30 may be one or more. When there is one latching structure 30, a single latching structure 30 may be connected to multiple thin wires 22 at the same time. When there are multiple latching structures 30, each latching structure 30 is connected to one thin wire 22.

[0077] In one embodiment, the circuit board structure 100 includes two circuit layers 20, two corresponding latching structures 30, and two insulating layers 11. The two insulating layers 11 are respectively disposed on opposite sides of the dielectric layer 4. The two circuit layers 20 are facing each other and are disposed correspondingly. The two latching structures 30 are facing each other and are disposed correspondingly.

[0078] The circuit layer 20 also includes pads 24 spaced apart from the fine lines 22, and a conductor 42 is provided through the dielectric layer 4, which electrically connects two opposite pads 24.

[0079] In the circuit board structure 100 of this application, part of the circuit layer 20 is embedded in the insulating layer 11, and another part of the circuit layer 20 is embedded in the dielectric layer 4. The widths of the two ends of the fine lines 22 are the same, and the locking structure 30 is embedded in the dielectric layer 4, which can greatly enhance the bonding force between the fine lines 22 and the dielectric layer 4.

[0080] The above description is merely an optimized implementation of this application, and its application should not be limited to this specific implementation. Other modifications and alterations made by those skilled in the art based on the technical concept of this application should fall within the protection scope of this application.

Claims

1. A circuit board structure with embedded fine lines, characterized in that, The circuit board structure includes at least one circuit layer, a latching structure, and at least one insulating layer and one dielectric layer stacked along the thickness direction. The circuit layer includes fine lines, a portion of which is embedded in the insulating layer and another portion is embedded in the dielectric layer. The side of the circuit layer facing away from the dielectric layer is exposed from the surface of the insulating layer facing away from the dielectric layer. The latching structure is embedded in the dielectric layer and connects to the fine lines. The width of the end of the fine lines facing the dielectric layer is not less than the width of the end of the fine lines facing the insulating layer.

2. The circuit board structure as described in claim 1, characterized in that, The width of the end of the latching structure connected to the thin wire is greater than the width of the thin wire.

3. The circuit board structure as described in claim 1, characterized in that, The circuit board structure includes two circuit layers, two latching structures, and two insulating layers. The two insulating layers are respectively disposed on opposite sides of the dielectric layer, the two latching structures are facing each other and correspondingly disposed, and the two circuit layers are correspondingly disposed.

4. The circuit board structure as described in claim 3, characterized in that, Each of the circuit layers further includes pads, and the dielectric layer has a conductor that electrically connects two opposite pads.

5. The circuit board structure as described in claim 1, characterized in that, The surface of the circuit layer facing away from the dielectric layer is flush with the surface of the insulating layer facing away from the dielectric layer.

6. A method for manufacturing a circuit board structure with embedded fine lines, characterized in that, Including the following steps: An insulating substrate is provided, and an insulating layer is stacked on one side of the insulating substrate along the thickness direction; The insulating layer is exposed and developed to form multiple openings, and the width of the opening on the side away from the insulating substrate is not less than the width of the opening on the side facing the insulating substrate. A circuit layer is formed by electroplating within the opening, the circuit layer comprising fine lines; A locking structure is formed on the side of the insulating layer opposite to the insulating carrier plate, and the locking structure is connected to the fine line. A portion of the insulating layer is removed along the thickness direction, creating a gap between the latching structure and the insulating layer to obtain a circuit board. A dielectric layer is laminated on one side of the circuit board, the dielectric layer fills the gap and adheres to the insulating layer, and the locking structure and part of the circuit layer are embedded in the dielectric layer; Remove the insulating substrate to obtain the circuit board structure with embedded fine lines.

7. The manufacturing method as described in claim 6, characterized in that, The step of "laminating a dielectric layer on one side of the circuit board" includes: A circuit substrate, a dielectric layer, and another circuit substrate are stacked and pressed together, wherein, during stacking, the two fine lines face each other and are arranged correspondingly; after pressing, an insulating layer is respectively bonded to the opposite sides of the dielectric layer.

8. The manufacturing method as described in claim 7, characterized in that, The dielectric layer contains a conductor, and the circuit layer also includes pads spaced apart from the fine lines. The step of "laminating one of the circuit substrates, one of the dielectric layers, and another of the circuit substrates" includes: During stacking, each end of the conductor corresponds to one of the pads; after lamination, the conductor connects the two pads.

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